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© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA

All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA

1

2008

LETI MODERN Contribution to WP5

• Contribution to WP5.2: Demonstrator : design, implementation and characterization

• Status :– Design of a full chip in 32 nm : LoCoMoTIV– Full AVFS architecture– Including WP3 and WP4 IP contributions– PG tape : December

• Deliverables:– D5.2.2: Test chip simulation results : on track – D5.2.3 : IP block design and layout : on track – D5.5.4 : test chip characterization : on track



2

2008

A dynamic adaptive Architecture

– Performances improvements: DVFS vs AVFS

1

1,2

1,4

1,6

1,8

2

2,2

2,4

2,6

2,8

3

3,2

3,4

20

40

60

80

100

120

140

160

180

200

0,9 0,95 1 1,05 1,1 1,15 1,2 1,25

Puissance (Consommation)

Puissance (Série4)

Puissance (Période min)

Puissance (PERIODE MIN MONITORS)

Power supply (V)Power supply (V)Pe

riod

(ns)

Perio

d (n

s)

Pow

er (m

W)

Pow

er (m

W)

DVFS

AVFS

DVFS

AVFS

1

1,5

2

2,5

3

3,5

4

4,5

5

20

40

60

80

100

120

140

160

180

200

0,9 0,95 1 1,05 1,1 1,15 1,2 1,25

Puissance (Consommation)

Puissance (Série4)

Puissance (Période min)

Puissance (PERIODE MIN MONITORS)

Same Speed

Same Power

Digital Block

K : Actuators

S : Sensors

K : Actuators

S : Sensors

Parameter Control

Circuit

S

KS

KS

Decision Maker

K

S

Diagnostic

Action

1 Power/Frequency domain



3

2008

Architecture OverviewA fine grain Local Dynamic Adaptive voltage and

frequency scaling architecture

• Diagnostic:– Process-Voltage-Temperature– Timing fault detection or prevention (WP3)

• Actuators:– Based on Vdd-hopping– Local clock generation using FLL

• Power/Variability Control– Local control with minimum hardware (WP4)– Global control : high level algorithms

Main HW objective : a minimum hardware based on standard cellsand simple analog macros for flow insertion and maximum efficiency

PE

CVPU

ANOC

RunTime

0.9v0.7v PE

CVPU

0.9v0.7v



4

2008

LoCoMoTIV architecture

An AVFS GALS approach at fine grain to reach an optimum energetic point according to PVT variations

D-$

Local Compensation of Modern Technology Induced Variability

ANOC

L2-RAM

ITsITs

Debug & Test Unit

NI

DMA

MS M

Memory Mapped

Peripherals

WDT

HWS

TMS TCK TDI TDO BI BO TMS TCK TDI TDO BI BO TMS TCK TDI TDO BI BO TMS TCK TDI TDO BI BO

16KB P-$

OCE

32-KB TCDM

STxP70-V4(Rev. A)

+ ITC#1

16KB P-$

OCE

32-KB TCDM

STxP70-V4(Rev. A)

+ ITC#2

16KB P-$

OCE

32-KB TCDM

STxP70

16KB P-$

OCE

32-KB TCDM

STxP70

Hopping / FLL

S PVT

CVP-U NI CVP-U NI NI NI

Hopping / FLL

S PVT

NI NI

NI

Asynchronous NoC

V/F Local actuators

Timing Fault Detectors

PVT sensors

4 XP70 µP4 XP70 µP4 XP70 µP4 XP70 µP

Dedicated memory blocks

Local ControllerCVP : Clock-

Vraiability-Power



5

2008

LoCoMoTIV flooplan

CDMA

PE0 PE1

PE2 PE3

ANOC

L2RAM

Hopping transition and switches :

Voltage genrationPVT probes

Fully digital FLL : Frequency generation

BACK

CONFIDENTIAL

Task 5.2 IFXA Objective and Outline

Objective: development and verification of monitor & control (M&C) strategies for AMS&RF circuits to deal with aging/reliability issues and aging induced parameter variations in nanometer CMOS.

Close link to T3.3 (M&C concept development)

Outline– Basic aging/reliability assessment identify sensitivities

• Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2)• Dedicated test-structures for transient effects and aging-parameter-variations

– Development of M&C concepts T3.3– Implementation and verification of M&C concepts

• Silicon based proof of concept • Concept development for accelerated aging/stress tests T5.2• Development of characterization methods (fast transient effects) T5.2

6MODERN General MeetingsCatania, Nov. 9 & 10, 2010

CONFIDENTIAL

Task 5.2 IFXA Completed and Remaining Activities

Test-chip status:– TC #1 (32nm CMOS): taped, lab characterization completed– TC #2 (32nm CMOS): taped, lab characterization on-going– TC #3 (28nm CMOS): design on-going, tape-out end 2010

Status basic aging/reliability assessment (-> circuit level results)– Circuit level aging simulation flow proven on TC1 (OpAmps, VCOs)– Structures for transient effects and aging-variations implemented on TC2


Static offset

Recovery

OpAmp: Offset driftVCO: aging of startup VDD

CONFIDENTIAL


Status implementation & verification of M&C concepts– Accelerated aging test-setup proven on TC1 and TC2 (OpAmps, VCOs)– Fast offset characterization method (transient effects) proven on TC2– Measurements to be finalized on TC2

• ADC incl. error correction (static & transient offsets)• Switch degradation monitor circuits• Variations of aging parameters• Novel burn-in concept (to increase robustness and compensate PV)

– Macros to be implemented on TC3• Switch control circuits to be implemented on TC3• DCDC test-structures


PD

EM

OS

ND

EM

OS V

-Sen

se

Re

fbu

f

ES

DE

SD

ESD

PID

ES

D

Fig

ure

5:

Ch

ip M

icro

gra

ph

PD

EM

OS

ND

EM

OS V

-Sen

se

Re

fbu

f

ES

DE

SD

ESD

PID

ES

D

PD

EM

OS

ND

EM

OS V

-Sen

se

Re

fbu

f

ES

DE

SD

ESD

PID

ES

D

Fig

ure

5:

Ch

ip M

icro

gra

ph

BACK

CONFIDENTIAL

Task 3.3 IFXA Key Results Aging Assessment

Majority of key blocks AMS & RF is inherently robust (“self-regulation”)

Sensitive cases– Non-linear / asymmetric operation (comparator)– Full scale driven devices (switches, VCO, …)

Transient effects (recovery) significantly contribute

Variations of aging parameters need to be considered ( T5.2)

Scaling 65nm to 32nm: not absolute values but sensitivities change


Static offset

Recovery

OpAmp: Offset drift VCO: aging of startup VDD

CONFIDENTIAL

Task 3.3 IFXA Key Results M&C Development

Switches– Monitor concepts: ring oscillator, current sensing– Control: “frequency locked loop”, analog control loop

Aging induced offsets– Avoid offset generation: e.g. chopping (comparator)– Correction of static & dynamic effects: e.g. error correction by redundancy – Burn-in: dedicated stress to increase robustness and compensate PV


Inv 1 ... Inv 2 ... Inv n

stress pattern control voltage

switch replicas

enable

ADC search algorithm incl. redundancy

CONFIDENTIAL


Testchip #1 and #2 taped, samples not fully characterized, design of #3 on-going

Basic aging/reliability assessment almost completed– Simulations completed, sim.-concept verified (TC1, OpAmps, VCOs)– Structures for transient effects and aging-variations implemented on TC2

Development of M&C concepts completed

Implementation and verification of M&C concepts ongoing– Accelerated aging test-setup proven on TC1 and TC2– Fast offset characterization method proven on TC2– TC2

• Switch monitor circuits• ADC incl. error correction

– TC3• Switch control circuits to be implemented on TC3• DCDC test-structures• Concept development for accelerated aging/stress tests


CONFIDENTIAL 12MODERN General MeetingsCatania, Nov. 9 & 10, 2010


BACK

MODERN

WP5 THALES foreseen activities10 November 2010

WP4 Web Meeting

Slide 16 of 19

20 November 2009

THL activities in MODERN linked to WP5

Up to now we (THL) have had contributions in WP4 to develop a SystemC simulator of a predictable fault-tolerant multicore chip (based on the ISD network) with embedded middleware and operating libraries.

developed a processor tile designed and implemented fault injection scenarios design the multicore chip with ISD network implemented a SystemC simulator of the chip designed and implemented operating libraries, middleware and tools modified in-house tools to generate parallel code for this architecture designed, developed and implemented a video detection algorithm on top of the

architecture based on the Viola & Jones face detection (Haar filters).

WP4 Web Meeting

Slide 17 of 19

20 November 2009

Architecture (SystemC)

…

NUMASHMEM

Supervisor : TILE 0CTR

DMA LMEM

NIM

CTR: ConTRolerDMA: Direct Memory AccessNIM: Network Interface Module(Makes network protocol translation)

ISD HyperCube Network

iNoC : Internal Network OCP TL2

ACC: ACCeleratorLMEM: Local MEMorySHMEM: SHared MEMoryNUMA: Non Uniform Memory Access

TILE 1CTR ACC

DMA LMEM

NIM

TILE NCTR ACC

DMA LMEM

NIM

WP4 Web Meeting

Slide 18 of 19

20 November 2009

Fault Scenario Definition Memory faults: a fault occurs randomly in shared data

memory (e.g. wrong value written). A read time, the memory tells the reading tile that data contains errors. This reading tile sends a message to the supervisor tile. The supervisor takes actions to solve the problem.

Tile faults: a processing tile sends periodically a message to the supervisor tile (watchdog). When it stops doing so, the supervisor takes actions to solve the problem.

To solve a problem, the supervisor : Stops the processing tiles Find a new memory mapping and tile mapping. Configure the network according to that mapping. Restart the processing tiles

WP5 foreseen activities and deadlines WP5: multicore chip FPGA implementation

M27: D5.2.2: VHDL IPs developed

supervisor Tile, NIM, SHMEM controler, NoC

Software developed Tile bootloader, SHMEM test access

M36: D5.3.3 Several Tiles (12 foreseen) Develop HAL Reuse Operating Libraries from SystemC Video detection application.

Supervisor : TILE 0CTR

DMA LMEM

NIM

BACK

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