oscillators.cvelissaris/fall13/phy3722/notes/lect_6... · this is called a lag circuit since the...

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Oscillators. Theory of Oscillations. The lead circuit, the lag circuit and the lead-lag circuit. The Wien Bridge oscillator. Other useful oscillators. The 555 Timer. Basic Description. The RS flip flop. Monostable operation of the 555 timer. Astable operation of the 555 timer. The VCO (Voltage Controlled Oscillator.) Pulse Width Modulation. Pulse Position Modulation. Ramp Generator.

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Page 1: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

Oscillators.

• Theory of Oscillations.

• The lead circuit, the lag circuit and the lead-lag circuit.

• The Wien Bridge oscillator.

• Other useful oscillators.

• The 555 Timer. Basic Description. The RS flip flop.

• Monostable operation of the 555 timer.

• Astable operation of the 555 timer.

• The VCO (Voltage Controlled Oscillator.)

• Pulse Width Modulation.

• Pulse Position Modulation.

• Ramp Generator.

Page 2: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

outυ

inυ

CR ( )

)(

)(0

)(

222

)(0

222

222

222222222

222

11

11

sincos1

1

1

11

1

)(

1

φωφω

φ

υ

ω

υυ

ω

υφφ

ω

ωυυ

ωω

ω

ω

ωυυ

ω

ωωυ

ω

ωυυυ

++ =

+

=

+

=++

=

++

++=

⇒+

+=

+=

+=

tj

out

tjin

out

j

ininout

inout

inin

C

inout

ee

CR

CR

ej

CR

RC

CRj

CR

RC

CR

RC

CR

jRCRC

RCj

RCj

XR

R

222222 1

1sin,

1cos

CRCR

RC

ωφ

ω

ωφ

+=

+=

This is called a LEAD circuit since the output voltage precedes (leads) the input voltage by

a phase which depends on the frequency. It is also a high pass filter since it allows high

frequencies to pass and blocks dc signals.

Page 3: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

outυ

inυ

CR

)(

)(0

)(

222

)(0

11

φωφω υ

ω

υυ ++ =

+

= tj

out

tjin

out ee

CR

222222 1

1sin,

1cos

CRCR

RC

ωφ

ω

ωφ

+=

+=

||

||

)(0

)(0

in

outA

υ

υ=

1

ω ω

φ

090

Page 4: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

inυC

Routυ

( )

)(

)(0

)(

222

)(0

222222

222222222

222

1

1sincos

1

11

1

1

1

1

1

φωφω

φ

υω

υυ

ω

υφφ

ω

υυ

ω

ω

ωω

υυ

ω

ωυ

ω

υυυ

−−

=+

=

⇒+

=−+

=

+−

++=

⇒+

−=

+=

+=

tj

out

tjin

out

j

inin

out

in

out

in

in

C

C

inout

eeCR

CR

ej

CR

CR

RCj

CRCR

CR

RCj

RCjXR

X

222222 1sin,

1

1cos

CR

RC

CR ω

ωφ

ωφ

+=

+=

This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a

phase which depends on the frequency. It is also a low pass filter since it allows low

frequencies and dc signals to pass and blocks high frequency signals signals.

Page 5: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

inυC

Routυ

)(

)(0

)(

222

)(0

1

φωφω υω

υυ −− =

+= tj

out

tjin

out eeCR

222222 1sin,

1

1cos

CR

RC

CR ω

ωφ

ωφ

+=

+=

||

||

)(0

)(0

in

outA

υ

υ=

1

ωω

φ

090

Page 6: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

inυC

Routυ

C

R

inυ

outυ

Cj

RCjXRZ C

ω

ω+=+=

11

RCj

RXRZ C

ω+==

1//2

1Z

2Z

−+

=+

=

RCRCj

ZZ

Z ininout

ωω

υυυ

1321

2

This is called a LEAD – LAG circuit and it is the feedback circuit of a Wien – bridge oscillator.

We will examine its frequency dependent behaviour.

Page 7: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

( )

)(

)(0

)(

2

)(0

22

222

21

2

19

19

sincos

19

19

1

19

3

19

13

φωφω

φ

υ

ωω

υυ

ωω

υφφ

ωω

υυ

ωω

ωω

ωωω

ω

υυ

ωω

υυυ

++ =

−+

=

−+

=+

−+

=

−+

+

−+

−+

=

−+

=+

=

tj

out

tjin

out

j

inin

out

in

out

in

inout

ee

RCRC

RCRC

ej

RCRC

RCRC

RCRCj

RCRCRC

RC

RCRCj

ZZ

Z

221

9

1

sin,

19

3cos

−+

=

−+

=

RCRC

RCRC

RCRC

ωω

ωωφ

ωω

φ

Page 8: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

2)(0

)(0

19

1

||

||)(

−+

==

RCRC

Ain

out

ωω

υ

υω

RCr

1=ω

3

1

ω

Voltage gain of a LEAD LAG circuit as a function

of frequency. The circuit has a resonant frequency

where the voltage gain is maximized.

Page 9: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

RCr

1=ω ω

221

9

1

sin,

19

3cos

−+

=

−+

=

RCRC

RCRC

RCRC

ωω

ωωφ

ωω

φ

φ

090+

090−

Phase difference between the output and input signals

at a LEAD LAG circuit. At the resonant frequency the

output signal is in phase with the input.

Page 10: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

-

+

C

C

R

R

2R1

R1

RL

A

+VCC

-VCC

RCf r

π2

1=

Wien Bridge oscillator.

Page 11: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

The 555 Integrated Circuit timer is an IC that can run in two modes. Either monostable where

it has only one stable state or astable where it has no stable output state. In the monostable mode

the 555 after it receives an external trigger pulse it changes its state from LOW to HIGH but

since this is not a stable state after some time it makes a transition back to low from high.

Therefore it produces an output pulse of fixed duration W. Another name for the 555 operating

in the monostable mode is monostable or one-shot multivibrator.

The 555 connected as an astable multivibrator has no stable states but it oscillates between two

output states producing a periodic rectangular signal (a series of rectangular pulses). Another

name for the astable operation of the 555 is free-running multivibrator.

An example of a bistable multivibrator is the RS Flip Flop. It has two stable output states and it

latches to an output state depending on its input. It is a basic electronic memory cell and we will

describe its operation.

Page 12: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

The RS Flip Flop has one power supply +VCC two inputs S (SET), R (RESET) and two

complementary outputs Q and Q/ . The two outputs cannot be both HIGH or both LOW at the

same time. When Q is high Q/ is low and vice versa.By applying a high pulse at the S input we

can drive the left transistor into saturation. This will make Q/ LOW and therefore it will drive the

right transistor into cutoff making therefore Q high. The state is stable even if we remove the

S high signal. If we impose a high signal at the R input the opposite will happen. We will drive

the right transistor into saturation and this will drive the left transistor into cutoff. The state will

persist even after the removal of the HIGH R pulse and we will have a HIGH Q/ and a LOW Q.

It is prohibited though to have both inputs HIGH

since this will produce undetermined results. If

we keep both inputs LOW the flip flop will

maintain its last state. It exhibits “memory” and

it is the basic cell of electronic memory.

Page 13: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

This is a rough sketch of the 555 timer Pin 5 is used to set the output frequency when the 555

timer is operating in the astable mode. Pin 5 is set inactive by connecting it to ground via a

capacitor. Pin 4 resets the output voltage to zero. It can be set inactive by connecting it to VCC

.

Pin 2 is the trigger voltage when the timer works in the monostable mode. Pin 2 is connected to

the lower comparator and when its signal becomes less than the LTP = VCC

/3 makes the lower

comparator to produce an output signal. Pin 6 is the threshold. When the threshold is larger than

The UTP = 2VCC

/3

the upper comparator

produces a HIGH

output. Since the three

resistances of the

voltage divider are

equal we have:

UTP = 2VCC

/3

LTP = VCC

/3

Page 14: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

This is the connection of the 555 in the monostable operation.When first powered the external

capacitor is charged and pin 6 is at 2VCC

/3. Since Pin 2 is HIGH The two comparators will

produce S = 1 and R = 0 which will set the flip flop at Q=1 and OUT = 0. High Q will saturate

the transistor and the external capacitor will discharge itself through the transistor setting pin 6 to

ground and S = R = 0 which has no effect at the output of the flip flop. A short trigger signal at

pin 2 from low to high will set

S = 0, R = 1 that will produce

OUT = 1 and Q = 0 which will

cut the transistor off. The

capacitor will once more start

charging itself and when the

voltage at pin 6 becomes

2VCC

/3we will have S=1, R = 0

and the flip flop output will

once more be Q= 1, OUT = 0.

The duration W of the HIGH

output state is equal to the

amount of time it will take the

external capacitor to charge

itself up to 2VCC

/3.

It can be proven that W = 1.1RC

External R and C control the

duration of the astable pulse.

Page 15: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

In the monostable operation when the TRIGGER signal at PIN high the output is low and the

capacitor is kept discharged via the transistor which is acting as a virtual short because it is kept

saturated. If a short pulse (high to low) is fed to the pin 2 the out is going to become high, the

transistor is going to be cut off and the charging of the capacitor will start as shown in the figure.

For as long as the capacitor is being charged the output is going to be high and the transistor cut

off. When the transistor voltage reached 2VCC

/3 out will become low and the transistor saturated.

The 555 will fall into its stable state.

Page 16: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

RCRCWeVV

eVV RC

W

CCCCRC

t

CCC 1.13ln)1(3

2)1( ==⇒−=⇒−=

−−

Proof of the W=1.1RC formula for the astable operation of the 555 timer. The time dependence

of the charging of the external capacitor is:

Pin 5 (CONTROL) is connected to ground via a capacitor to prevent stray em noise to interfere

with the circuit operation. Pin 5 this way becomes inactive. Pin 4(RESET) is connected to VCC

and this way is inactive during this operation of the 555 timer.

For the astable operation of the 555 timer two external resistors and one capacitor are required.

Pin 2 (the trigger) and pin 6 (the threshold) are tied together, to the ground via an external

capacitor C and to the pin 7 (discharge) via an external resistor R2. Pin 7 is also connected to

pin 8 (the power supply VCC

) via another external resistor R1.the capacitor is continuously

charged and discharged setting the flip flop at S=1 R=0 and S=0, R=1 consecutively.

When the capacitor is charged it is the time constant is (R1+R

2)C and when discharged the time

constant is R2C. The lowest capacitor voltage is the LTP = V

CC/3 and the highest is UTP =

2VCC

/3.

Page 17: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

Initially the capacitor is charged up to 2VCC

/3 wit a time constant (R1+R

2)C and S=1,R=0 that

set OUT = 0 and the transistor into deep saturation. The saturated transistor discharges the

capacitor with a time constant R2C down to LTP = V

CC/3 that set S=0, R=1, OUT=1 and the

transistor into cutoff. The capacitor discharge stops and the charging starts all over.

OUT = 1 during the capacitor charging time and OUT = 0 during its discharging time.

Page 18: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

inRC

t

inCC VeVVtV +−=−

))0(()(

In an RC circuit with input constant dc voltage Vin

, the voltage at the capacitor is given by

the equation.

When the capacitor charges itself VC(0)= V

CC/3, Vin = V

CCand R = R

1+R

2. The charging time

W is:

CRRCRRW

VeVVV

WV CC

CRR

W

CCCCCC

C

)(693.02ln)(

)3

(3

2)(

22

)(

11

21

+=+=

⇒+−==+

When the capacitor discharges itself VC(0)= 2V

CC/3, Vin = 0 and R=R

2. The discharging time is:

CRCRteVV

tVCR

W

CCCC

C 2211 693.02ln3

2

3)( 2 ==⇒==

The period of the waveform is W+t1

= T

CRRCRRT )2(693.02ln)2( 22 11+=+=

Page 19: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

When the 555 chip is operating as Voltage Controlled Oscillator or VCO it is connected as an

astable multivibrator with the only difference that pin 5 (CONTROL) is not idle by being

connected to ground via a capacitor but it is connected to a potentiometer which is connected to

the power supply VCC

. Therefore the Vcon

voltage of pin 5 can vary from 0 to VCC

.

Recall that pin 5 is defining the UTP of the

555 first comparator. The external voltage

Vcon

overrides the default UTP = 2VCC

/3

and LTP = VCC

/3 and sets them to UTP =

Vcon

and LTP = Vcon

/2. The capacitor

charges and discharges itself from LTP to

UTP and vice versa, operating once more in

the astable configuration. By using:

inRC

t

inCC VeVVtV +−=−

))0(()( We can find

2ln

5.0ln)(

2

21

CRWT

VV

VVCRRW

conCC

conCC

+=

−+=

Page 20: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

In the START and RESET

circuit the 555 timer is connected

in the monostable configuration.

When the switch at PIN 2 is

pressed a TRIGGER signal

produces an output pulse of

fixed duration. This pulse may

drive an alarm or FET or buzzer.

Here in the figure it drives an

LED.

The switch at PIN 4 acts as a

RESET button to reset the timer

output at LOW in case that the

output signal lasts too long.

Page 21: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

In the ALARM circuit the 555

timer is connected in the astable

configuration. Normally the

switch at PIN 4 is closed and the

timer has the RESET pin active.

When the switch is depressed

(open) a rectangular periodic

wave train is generated which in

the figure drives a siren.

The alarm can be reset by pressing

the PIN 4 switch one more.

When the switch at PIN 2 is

Page 22: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

In Pulse Width Modulation the timer is connected in the monostable configuration. A periodic

TRIGGER pulse is fed at PIN 2 and its period defines the period of the output rectangular pulses.

At PIN 5 an ac input signal is superimposed on the dc UTP = 2VCC

/3 + υ(t). The output rectangular

pulses have a constant period but their width depends on the instantaneous UTP when the triggerpulse at PIN 2 arrived.

Page 23: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

In the Pulse Position

Modulation the 555 timer is

connected at the astable

configuration. At PIN 5 an

ac input signal is

superimposed on the dc

UTP = 2VCC

/3 + υ(t). The

output sequential

rectangular pulses have

constant “space” between

them (the discharge time of

the capacitor R2Cln2). The

width of each pulse depends

on the instantaneous UTP.

Notice the absence of clock.

Page 24: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

inRC

t

inCC VeVVtV +−=−

))0(()(

In an RC circuit with input constant dc voltage Vin

, the voltage at the capacitor is given by

the equation.

When the capacitor charges itself VC(0)= LTP=UTP/2, Vin = V

CCand R = R

1+R

2. The final

voltage of the capacitor will be VC(W)=UTP and the charging time will be:

When the capacitor discharges itself VC(0)=UTP, Vin = 0, R=R

2.and V

C(t

1)=LTP=UTP/2. The

discharging time is:

CRCRtUTPeUTP

tVCR

t

C 2211 693.02ln2

)( 2

1

==⇒==−

The period of the waveform is W+t1

= T CRRCRRT )2(693.02ln)2( 22 11+=+=

⋅−

−+−=

⇒+−==+

UTPV

UTPVCRRW

VeVUTP

UTPWV

CC

CC

CC

CRR

W

CCC

5.0ln)(

)2

()(

21

)( 21

Page 25: Oscillators.cvelissaris/Fall13/PHY3722/notes/Lect_6... · This is called a LAG circuit since the output voltage succeeds (lags) the input voltage by a phase which depends on the frequency

When the 555 timer is configured as a ramp

generator it is connected in the monostable

configuration but the charging of the capacitor

now is via the emitter current of a transistor.

The transistor is biased in such a way that it

delivers constant current IE=(V

CC-V

E)/R

E.

The VE

is determined from VE-V

B=0.7V and

VB

is determined from the R1, R

2voltage

divider. Current IE

is charging the capacitor

and the capacitor is being discharged

instantaneously (via the saturated transistor

inside the 555 IC). The output now is not

from pin 3 any more but from pins 6 and 7

(shorted together). When a trigger arrives the

capacitor starts charging itself and the outpou

voltage is VC(t)=(I

C/C)t. The duration of that

ramp like voltage pulse is given by the

equation:

C

CC

CCC

I

CVW

WC

IVUTP

3

2

3

2

=

⇒==