· 0093-9994 (c) 2015 ieee. personal use is permitted, but republication/redistribution requires...

0093-9994 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2016.2553650, IEEETransactions on Industry Applications

Chuan Shi, Student Member, IEEE, Alireza Khaligh1, Senior Member, IEEE, and Haoyu Wang,

Member, IEEE

Maryland Power Electronics Laboratory

Electrical and Computer Engineering Department, The Institute for Systems Research,

University of Maryland, College Park, MD 20742 1Corresponding Author, EML: [email protected]; URL: http://khaligh.umd.edu/

Abstract—A power factor pre-regulator (PFP) usually

serves as the first stage of an active two-stage AC/DC

converters in a variety of applications including inductive

heating systems, wireless charging systems, and onboard

chargers for plug-in electric vehicles (PEVs).

Conventionally, boost-type PFPs are utilized to regulate

the DC-link voltage at a fixed voltage; however, a

variable DC-link voltage can enhance the overall

efficiency of the converters. In this paper, an interleaved

single-ended primary inductor converter (SEPIC) with

coupled inductors is proposed as the PFP stage for two-

stage AC/DC converters. The converter is designed to

operate in discontinuous conduction mode (DCM) in

order to achieve soft switching for switches and diodes.

The directly coupled inductors are utilized to reduce the

number of magnetic components and decrease the input

current ripple. A 500W interleaved SEPIC PFP

prototype is designed to verify the benefits of this

converter. The experimental results show that the

converter can maintain high efficiency over a wide range

of DC-link voltage.

Keywords—Power factor pre-regulator (PFP), single-

ended primary inductor converter (SEPIC),

discontinuous conduction mode (DCM), coupled

inductors, interleaved converter.

I. INTRODUCTION

To improve the power quality of the gird, high power

factor (PF) and low total harmonics distortion (THD) are

required for the grid-connected AC/DC converters.

Nowadays, two-stage active AC/DC converters have been

widely used in a variety of applications such as onboard

chargers for plug-in electric vehicles (PEVs), inductive

heating systems, and wireless charging systems [1]-[3]. The

two-stage AC/DC converters are typically composed of a

PFP stage followed by an isolated DC/DC stage, as shown in

Fig. 1 [1]. A DC/DC resonant converter is usually selected as

the second stage due to its attractive features such as soft

switching, galvanic isolation, and high efficiency near

resonant frequency.

AC/DC

PFP

Converter

VgridIsolated

DC/DC

Converter

DC

Load

DC Link Bus

Capcitors

DSP

Controllers

Fig. 1. Typical structure of two-stage active AC/DC converters.

The objective of PFP stage is to improve power quality

and reduce harmonic contamination. The topology for the

PFP stage is a diode bridge followed by a boost-type

converter [1]. Although the boost-type PFP converters can

provide efficiencies over 98% [4]-[5], the overall efficiency

of the two-stage converter is reduced significantly if the

second-stage resonant converter cannot operate near the

resonant frequency.

In the application of onboard battery chargers for PEVs, as

shown in Fig. 2, a LLC resonant converter stage follows a

boost-type PFP stage [6]-[8]. The output voltage of the LLC

converter is regulated by pulse frequency modulation. The

resonant frequency is the optimal operation frequency

associated with the highest efficiency. The operating

frequency of the LLC converter moves away from the

resonant frequency when the battery voltage is lower than the

rated voltage at a lower state of charge (SOC). Consequently,

the efficiency of the LLC converter drops significantly. To

achieve the highest possible efficiency, i.e. ensure operation

at resonant frequency, the input voltage of the LLC converter

can be regulated to follow the output battery voltage [9]-[11].

Due to the wide variation of the battery pack, the DC-link

voltage should be regulated over a wide range and sometimes

Interleaved SEPIC Power Factor Pre-Regulator Using

Coupled Inductors in Discontinuous Conduction Mode

with Wide Output Voltage

mailto:[email protected]

http://khaligh.umd.edu/



become less than the PFP’s input voltage [12], [13].

However, the output voltage of boost-type topologies cannot

be lower than the input voltage.

Batt.

Pack

VDC

PFP LLC converter

Vgrid

DC Link

Bus

Transformer

L1 D1

S1

C1

Lr

S2

Lm

S4

S3 S5

Cr

C2

CDC

DB1 DB2

Fig. 2. Two-stage battery charger system.

Additionally, the boost-type PFPs are not the most suitable

topologies for inductive heating applications, where the high

frequency AC magnetic field should be generated to deliver

power over a distance by a subsequent resonant converter

stage [3]. A wide output voltage variation is required in this

application due to a need for variable power levels for

heating. Similar to onboard charger application, a fixed DC-

link voltage would result in lower overall efficiency

particularly in light loads by using a resonant DC/DC

converter stage controlled by pulse frequency modulation.

For such applications, a PFP stage capable of providing a

wide regulated DC-link voltage, such as a single-ended

primary-inductor converter (SEPIC) PFP, can improve the

overall efficiency of the systems to a great extent.

The SEPIC topology, shown in Fig. 3, has been

investigated as the PFP in AC/DC converters in various

applications including standalone photovoltaic systems and

LED lighting systems [14]-[23]. In a SEPIC PFP, the output

voltage can be either higher or lower than the input voltage.

The voltage and current stresses of diodes and switches, in a

traditional SEPIC converter, are much higher than a boost-

type topology at the same power level. Thus, the traditional

SEPIC topology is not widely used for high power

applications [24]. The bridgeless SEPIC PFP converters have

been investigated to reduce the conduction loss of the diode

bridge in [15]-[18]. However, the voltage and current stresses

of switches are not reduced, and the power level is usually

limited to less than 150W, due to voltage and current

limitations of switches in the orders of 300V and 10A,

respectively. In addition, in the continuous conduction mode

(CCM), the SEPIC converters have large hard-switching

losses, especially in high frequency operation. Therefore, the

efficiencies are low for a traditional SEPIC converter

operated in CCM. In [3], the power level is increased by

interleaving two SEPIC converters. However, this topology

is constructed by directly paralleling two traditional SEPIC

converters, and consequently the input current ripple is large

in discontinuous conduction mode (DCM) operation.

VgridVg

S1

C1

CDC RL

L1 D1

L2

Fig. 3. Traditional SEPIC PFP converter.

In this paper, a two-phase interleaved SEPIC AC/DC

converter with coupled inductors is proposed to serve as the

PFP stage with a wide range of output DC-link voltage. Its

topology is shown in Fig. 4. The input power is shared

evenly between two phases to reduce the current stresses of

the switches and diodes; and consequently, the power level

can be increased. Since the CCM operation causes large

switching losses, the DCM operation is selected to enable

soft switching. The ZVS can be realized for the MOSFET’s

to reduce the switching losses, while the ZCS can be realized

for diodes, D1 and D2, to eliminate reverse recovery losses

[14]. In order to reduce the number of magnetic components,

the corresponding inductors in two phases are directly

coupled. The input current ripple could be significantly

reduced through proper design of the coupled inductors.

Vgrid

S2 S1

C1

C2

CDC RL

L1

D1

D2

L2

L3 L4

iL1

iL2iin

iL3 iL4 iCo

iout

Vo

iD1

iD2

iS2 iS1

VC1

VC2

Fig. 4. Proposed interleaved SEPIC PFP converter.

This paper is organized as follows. The principle of

operation is presented in Section II. The theoretical analyses

are elaborated in Section III. Furthermore, experimental

results of a 500W prototype are demonstrated in Section IV

for validation of the analyses. Finally, Section V concludes

the manuscript.

II. OPERATION PRINCIPLE

In Fig. 4, the rectified voltage after the diode bridge can be

modeled as an equivalent variable DC source Vg. Assuming

that the DC-link capacitor CDC and two middle capacitors C1,

C2 are large enough and their voltage ripples are negligible

compared with their steady-state voltages. The output

capacitor can be modeled with an equivalent DC source Vo.

Since the middle capacitors C1 and C2 have the same steady-

state voltages as the input rectified voltage Vg, the two

middle capacitors can be modeled as the equivalent variable

DC source Vg [24], as shown in Fig. 5.

The analyses are separated into the higher output voltage

case and the lower output voltage case as the output voltage

of a SEPIC converter can be either higher or lower than the

input peak voltage. These two cases are analyzed in this

section using the derived equivalent model.

Vg S2 S1 RL

D1

D2

Vo

Vg

Vg

L1

L2

L3 L4

Fig. 5. Equivalent circuit of the proposed interleaved SEPIC converter.



A. Lower Output Voltage Case

The output voltage of PFP stage can be lower than the

input peak voltage. In DCM operation, the duty cycle is less

than 0.5, and it is also less than the duty cycle derived in

CCM operation with the same output voltage [24].

The typical waveforms of the converter in DCM are

shown in Fig. 6, in which there are six modes in one

switching cycle. There are three modes in each of the

positive and the negative half cycle operations. Here, only

three modes in positive half cycle are analyzed due to the

symmetry of operation. The equivalent circuit for each mode

is shown in Fig. 7.

S1

S2

iL1iL2

iL3 iL4

iD1

Current

Current

Current

Gate Drive 2

Gate Drive 1

0

0

Time

iD2

t0

Current

t1 t2 t3 t4 t5 t6

0

0

Fig. 6. Typical waveforms of the interleaved SEPIC converter in DCM.

In this two-phase interleaved topology, the corresponding

inductors in two phases are coupled using the same cores

with the same coupling coefficients. The inductor L1 is

coupled with L2, while the inductor L3 is coupled with

inductor L4. These four inductors have the same self-

inductances and mutual inductances. In each operation mode,

the voltages across inductors L1 and L4 are the same in each

operation mode. Thus, the inductor currents iL1 and iL4 have

similar waveforms as shown in Fig. 6. Similar waveforms are

valid for inductors L2 and L3.

Vg S2 S1 RL

D1

D2

Vo

Vg

L1

L2

L3 L4

iL1

iL4iS1

Vg iD2

iL3

iL2

(a)

Vg S2 S1 RL

D1

D2

Vo

Vg

Vg

L1

L2

L3 L4

iL2

iL3

(b)

Vg S2 S1 RL

D1

D2

Vo

Vg

L1

L2

L3 L4

iL4

iL1

iL3

iD1

iL2

iL3

Vg

(c)

Fig. 7. Equivalent circuits in DCM, (a) Mode I, (b) Mode II, (c) Mode III.

1) Mode I (t0-t1):

In this mode, as shown in Fig. 7(a), the switch S1 is on,

while the switch S2 is off. The diode D1 is off, and diode D2

is on. The voltages across both inductors L1 and L4 are Vg.

Therefore, the inductor currents iL1 and iL4 increase at the

same rates. The current through S1, iS1, is the sum of the

inductor currents iL1 and iL4. Meanwhile, voltages across both

inductors L2 and L3 are −Vo. Thus, the inductor currents iL2

and iL3 decrease at the same rates, and the current through

diode D2, iD2, is the sum of these two inductor currents.

As the inductors L1 and L2 are directly coupled, the core

flux is affected by both inductor currents iL1 and iL2. The

mutual inductance, M, is defined as,

M=√L12∙L21 (1)

where, L12 is the mutual inductance induced by the inductor

current iL1 in inductor L2, and L21 is the mutual inductance

induced by the inductor current iL2 in inductor L1. Since the

mutual inductance of inductors L1 and L2 are the same, the

mutual inductance M has the same value as L12 and L21.

Additionally, the coupling coefficient, k, is defined as,

k=

M

√L1∙L2

(2)

where, L1 and L2 are self-inductances of the first coil and the

second coil.

The voltages and currents of the mutually coupled

inductors can be expressed as,

Vg=L1

diL1

dt+M

diL2

dt (3)

−Vo=M

diL1

dt+L2

diL2

dt (4)

Eq. (3) and Eq. (4) can be rearranged as,

diL1

dt=

Vg+kVo

(1-k2)L1

(5)

diL2

dt=-

Vo+kVg

(1-k2)L2

(6)

Seen from the Fig. 6, the inductor current iL2 decreases all

the time and changes the flowing direction in this mode. The

current through diode D2, iD2, keeps on decreasing. The



variations of inductor currents, ∆iL1 and ∆iL2, can be

expressed as,

∆iL1=Vg+kVo

(1-k2)L1

D'T (7)

∆iL2=

Vo+kVg

(1-k2)L2

D'T (8)

where, T is the switching period, and D'T is the time interval

between t0 and t1.

2) Mode II (t1-t2):

At t1, the current through diode D2, iD2, which is the sum

of inductor currents iL2 and iL3, drops to zero. Then, the diode

turns off with ZCS. Meantime, the inductor currents iL3 and

iL2 flow in a loop composed of the inductor L3, the capacitor

C2, the inductor L2, and the equivalent voltage source Vg, as

shown in Fig. 7(b).

The variations of inductor currents iL3 and iL2 are the same

due to the same voltages across inductors L3 and L2. In

addition, the average current of iL3 is higher than the average

current of iL2 [17]. Thus, at t1, when the inductor currents iL3

and iL2 drop to minimum, the inductor current iL3 is higher

than iL2 with iL3 as positive value and iL2 as negative value, as

shown in Fig. 6. The current flows from inductor L3 to

inductor L2 in the aforementioned loop containing inductors

L3 and L2. Assuming that the resistances of inductors and

capacitors in this loop are negligible, the loop current

remains constant from t1 to t2, as expressed in Eq. (9).

iL3=-iL2=const (9)

The inductor current iL1 changes with a higher rate in

comparison to Mode I as expressed in Eq. (10). The current

of coupled inductor L2 is constant, and only sets the flux bias.

diL1

dt=

Vg

L1

(10)

Consequently, the variation of inductor current, ∆iL1, can

be expressed as,

∆iL1=Vg

L1

(D-D')T (11)

where, D is the duty cycle. Similar expressions are valid for

the inductor L4.

3) Mode III (t2-t3):

As shown in Fig. 7(c), both switches are off in this mode.

The diode D2 is off, while the diode D1 turns on. The

constant current flows in the aforementioned loop consisting

of inductors L2 and L3. The inductor currents iL1 and iL4

decrease from maximum values, and the sum of them flows

through the diode D1. The voltages across both inductors L1

and L4 are −Vo. The inductor current iL1 decreases at a rate

expressed as,

diL1

dt=-

Vo

L1

(12)

Consequently, the variation of inductor current, ∆iL1, can

be shown as,

∆iL1=-Vo

L1

(0.5-D)T (13)

Similar expressions are applicable for the inductor L4.

B. Higher Output Voltage Case

The waveforms of higher output voltage case are similar to

those of lower output voltage case. In DCM, the operation

principles of higher output voltage case are similar to those

of lower output voltage case. In a switching cycle, there are

six modes, among which only three modes are analyzed due

to the symmetry of operation.

1) Mode I:

The inductor currents iL1 and iL2 increase simultaneously at

small rates. Similar to the lower output voltage case, the slew

rate of inductor current iL1 and iL2 are expressed as,

diL1

dt=

Vg

(1+k)L1

(14)

diL2

dt=

Vg

(1+k)L2

(15)

Thus, the inductor current variations, ∆iL1 and ∆iL2, can be

expressed as,

∆iL1=Vg

(1+k)L1

(D-0.5)T (16)

∆iL2=

Vg

(1+k)L2

(D-0.5)T (17)

Since the L3 and L4 have the same inductance values as L1

and L2, similar equations can be derived for the inductor

currents iL3 and iL4.

2) Mode II:

Similar to the lower output voltage case, the slew rate of

inductor current iL1 can iL2 are expressed as,

diL1

dt=

Vg+kVo

(1-k2)L1

(18)

diL2

dt=-

Vo+kVg

(1-k2)L2

(19)

The inductor current iL3 decreases and changes the

direction in this mode. The current through diode, D2, keeps

on decreasing. 𝐷′𝑇 is the time interval between the diode D2

turn-on and turn-off. The variations of inductor currents, ∆iL1

and ∆iL2, can be expressed as,

∆iL1=Vg+kVo

(1-k2)L1

D'T (20)

∆iL2=

Vo+kVg

(1-k2)L2

D'T (21)



3) Mode III (t2-t3):

At t2, the current through diode, D2, drops to zero. Then,

the diode turns off with ZCS. Meanwhile, the currents of

inductors L2 and L3 circulate in a loop composed of the

inductor L3, the capacitor C2, the inductor L2, and the

equivalent voltage source Vg. The constant current flows

from inductor L2 to inductor L3. Thus, Eq. (22) can be

obtained as,

iL3=-iL2=const (22)

The inductor current iL1 changes with a higher rate in

comparison to Mode I as expressed in Eq. (23). The current

of coupled inductor L2 is constant, and only sets the flux bias.

diL1

dt=

Vg

L1

(23)

Therefore, the inductor current variations, ∆iL1, can be

expressed as,

∆iL1=Vg

L1

(D-D')T (24)

Similar expressions are valid for inductor L4.

III. ANALYSIS OF THE PROPOSED PFP TOPOLOGY

Based on the operation principles for higher output voltage

and lower output voltage cases, the detailed analysis can be

conducted to set the critical parameters of power components

and to assess the circuit performance. Relevant expressions

are derived in this section. The analyses are based on the

assumption of unity power factor and a constant output

voltage due to a large output filter capacitance.

A. Reduced Input Current Ripple by Coupled Inductors

In this section, the input current ripple is calculated in

DCM operation. Although the two SEPIC converters work in

DCM operation individually, the input current maintains

CCM features with a small input current ripple.

As shown in Fig. 6, from t0 to t1, the current of L1

increases, and the current of L2 decreases. In this interval, the

input current variation, ∆i1 , is the sum of the current

variations of inductors L1 and L2. It can be expressed as,

∆i1= (

Vg+kVo

(1-k2)L1

-Vo+kVg

(1-k2)L2

) D'T (25)

From t1 to t2, the current of L2 becomes constant, and the

current of L1 increases at a different rate. The input current

variation, ∆i2, is expressed as,

∆i2=

Vg

L1

(D-D')T (26)

The input current ripple is the sum of the two variations,

∆i1 and ∆i2. Thus,

∆i=∆i1+∆i2=a∙D'T+b∙(D-D

')T

(27)

where, a and b are the weighted coefficients.

a=Vg-Vo

(1+k)L, b=

Vg

L

(28)

where, L = L1 = L2.

The coefficient a is much smaller than coefficient b, and

consequently the input current ripple is mostly determined by

second term based on Eq. (27). Thus, the input current

becomes larger as the converter works in deeper DCM

operation. In order to reduce the input current ripple, the

converter should operate under DCM in close proximity to

boundary conduction mode (BCM). When D’ becomes equal

to D, the converter works in BCM with minimum input

current ripple.

Compared with the input current ripples of traditional

SEPIC and interleaved SEPIC with non-coupled inductors,

the input current ripple is significantly reduced. The

expressions for input current ripples are listed in Table I.

TABLE I

INPUT CURRENT RIPPLES OF THREE TOPOLOGIES

Topology Input current ripple

Traditional SEPIC TVg

LD'

Interleaved SEPIC (non-coupled) Vg-Vo

LD'T+

Vg

L(D-D

')T

Interleaved SEPIC (coupled) Vg-Vo

(1+k)LD'T+

Vg

L(D-D

')T

B. Worst Case for DCM Operation and Minimum Coupling

Coefficient

As shown in Fig. 6, most of the inductor current variations

happen when the currents in the mutually coupled inductors

change rapidly in opposite directions. Thus, the inductor

current variation can be simplified as,

∆iL≈Vg+kVo

(1-k2)L

2

DT (29)

Eq. (29) can be rearranged as,

∆iL≈[(1-k)D+k]∙VoT

(1-k2)L

2

(30)

Assume the output voltage, Vo, is constant. With fixed k

and L2 parameters, Eq. (30) shows that the inductor current

variation monotonically increases with the duty cycle. At

peak input voltage, the duty cycle would reach its minimum

value, and the current ripple would be minimum. Meantime,

the instantaneous value of current Ig would be maximum at

peak input voltage, as shown in Eq. (31).

𝐼g=𝐼psin(𝜃) (31)

where, 𝜃 is equal to π/2+kπ radian, and k is an integer.

In other words, the peak input voltage corresponds to the

largest instantaneous current and the smallest current ripple.

Thus, the peak input voltage is the worst case to maintain the

DCM operation in a grid cycle. Designing the circuit to

operate under DCM in this worst case can ensure DCM

operation for the entire period.



The coupling coefficient, k, is critical for ensuring DCM

operation. According to Eq. (29), given a smaller coupling

coefficient, the inductor current variation would become

smaller, and it would be harder for the converter to operate in

DCM. Hence, there exists the minimum coupling coefficient,

kmin, corresponding to operation in BCM, which shares the

same soft-switching features as the DCM operation. Fig. 8

shows the typical waveforms of BCM operation in higher

output voltage case.

S1

S2

iL1 iL2

iL3iL4

iD1

Current

Current

Current

Gate Drive 2

Gate Drive 1

0

0

Time

iD2

t0

Current

t1 t2 t3 t4

0

0

Fig. 8. Typical waveforms of the converter with kmin in higher output

voltage case.

In Fig. 8, there are four modes in one switching cycle. At

t2, the inductor currents iL2 and iL3 reach minimum values,

and the sum of these two currents is the current through

diode D2, which drops to zero. At the same time, the switch

S2 turned on, and the diode D2 turned off with ZCS. Thus, it

is proved that the converter operates in BCM.

The kmin can be obtained by simulation. In Table II, the kmin,

is obtained for different inductances of inductor L2 in both

higher output voltage case and lower output voltage case.

TABLE II L2 AND CORRESPONDING MINIMUM COUPLING COEFFICIENT

Inductance L2 kmin (lower Vout case) kmin (higher Vout case)

200µH 0.6693 0.1397

300µH 0.7837 0.4475

400µH 0.8391 0.5909

500µH 0.8719 0.6749

600µH 0.8936 0.7301

According to Table II, kmin increases with inductance L2.

Based on Eq. (29), with the inductance of L2 increasing, the

coupling coefficient has to increase to keep the inductor

current variation unchanged so that the inductor current iL2

can enter DCM in the worst case. The same principle is valid

for other inductors.

When designing the components, the coupling coefficient

k has to be set higher than the minimum value for specially

chosen inductances to ensure DCM. However, k cannot be

too much higher than the calculated minimum value.

Otherwise, the converter would work in deep DCM resulting

in large input current ripple according to Eq. (27) and Eq.

(28).

C. Theoretical Estimation of Circuit Performance

For simplicity of analysis, it is assumed that the coupled

PFP operates under DCM in close proximity to BCM. The

analysis is conducted in BCM for the proposed converter. In

BCM operation, the diodes turn off with ZCS when the

currents through them decrease to zero. Hence, the reverse

recovery losses are eliminated due to ZCS turn-off. As for

the two MOSFETs, the ZVS turn-on is enabled since the

currents through the switches decrease to zero before they

turn on. Consequently, the turn-on switching losses are

ignored.

The current ripples of the coupled inductors are assumed

to be triangular waveforms. The ripple is assumed to be half

of the peak value for CCM operation, which is a common

assumption in designing inductors in SEPIC circuits [21].

Table III shows the comparison of three different topologies

to highlight the benefits of the proposed topology.

As it can be seen from Table III, the proposed topology

has much lower current ripple and output voltage ripple

compared with the traditional SEPIC PFP. The interleaved

topology has reduced input current ripple and output voltage

ripple. The use of coupled inductors allows the converter to

have the same count of magnetic cores as the traditional

SEPIC converter. The DCM operation reduces the switching

losses to a large extent while the input current ripple and

output voltage ripple are kept close to the CCM operation.

Hence, the efficiency is improved significantly.

TABLE III COMPARISON OF THREE TOPOLOGIES

Topology

Interleaved

SEPIC

BCM-PFP

Interleaved

SEPIC

CCM-PFP

Traditional

SEPIC

CCM-PFP

Input ripple

Current (high

frequency)

Vg-Vo

(1+k)LDT

(2D-1)Vg

(1+k)L

DVg

L

Inductor RMS

current

√30

6

Pin

VPK

√21

6

Pin

VPK

√21

3

Pin

VPK

Output voltage

ripple

Pin

4VoCofs

(D-0.5)P

in

VoCofs

DPin

VoCofs

Output Cap

peak Current

ripple (Low

frequency)

4VPKPin

Vo(VPK+Vo)

4VPKPin

Vo(VPK+Vo)

4VPKPin

Vo(VPK+Vo)

To validate the improved efficiency of the proposed PFP,

theoretical loss analyses are conduct for the proposed PFP

and the interleaved SEPIC CCM-PFP. The loss breakdowns

are calculated for both topologies at full load condition at

Vin=110Vac, Vout=190V (for higher Vout case) and Vout=90V

(for lower Vout vase). The loss breakdowns include the

switching losses of MOSFETs, the diode reverse recovery

losses, the switch conduction losses, the diode conduction



losses, the core losses of inductors, and the ESR (equivalent

series resistance) losses of SEPIC capacitors. The results of

loss breakdown are shown in Fig. 9.

11.8W(44.4%)

5.5W(20.8%)

1.3W(4.9%)0.9W(3.6%)1.5W(5.7%)

Switching LossDiode ReverseSwitch Cond.Diode Cond.Inductor LossCapacitor Loss

0.9W(8.8%)

3.0W(27.9%)

5.5W(51.5%)

Proposed PFP@Vout=190V

11.3W(39.7%)

1.8W(6.5%)2.8W(9.9%)

3.4W(11.8%)

5.5W(11.3%)

CCM-PFP@Vout=90V

2.8W(16.5%)

5.5W(32.3%)

Proposed PFP@Vout=90V

Switching LossDiode ReverseSwitch Cond.Diode Cond.Inductor LossCapacitor Loss

(a) (b)

(c) (d)

5.5W(20.8%) 1.3W(12.2%)

6.9W(40.4%)3.7W(12.9%)

1.8W(10.8%)

CCM-PFP@Vout=190V

Fig. 9. Loss breakdown at full load at Vin=110 Vac, (a) CCM-PFP at

Vout=190V, (b) Proposed PFP at Vout=190V, (c) CCM-PFP at Vout=90V, (d)

Proposed PFP at Vout=90V.

At the full load, the efficiencies of the interleaved SEPIC

CCM-PFP are 94.6% and 94.3% for Vout=190V and

Vout=90V, respectively. In comparison, the efficiencies of the

proposed topology are 97.8% and 96.6% for Vout=190V and

Vout=90V, respectively. The proposed PFP has a higher

efficiency than the interleaved SEPIC CCM-PFP at different

output voltages due to the soft switching feature.

Furthermore, the calculated efficiency curves of the proposed

PFP are shown in Fig. 24.

IV. DESIGN CONSIDERATIONS AND EXPERIMENTAL RESULTS

In this section, a 500W interleaved SEPIC converter with

coupled inductors is designed to validate the theoretical

analysis. The experiments are conducted to validate the

advantages of proposed topology.

A. Control Scheme

The proposed control scheme requires three sensors (input

voltage, input current, and output voltage). The topology

and the control scheme are shown in Fig. 10. Only one

current sensor is used to sample the total current of the two-

phase interleaved PFP converter. The sawtooth carrier

signals of switches S1 and S2 have 180o phase shift. The

control is implemented in a DSP controller. In the voltage

control loop, the voltage error between the output voltage

and its reference voltage is fed to the voltage-loop PI

controller, Gv, to generate the reference signal of the input

current. Then, the current error between this generated

current reference and input current is fed to current-loop PI

controller, Gi, to adjust the duty ratio for switches S1 and S2.

Vgrid

S2 S1

C1

C2

CDC RL

L1D1

D2

L2

L3 L4

Current

Sensor

ADC1

Σ

Σ ADC3

Voltage

Sensor

Voltage

Sensor

Σ

kf

Bias

ADC2 Σ

Const1

kd1

kd2

×

kf

kf

Gv

Bias Σ

kf

Σ Gi

Dpwm1

Dpwm2Const2

S2

S1

Vout,refiref

Control Scheme for interleaved SEPIC converter

Fig. 10. Topology and control scheme of proposed interleaved SEPIC

converter.

B. Design of Critical Components

1) Intermediate capacitor

In a SEPIC converter, the intermediate capacitor has two

tasks: (i) to keep a constant voltage in a switching period;

and (ii) to follow the variation of the input voltage [14]. Thus,

the selection of this capacitor is constrained by both the grid

frequency, fl, and the switching frequency, f

s. The resonant

frequency of the intermediate capacitor and the input

inductor has to be much larger than the line frequency to

avoid the oscillation of the input current. On the other hand,

this resonant frequency has to be much lower than the

switching frequency to reduce the voltage ripple of the

intermediate capacitor. The large voltage ripple causes large

power loss on the intermediate capacitor, which reduces the

efficiency and reduces the life of the intermediate capacitor.

fr=

1

2π√

1

C(L1+L2) (32)

fl<f

r<f

s (33)

In the experiment, the operation frequency of the PFP, 𝑓𝑠,

is set as 150kHz, and the 𝑓𝑟 is set as 10kHz. Thus, the

intermediate capacitor can be selected as 1μF.

2) Inductors and coupling coefficient

A proper coupling coefficient for the entire range of output

DC-link voltage is critical for the performance of the circuit.

A coupling coefficient much higher than the minimum value,

kmin, increases the input current ripple. On the other hand, a

low coupling coefficient increases the size of the coupled

inductor because a larger magnetic core would be needed

without significantly increasing coil turns.

In order to select a proper coupling coefficient, the

inductance of coupled inductors should be taken into

consideration. On one hand, the inductance cannot be too

small. As shown in Table II, the kmin value of the higher

output voltage case is much smaller than that of the lower

output voltage case given a small inductance L2. However,

the kmin should not be too much different for these two cases.

Otherwise, the converter would enter deep DCM in higher



output voltage case, resulting in significantly increased input

current ripple in this case. On the other hand, the inductance

L2 cannot be too large because the coil turns increase largely

for higher inductance L2, resulting in much larger size of the

coupled inductors.

According to Table II, the inductance of 400uH with a

minimum coupling coefficient of 0.8391 is selected for both

coupled inductors. To ensure the DCM operation, the

coupling coefficient is chosen as 0.85.

To implement the coupled inductor, the ETD44 core is

selected, and Litz wire is adopted to build the coils due to the

high switching frequency. Coils of both coupled-inductors

have 24 turns. The air gap is tuned to be 0.3mm to set the

coupling coefficient as 0.85. As the voltage stress between

the two coupled-inductors is really high, a large air gap

(5mm) is incorporated between the two coils. An image of

the coupled inductor, designed for this application, is shown

in Fig. 11.

Fig. 11. Coupled inductor applied in the circuit.

The parameters of all the components in the two-phase

interleaved SEPIC converter with coupled inductor s are

listed in Table IV.

TABLE IV

DESIGN PARAMETERS OF THE CONVERTER

Parameter Symbol Value

Input voltage Vin 85Vac-135Vac, 60Hz

Output voltage Vo 50V-200V

SEPIC capacitor C1, C2 1uF Input inductor L1, L2 400uH

Output inductor L3, L4 400uH

Coupling coefficient k 0.85 Switching Frequency fs 150kHz

Output capacitor CDC 2mF

C. Simulation Results

In order to validate the advantages of the proposed

topology and the designed parameters, simulations are

conducted for 90V output voltage and 180V output voltage

cases. The inductance is set as 400µH for all the inductors

with 0.85coupling efficient. The input voltage is 110Vac.

The simulation results are shown in Fig. 12 and Fig. 13. The

DCM operation can be observed from the inductors current

waveforms. According to the simulation results in Fig. 12,

the input voltage is in phase with the input current. The

power factor is 0.998, and the THD of the input current is

3.5%. According to Fig. 13, the power factor is 0.996, and

THD of the input current is 3.1%. As the output voltage is

higher than the input voltage, the currents of L1 and L2 are

mostly positive. In simulation, an ideal diode bridge is

utilized to rectify the AC input voltage.

Time (s)

Vout

Vin

Iin

Capacitor Voltages, VC1 & VC2

Inductor Currents, iL3 & iL4

Inductor Currents, iL1 & iL2

200

100

0

100

80

200100

0-100-200

40

-4

8

4

0

52.5

0-2.5

0.1 0.12 0.14

Fig. 12. Simulation result for Vin=110Vac, Vo=90V, and Pout=370W.

0

2

4

6

0-2

246

050

100150200

140160180200220

0-100-200

100200

0.15 0.16 0.17 0.18 0.19 0.2Time (s)

0-4

4

Inductor Currents, iL1 & iL2 (A)

Inductor Currents, iL3 & iL4 (A)

Capacitor Voltages, vc1 & vc2 (V)

Vout (V)

Vin (V)

Iin (V)

Fig. 13. Simulation result for Vin=110Vac, Vout=180V, and Pout=360W.

D. Experiment Results

In order to verify the analysis and the design, experimental

investigation of the proposed PFP converter is performed

with the components listed in Table IV. A 500W/110V

prototype is designed, which is shown in Fig. 14. A

TMS320F28335 digital signal processor is used to control

the converter operating in DCM.

Fig. 14. Photograph of the designed two-phase interleaved SEPIC PFP with coupled inductors.

Table IV provides the maximum and minimum output

voltages, which the proposed converter can be operated over

a large range of input voltages. When the input voltage is



85Vac, the output voltage can be stepped down to as low as

50V. When the input voltage is 135Vac, the output voltage

can be stepped up to as high as 200V. The limits of output

voltage vary with the input voltage. For simplicity, a typical

scenario is demonstrated in the experimental section, in

which the input voltage is set as 110Vac, and waveforms

shown for output voltages at 90V and 190V to demonstrate

the step-up and step-down features of the proposed

interleaved SEPIC converter.

The AC input voltage at 110V,RMS (60Hz) is provided by a

controllable Chroma 61605 AC power supply. Figs. 15-18

show the current and voltage waveforms for lower output

voltage case. In Fig. 15, the waveforms of the inductor

currents iL1 and iL2 in DCM operation are shown. With the

switch S1 on, the inductor current iL1 increases rapidly. At the

same time, the inductor current iL2 drops rapidly until the

current through the diode decreases to zero. In Fig. 16, the

waveforms of the inductor currents iL2 and iL3 in DCM

operation are presented. Since the average input current was

lower than the average output current, the inductor currents

iL2 drops below zero, while the inductor currents iL3 is

maintaining a positive minimum current value. The sum of

inductor current iL2 and iL3 decreases and gets very close to

zero. At this moment, switch S2 turns on. In other words, the

converter almost works in BCM. Hence, the experimental

results are consistent with the theoretical analyses.

In Fig. 17, the zoom-out waveforms of inductor current iL1

and iL2 are shown. The waveforms of the input voltage, input

current and output voltage at steady state are shown in Fig.

18. The output voltage is regulated at 90V, and the output

power is 370W with the power factor measured as 0.997.

Fig. 15. Waveforms of drive pulse, inductor currents iL1 and iL2 in lower output voltage case.

Fig. 16. Waveforms of drive pulse, inductor currents iL2 and iL3 in lower output voltage case.

Fig. 17. Waveforms of drive pulse, inductor currents iL1 and iL2 in lower


Fig. 18. Steady-state waveforms of output current, input current and input voltage in lower output voltage case, Pout=370W.

Figs. 19-22 demonstrate the current and voltage

waveforms for higher output voltage case. In Fig. 19, the

waveforms of the inductor currents iL1 and iL2 in DCM

operation are presented. With the switch S1 on, the inductor

current iL1 increases rapidly. At the same time, the inductor

current iL2 drops quickly until the current through the diode

becomes zero. In Fig. 20, the waveforms of the inductor

currents iL1 and iL4 in DCM operation are given. Since the

average input current is higher than the average output

current, the inductor current iL4 becomes negative, while the

inductor current iL1 has a positive minimum value. There are

six operation modes in a switching period, and the converter

works in DCM. In Section III, the theoretical analysis shows

that the converter would work under DCM in higher output

voltage case if the coupling coefficient k is larger than the

kmin of the higher output voltage case. Thus, the experimental

results confirm the theoretical analysis.

The zoom-out waveforms of inductor current iL1 and iL2

are shown in Fig. 21. In Fig. 22, the waveforms of the input

voltage, input current and output voltage at steady state are

shown. The output voltage is regulated at 190V, and the

output power is 402W with the power factor equal to 0.991.

In Fig. 18 and Fig. 22, the zero-crossing distortion of input

currents happens due to the forward voltage drop of diodes in

the diode bridge, which is utilized to rectify the AC input

voltage. Furthermore, when the input voltage is close to zero,

the input current cannot ramp up quickly due to small

voltages across inductors L1-L4. The current slew rate needed

to reach the reference input current exceeds the available

current slew rate, so the input current lags behind the

reference input current for a short period of time, resulting in

the zero-crossing distortion of the input current.

The THD of input current is shown in Table V for Vout

=90V and Vout =190V at Vin =110V at different power levels.



The efficiency curve at Vin=110Vac is shown in Fig. 23. The

efficiency is 96% at 500W.

Fig. 19. Waveforms of drive pulse, inductor currents iL1 and iL2 in higher






Fig. 22. Steady-state waveforms of output voltage, input current and input

voltage in higher output voltage case, Pout=402W.

TABLE V

THD OF INPUT CURRENT VS. POWER AT DIFFERENT VOUT CASES

Lower Vout Case Higher Vout Case

Power (W) THD (%) Power (W) THD (%)

105 9.8 138 10.3

179 7.8 268 8.2

262 6.7 340 6.9 370 6.0 423 6.2

495 5.7 498 5.8

88%

90%

92%

94%

96%

98%

100%

100 180 260 340 420 500Output Power (W)

Eff

icie

ncy

(%

)

Higher Vout Case (calc.)

Lower Vout Case (calc.)

Lower Vout Case (meas.)

Higher Vout Case (meas.)

Fig. 23. Calculated and measured efficiency curves of the proposed PFP at

Vin=110Vac.

V. CONCLUSION

This paper proposed a novel interleaved two-phase SEPIC

PFP with inductors directly coupled. The directly coupled

inductors can reduce the number of magnetic components,

decrease the input current ripple. The key circuit and design

features are summarized as follows. The power level of

SEPIC PFP is improved by interleaving two SEPIC

converters, the voltage and current stresses of the diodes and

switches are largely reduced, improving the power level up

to 500W. High efficiency is maintained over a wide range of

DC-link voltage. The converter is designed to operate in

DCM in order to achieve ZVS for switches and ZCS for

diodes. The input current ripple is reduced by properly

designing the coupled inductors. The inductance and

coupling coefficient are carefully selected for the coupled

inductors to ensure the DCM operation in close proximity to

BCM operation over the wide range of DC-link voltage.

A 500W prototype is built to validate the advantages of

this proposed PFP. The experimental results show the

proposed interleaved SEPIC PFP can provide a wide output

DC-Link voltage from 90V to 190V at 110Vac input voltage,

and the efficiency is over 96% at 500W over a wide range of

DC-link voltage with power factor over 0.99.

VI. ACKNOWLEDGMENT

This work is partly sponsored by the U.S. National

Science Foundation Grant number 1507546, which is also

gratefully acknowledged.

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Chuan Shi (S’16) received the B.S. degree in

electrical engineering from Wuhan University,

Wuhan, China in 2013. He is currently working

toward the Ph.D. degree at the University of Maryland, College Park.

He was an Intern with Altera, Inc., TX, USA,

during summer 2015. He was the recipient of 2016 Harry K. Wells Energy Research

Fellowship from the University of Maryland

Energy Research Center. His current research interests include modeling, analysis, design, and

control of power electronic converters for plug-

in hybrid electric vehicles (PHEVs), as well as the power management of battery/ultracapacitor hybrid energy storage systems (HESS) for PHEVs.

Alireza Khaligh (S’04–M’06–SM’09) is an

Associate Professor at the Electrical and

Computer Engineering (ECE) Department and the Institute for Systems Research (ISR) in the

University of Maryland (UMD). His major

research interests include modeling, analysis, design, and control of power electronic

converters for transportation electrification,

renewable energies, energy harvesting, and microrobotics. He is an author/coauthor of over

140 journal and conference papers. Dr. Khaligh

is an Editor of the IEEE Transactions on Vehicular Technology, an Associate Editor for IEEE Transactions on Power

Electronics, and an Associate Editor for IEEE Transactions on

Transportation Electrification. Dr. Khaligh is the recipient of various awards and recognitions including

the 2015 Inaugural ISR Junior Faculty Fellowship from the Institute for

Systems Research of UMD, the 2013 George Corcoran Memorial Award from the ECE Department of UMD, 2013 Best Vehicular Electronics Paper

Award from the IEEE Vehicular Technology Society, and 2010 Ralph R. Teetor Educational Award from the Society of Automotive Engineers. Dr.

Khaligh was the General Chair of the 2016 IEEE Applied Power Electronic

Conference and Expo (APEC), the Program Chair of the 2015 IEEE APEC, the Assistant Program Chair of the 2014 IEEE APEC, the General Chair of

the 2013 IEEE Transportation Electrification Conference and Expo (ITEC),

and the Program Chair of the 2011 IEEE Vehicle Power and Propulsion Conference (VPPC). He is a Distinguished Lecturer of the IEEE Vehicular

Technology Society and also a Distinguished Lecturer of the IEEE Industry

Applications Society.

Haoyu Wang received his bachelor degree with distinguished honor from Zhejiang University in

Hangzhou, China. He received his master and

Ph.D. degrees both in electrical engineering from the University of Maryland, College Park, MD,

USA. He worked as a design engineer with

GeneSiC Semiconductor Inc. Dulles, VA, in summer, 2012. He is currently a tenure track

assistant professor in the School of Information

Science and Technology at ShanghaiTech University, Shanghai, China. His research

interests include power electronics, plug-in

electric and hybrid electric vehicles, the applications of wide band-gap semiconductors,

renewable energy harvesting, and power management integrated circuits.

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