01 asic design flow

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ASIC Design Flow TS. Hoang Trang ThS. Pham Dang Lam

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ASIC Design Subject

Idea

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ASIC Design Subject

Hardware Develop

Idea

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ASIC Design Subject

Hardware Develop

Idea

Third party

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ASIC Design Subject

Hardware Develop

Third party

Idea

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ASIC Design Subject

Layout

Factory

Hardware Develop

Third party

Idea

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ASIC Design Subject

Layout

Physical ChipFactory

Hardware Develop

Third party

Idea

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ASIC Design Subject

Layout

Physical ChipFactory

Hardware Develop

Third party

Idea

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ASIC Design Subject

Design Methodology

Fully Custom Semi Custom

Standard Cells Gate Arrays Programmable Logic

F P G A

P L D

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ASIC Design Subject

Design Methodology

Fully Custom Semi Custom

Standard Cells Gate Arrays Programmable Logic

F P G A

P L D

ASIC Design Flow(Application-specific integrated circuit)

FPGA Design Flow(Field Programmable Gate Array)

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ASIC Design Subject

•Use predesigned, pretested and pre_characterized logic cells from the standards-cell library as building blocks.

•The chip layout is customized

•Advantages: Save design time and money, reduce risk compared to full-custom design

•Disadvantages: Still incurs high none-recurring-engineering (NRE) cost and long manufacture time

•Design a chip from scratch

•Engineer design some or all the logic cells, circuits, and the chip layout specifically for a full-custom IC

•Advantages: Complete flexibility, high degree of optimization performance ad area

•Disadvantages: Large amount of design effort, expensive

Full Custom Standard Cell Base

•Parts of the chip are pre-fabricated, and other parts are custom fabricated for particular customer’s circuit.

•Idential base cells are pre-fabricated in the form of a 2-D array on a gate-array (this partially finished chip is called gate-array template).

•This wires between the transistors inside the cells and between the cells are custom fabricated for each customer

•Custom mask are made for the wiring only

Gate Array

•A PLD is a general-purpose chip for implementing logic circuitry.

•Transistors and wires are already prefebricated on a PLD

•Logic cells and interconnect can be programmed by end-user to implement specific circuitry

•No need to create custom masks for each customer

PLD

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ASIC Design Subject

Design

Manufacturing

Packaging/Test

Fabrication/Test

Mask Production

ASIC Design Flow

Hardware Development Activities

Shipping

Back end Process

Front end Process(Wafer Process)

Back end Design

Front end Design

GDS

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ASIC Design Subject

Product

Hardware

Software

Middleware

Device driver

Compiler, OS

Board, Hardware Flatform

SemiconductorDevice

Discrete Device

IntegratedDevice

LedBJTDiodeFET

DigitalAnalogMix Signal

Develop & Evaluate Design Kit

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ASIC Design Subject

Product

Hardware

Software

Middleware

Device driver

Compiler, OS

Board, Hardware Flatform

SemiconductorDevice

Discrete Device

IntegratedDevice

LedBJTDiodeFET

DigitalAnalogMix Signal

Develop & Evaluate Design Kit

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ASIC Design Flow

Cell Base & Custom Design Flow Concepts

Custom Design Flow

Cell Base Design Flow

ASIC vs. FPGA Design Flow

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ASIC Design Flow


Custom Design Flow



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ASIC Design Products

Products for Cell Base Design Flow

Products for Custom Design Flow


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ASIC Design Products

Products for Cell Base Design Flow

Products for Custom Design Flow

MCU: I2C, DMAC, SBI, SCI, PCI, UART, TIMER, CAN, etc.DSP: Digital Filter, router, etc.

Analog Device: ADC, PLL, Amplier, etc.Memory: ROM, RAM, etcMisSignal: RFID, etc


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Custom Design Flow

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Custom Design Flow

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Custom Design Flow

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CMOS Level


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Custom Design Flow

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Symbol Level

CMOS Level


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Custom Design Flow

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ADC IP


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Build Library

from the scratch

Custom Design Flow

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ADC IP


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Cell BaseDesign Flow

y = !(x1 & x2);

y = !(x1 I x2);

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y = !(x1 & x2);

y = !(x1 I x2);

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RTL Level


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y = !(x1 & x2);

y = !(x1 I x2);

matching

matching

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y = !(x1 & x2);

y = !(x1 I x2); matching

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UART IPmatching


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Ready Library


y = !(x1 & x2);

y = !(x1 I x2);

matching

matching

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UART IP


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•Use predesigned, pretested and pre_characterized logic cells from the standards-cell library as building blocks.

•The chip layout is customized

•Advantages: Save design time and money, reduce risk compared to full-custom design

•Disadvantages: Still incurs high none-recurring-engineering (NRE) cost and long manufacture time

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ASIC Design Flows

Cell Base Design Flow Custom Design Flow

•Design a chip from scratch

•Engineer design some or all the logic cells, circuits, and the chip layout specifically for a full-custom IC

•Advantages: Complete flexibility, high degree of optimization performance ad area

•Disadvantages: Large amount of design effort, expensive


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comparision Cell Base Design Custom Design

Integration Density

X

Speech X

Chip Scale X

Support Tools X

Time to market X

Risk reduction X

http://www.ami.ac.uk/courses/ami4407_dicdes/u03/#3.2http://www.eng.uwo.ca/people/wwang/ece616a/616_extra/notes_web/1_dintro.pdfhttp://www.ece.ucdavis.edu/~bbaas/116/notes/Handout.std.cell.design.pdf


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ASIC Design Flow


Custom Design Flow



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Custom Design Flow

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Design flow Support Tools Output

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Specifications

Design flow Support Tools Output

<file>.docx/xls/ppt

Custom Design Flow

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Specifications

Schematic

Design flow Support Tools

Composer

Output

<file>.docx/xls/ppt

Custom Design Flow

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Specifications

Schematic

Netlist extractionNG


Composer

Composer

Output

<file>.docx/xls/ppt

<file>.cdl, <file>.net

Custom Design Flow

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Specifications

Schematic

Pre_Layout Verification



Composer

Composer

HSpice

Output

<file>.docx/xls/ppt


<file>.wf, <file>.tr

Custom Design Flow

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Specifications

Schematic


Layout



Composer

Composer

HSpice

Virtuoso

Output

<file>.docx/xls/ppt



<file>.gds

Custom Design Flow

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Specifications

Schematic


Layout

Layout Verification



Composer

Composer

HSpice

Virtuoso

Calibre

Output

<file>.docx/xls/ppt



<file>.gds

<file>.db (DRC) <file>.svdb(LVS)

NG

DRC: Design Rule CheckLVS: Layout Versus Schematic

Custom Design Flow

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Specifications

Schematic


Layout

Layout Verification

RC_extraction

Pos_LayoutVerification



Composer

Composer

HSpice

Virtuoso

Calibre

Output

<file>.docx/xls/ppt



<file>.gds

<file>.db (DRC) <file>.svdb(LVS)

NG

DRC: Design Rule CheckLVS: Layout Versus Schematic

Spectre SimulatorPritime

Report file<file>.lib/.db

Custom Design Flow

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ASIC Design Flow


Custom Design Flow



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Design flowSupport Tools (Languages)

Output


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Specifications


Output

<file>.docx/xls/ppt


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Specifications


Output

<file>.docx/xls/ppt


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Specifications


Output

<file>.docx/xls/ppt


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Specifications

System Level Design


Output

<file>.docx/xls/ppt

Flatform / ModelG++ (C++ with

Sysem C class)


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Specifications

System Level Design

RTL Design


VI, NotePath++ (Verilog/VHDL)

Output

<file>.docx/xls/ppt

<file>.v


Sysem C class)


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Specifications

System Level Design

RTL Verification

RTL DesignNG



Output

<file>.docx/xls/ppt

<file>.v

Report file, wave form

VCS/ModelSim, etc(Verilog/ VHDL)


Sysem C class)


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Specifications

System Level Design

RTL Verification

Synthesis

RTL DesignNG



DC compiler

Output

<file>.docx/xls/ppt

<file>.v


<file>.v (netlist), <file>.sdf,Reports



Sysem C class)

NG


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Specifications

System Level Design

RTL Verification

Synthesis

Netlist Verification

RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG



Sysem C class)

NG


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Specifications

System Level Design

RTL Verification

Synthesis


DFT

RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG


FastScan/Tmax/… Report file, Netlist


Sysem C class)

NG


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Specifications

System Level Design

RTL Verification

Synthesis


DFT

STA

RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG

Prime Time Report file, Netlist




Sysem C class)

NG


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Specifications

System Level Design

RTL Verification

Synthesis


DFT

STA

RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG



ICC compiler <file>.gdsPlace&Route



Sysem C class)

NG


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Specifications

System Level Design

RTL Verification

Synthesis


DFT

STA

RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG






Sysem C class)

NG

FrontEnd

BackEnd


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Specifications


Output

<file>.docx/xls/ppt

Design the one bit adder: + Three inputs (A, B, Cin) + Two output (S, Cout)


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Specifications

System Level Design


Output

<file>.docx/xls/ppt

Flatform / ModelsG++ (C++ with

Sysem C class)

C++Methods in

SystemC class

Flatform/Model concepts

TLM class


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Specifications

System Level Design

RTL Design

Design flow

Design vs. ModelCoding style

Verilog/VHDL language

VI, NotePath++ (Verilog/VHDL) <file>.v

Support Tools (Languages)

Output

<file>.docx/xls/ppt


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Specifications

System Level Design

RTL Verification

RTL Design

Design flow



Verification Environment

Check list

VI, NotePath++ (Verilog/VHDL) <file>.v


Output

<file>.docx/xls/ppt

VCS tool


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Specifications

System Level Design

RTL Verification

Synthesis

RTL Design

Design flow

NG VI, NotePath++ (Verilog/VHDL)

DC compiler

<file>.v




NG

Report analysis

Tool commands

Timing analysis


Output

<file>.docx/xls/ppt


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Specifications

System Level Design

RTL Verification

Synthesis


RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG



Sysem C class)

NG

Report analysis

Tool commands


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Specifications

System Level Design

RTL Verification

Synthesis


DFT

RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG




Sysem C class)

NG

LBISTMBIST


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Specifications

System Level Design

RTL Verification

Synthesis


DFT

STA

RTL DesignNG



DC compiler

Formality

Output

<file>.docx/xls/ppt

<file>.v



Report file

NG





Sysem C class)

NG

Report analysis

Tool commands

Timing analysis


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DFT

STA


Output




Tool Commands

Library UsingTiming/Area…

analysis

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ASIC Design Flow


Custom Design Flow



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ASIC FPGA

1986: Synopsys1987: TSMC1988: Cadence

1983: Altera1984: Xilinx

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Appendix

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ASSP : Application Specific Standard Product (DSP, Mircro Processor)ASCP: Application Specific Custom ProductGDS: Graphic Data System

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Appendix

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Language Design Level

Simulation

Synthesizeable

Explicit Hardware Resource

Elapsed Time

Sequence

C++ Transaction Yes No No No Yes

SystemC Transaction Yes Yes* No Yes Yes

VHDL RTL Yes Yes* Yes* Yes Yes

Verilog RTL Yes Yes* Yes* Yes Yes

Verilog/VHDL Netlist

Gate Yes Yes Yes Yes Yes

Yes*: Base on the constraints to be able or not

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Q & AQ & A

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1. “Cell Characterization Concepts” slide - SIVACO company

2. Henrik Eriksson and Per Larsson-Edefors, Tomas Henriksson and Christer Svensson, “Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study”

3. TSMC 65nm CLN65LP HVT Process 1.2-Volt 12-Track AdvantageTM v2.1Standard Cell Library Databook

4. http://www.ami.ac.uk/courses/ami4407_dicdes/u03/

5. http://www.eng.uwo.ca/people/wwang/ece616a/616_extra/notes_web/1_dintro.pdf

6. http://www.ece.ucdavis.edu/~bbaas/116/notes/Handout.std.cell.design.pdf

1. “Cell Characterization Concepts” slide - SIVACO company

2. Henrik Eriksson and Per Larsson-Edefors, Tomas Henriksson and Christer Svensson, “Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study”

3. TSMC 65nm CLN65LP HVT Process 1.2-Volt 12-Track AdvantageTM v2.1Standard Cell Library Databook

4. http://www.ami.ac.uk/courses/ami4407_dicdes/u03/

5. http://www.eng.uwo.ca/people/wwang/ece616a/616_extra/notes_web/1_dintro.pdf

6. http://www.ece.ucdavis.edu/~bbaas/116/notes/Handout.std.cell.design.pdf

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Reference

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Q1/ Why “Static Timing Analysis” step is only done after “Place and Route” step in FPGA design flow ?

Q2/ In FPGA and ASIC design flows, which ‘s performances such as area and timing are better?

Q3/ Why is “Time to Market” of FPGA design flow faster ?

Q1/ Why “Static Timing Analysis” step is only done after “Place and Route” step in FPGA design flow ?

Q2/ In FPGA and ASIC design flows, which ‘s performances such as area and timing are better?

Q3/ Why is “Time to Market” of FPGA design flow faster ?

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Question

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Question

01 asic design flow

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