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12/2012 1 ASIC Design Flow TS. Hoang Trang ThS. Pham Dang Lam

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This book can help you more understand about ASIC design flow step by step, with some example in Verilog language

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  • 12/2012

    1

    ASIC Design Flow

    TS. Hoang Trang

    ThS. Pham Dang Lam

  • 12/2012

    2

    Specifications

    System Level

    Design

    RTL Verification

    Synthesis

    Netlist Verification

    DFT

    STA

    RTL Design NG

    Design flow Support Tools

    (Languages)

    VI, NotePath++

    (Verilog/VHDL)

    DC compiler

    Formality

    Output

    .docx/xls/ppt

    .v

    Report file,

    wave form

    .v (netlist),

    .sdf,

    Reports

    Report file

    NG

    Prime Time Report file, Netlist

    VCS/ModelSim,

    etc(Verilog/ VHDL)

    ICC compiler .gds Place&Route

    FastScan/Tmax/ Report file, Netlist

    Flatform / Model SystemC (C++ with

    Sysem C class)

    NG

    Front

    End

    Back

    End

    Cell Base Design Flow

  • 12/2012

    3

    Specifications

    Design flow Support Tools

    (Languages) Output

    .docx/xls/ppt

    Design the one bit adder:

    + Three inputs (A, B, Cin)

    + Two output (S, Cout)

    Cell Base Design Flow

  • 12/2012

    4

    How to start specification ?

    Core

    Bus

    DSP

    Interface

    IPs

    Control

    Data

    Specifications

  • 12/2012

    5

    Core

    Bus

    DSP

    Interface

    IPs

    Control

    Data

    Specifications How to start specification ?

  • 12/2012

    6

    Core

    Bus

    DSP

    Interface

    IPs

    Control

    Data

    Specifications How to start specification ?

  • 12/2012

    7

    Core

    Bus

    DSP

    Interface

    IPs

    Control

    Data

    Specifications How to start specification ?

  • 12/2012

    8

    Core

    Bus

    DSP

    Interface

    IPs

    Control

    Data

    Specifications

    ???

    How to start specification ?

  • 12/2012

    9

    Specifications How to start specification ?

  • 12/2012

    10

    Specifications How to start specification ?

  • 12/2012

    11

    Specifications How to start specification ?

  • 12/2012

    12

    Specifications How to start specification ?

  • 12/2012

    13

    Specifications

    Controller

    How to start specification ?

  • 12/2012

    14

    Cell Base Design Flow Specifications

  • 12/2012

    15

    Specifications How to start specification ?

  • 12/2012

    16

    Specifications How to start specification ?

  • 12/2012

    17

    Cell Base Design Flow Specifications

    DataPath

  • 12/2012

    18

    Specifications

    ALU - Controller

    ALU - Data Path

    Sel_1 Sel_2 Sel_6

    W

    K

    f

    How to start specification ?

  • 12/2012

    19

    Specifications

    Network-On-Chip (NoC) has been proposed as replacing

    traditional bus architectures to solve complexity issues

    such as synchronous frequency, infrastructure

    interconnect and connective protocols when integrating

    hundreds IP core or systems

    http://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html

    How to start specification ?

  • 12/2012

    20

    Specifications

    Header

    flit BW RC VA SA ST LT

    Body flit BW RC VA SA ST LT

    BW: Buffer write

    RC: Router computation

    VA: Virtual allocation

    SA: Switch allocation

    ST: Switch traversal

    LT : Link traversal

    Amit Kumar Li-Shiuan Peh, Parth Kundu, Niraij K.Jha, Toward Ideal On-Chip Communication Using Express Virtual Channels, micr-28-01-kuma.3d.IEEE 2008, Princeton University.

    How to start specification ?

  • 12/2012

    21

    Specifications

    WEST

    NORTH

    EAST

    SOUTH

    IP

    How to start specification ?

  • 12/2012

    22

    Specifications How to start specification ?

  • 12/2012

    23

    Specifications

    http://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html

    DataPath Controller

    How to start specification ?

  • 12/2012

    24

    Specifications

    DataPath Controller

    How to start specification ?

  • 12/2012

    25

    Specifications

    DataPath Controller

    How to start specification ?

  • 12/2012

    26

    Specifications

    How to model a behavior of one traffic light ?

    Red Green : 30 s Green Yellow : 27s Yellow Red : 3 s

    How to start specification ?

  • 12/2012

    27

    Specifications

    How to model a behavior of traffic light system?

    Red Green : 30 s Green Yellow : 27s Yellow Red : 3 s

    How to start specification ?

  • 12/2012

    28

    ASSIGNMENT

    Try to detail one of design in hardware structure

    Note that use many graphic and true table instead of using behavior sentences

  • 12/2012

    29

    Pipeline Concept

    Pipe line not using state machine

  • 12/2012 30

    CPU & Proccessing

  • 12/2012 31

    IFetch Reg/Dec Exec Wr

    Proccessing

    Mem

  • 12/2012 32

    Pileline Process

  • 12/2012 33

    Hazard &Solution

    Structure Hazard

    Data Hazard

    Control Hazard

  • 12/2012 34

    Structure Hazard

  • 12/2012 35

    Structure Hazard

  • 12/2012 36

    Structure Hazard

  • 12/2012 37

    Structure Hazard

  • 12/2012 38

    Structure Hazard

  • 12/2012 39

    Structure Hazard

  • 12/2012 40

    Hazard &Solution

    Structure Hazard

    Data Hazard

    Control Hazard

  • 12/2012 41

    Data Hazard

  • 12/2012 42

    Data Hazard

  • 12/2012 43

    Data Hazard

  • 12/2012 44

    Hazard &Solution

    Structure Hazard

    Data Hazard

    Control Hazard

  • 12/2012 45

    Control Hazard

    Jump

    Jump for condition

    Others

  • 12/2012 46

    Using Noop

    Moving the jump points to the other

    places

    Guessing

    Control Hazard

  • 12/2012 47

    Control Hazard

  • 12/2012 48

    Control Hazard

  • 12/2012 49

    Solution

  • 12/2012

    50

    DataPath

    State Machine - Pipeline Specifications

    Unit 01 Unit 02 Unit 03

    Write Mem

    GCU

    Viterbi

    Write Mem

    GCU Write Mem

  • 12/2012 51

    Thc Hin Ti c T - Viterbi C Ch ng

    ng Write Mem GCU Viterbi

    Tun T

  • 12/2012 52

    Thc Hin Ti c T - Viterbi C Ch ng

    ng Write Mem GCU Viterbi

    ng ng

    Tun T V V

  • 12/2012 53

    Thc Hin Ti c T - Viterbi C Ch ng

    ng Write Mem GCU Viterbi

    Write Mem

    Write Mem GCU

    Write Mem GCU Viterbi

    Write Mem GCU Viterbi

    GCU Viterbi

    Viterbi

    ng ng

    Tun T V V

  • 12/2012 54

    Thc Hin Ti c T - Viterbi C Ch ng

    ng Write Mem GCU Viterbi

    Write Mem

    Write Mem GCU

    Write Mem GCU Viterbi

    Write Mem GCU Viterbi

    GCU Viterbi

    Viterbi

    State 1

    State 2

    State 3

    State 3

    State 4

    State 5

    ng ng

    Tun T V V

  • 12/2012 55

    Thc Hin Ti c T - Viterbi C Ch ng

    ng Write Mem GCU Viterbi

    Write Mem

    Write Mem GCU

    Write Mem GCU Viterbi

    Write Mem GCU Viterbi

    GCU Viterbi

    Viterbi

    State 1

    State 2

    State 3

    State 3

    State 4

    State 5

    Loop

    ng ng

    Tun T V V

  • 12/2012

    56

    State Machine - Pipeline Specifications

    X cycles Y cycles Z Cycles

    Cycle Delay = max {X, Y, Z}

    Cnt = cnt + 1 cnt == cycle_delay state_ena = 1

  • 12/2012

    Handshake- Pipeline Specifications

    Viterbi GCU Write Mem

    Notify

    Confirm/Finish

  • 12/2012

    Handshake- Pipeline Specifications

    Notify

    Confirm/Finish

    How to cat the notify and confirm Prototype ?

    Many to solve notify tasks ?

    How to control and store the output data ?

    How to improve the design ?


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