19.02.20 08:50CSCI 150 Introduction to Digital and Computer

System Design Lecture 3: Combinational Logic Design VI

Jetic Gū2020 Winter Semester (S1)

Overview• Focus: Arithmetic Functional Blocks

• Architecture: Combinatory Logical Circuits

• Textbook v4: Ch4 4.3, 4.7; v5: Ch2 2.9, Ch3 3.10

• Core Ideas:

1. Subtraction I

2. VHDL

Review

Summary

P0 Binary Adder

Unsigned Binary Adder

1-bit Half Adder

• Half adderinput � , � output � , �

X YS C

Review

P0 Binary Adder

X+Y

Augend

Carries

Addend

Sum S

C

+

InputOutput

1-bit Half Adder

Review

P0 Binary Adder

X+Y

Augend

Carries

Addend

Sum S

C

+

InputOutput

158 CHAPTER 3 / COMBINATIONAL LOGIC DESIGN

The half adder can be implemented with one exclusive-OR gate and one AND gate, as shown in Figure 3-40.

Full Adder

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. Besides the three inputs, it has two outputs. Two of the input variables, denoted by X and Y, represent the two significant bits to be added. The third input, Z, rep-resents the carry from the previous lower significant position. Two outputs are neces-sary because the arithmetic sum of three bits ranges in value from 0 to 3, and binary 2 and 3 need two digits for their representation. Again, the two outputs are designat-ed by the symbols S for “sum” and C for “carry”; the binary variable S gives the value of the bit of the sum, and the binary variable C gives the output carry. The truth table of the full adder is listed in Table 3-12. The values for the outputs are determined from the arithmetic sum of the three input bits. When all the input bits are 0, the out-puts are 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output is a carry of 1 if two or three inputs are equal to 1. The maps for the two outputs of the full adder are shown in Figure 3-41. The simplified sum-of-product functions for the two outputs are

S = X YZ + XYZ + XY Z + XYZ

C = XY + XZ + YZ

The two-level implementation requires seven AND gates and two OR gates. However, the map for output S is recognized as an odd function, as discussed in

XY

S

C

FIGURE 3-40Logic Diagram of Half Adder

TABLE 3-12Truth Table of Full Adder

Inputs Outputs

X Y Z C S

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

M03_MANO0637_05_SE_C03.indd 158 23/01/15 1:51 PM

1-bit Full Adder

• Full adderinput � , � , � ;output � , �

X Y ZS C

Review

P0 Binary Adder

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutputX

YZ

1-Bit Binary Adder

S

C

SC

1-bit Full Adder

• Full adderinput � , � , � ;output � , �

X Y ZS C

Review

P0 Binary Adder

• Half adder1input � , � output � , �

X YS′� C′�

• Half adder2input � , � output � , �

S′� ZS C′�′�

C = C′� + C′�′�

XY

Z

1-Bit Half Adder

S

C C

1-Bit Half Adder

S

C

S

n-bit Full Adder

Review

P0 Binary Adder

A0 B0 0

1-Bi

t Bin

ary

Adde

r

S C

S0

1-Bi

t Bin

ary

Adde

r

S C

S1

1-Bi

t Bin

ary

Adde

r

S C

S2

1-Bi

t Bin

ary

Adde

r

S C

S3

A1 B1 A2 B2 A3 B3

…

n-bit Full Adder• Ripple Carry Adder

Review

P0 Binary Adder

A0 B0 0

1-Bi

t Bin

ary

Adde

r

S C

S0

1-Bi

t Bin

ary

Adde

r

S C

S1

1-Bi

t Bin

ary

Adde

r

S C

S2

1-Bi

t Bin

ary

Adde

r

S C

S3

A1 B1 A2 B2 A3 B3

…

Unsigned Binary Subtraction I

Summary

P1 Subtraction

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

0

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

InputOutput

0101101001100011

0

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Review

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

InputOutput

0101101001100011

This method works when the Minuend is greater than the Subtrahend!

0

Unsigned Binary Subtraction

• We learned to perform subtraction, by subtracting the smaller number from the greater number

Review

P1 Subtraction

X > Y, F = X − Y

Unsigned Binary Subtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Concep

t

P1 Subtraction

0011010110

−1001100011

Minuend

Borrows

Subtrahend

Difference

InputOutput

0101101001100011

0

Unsigned 1-bit Binary Subtraction

• Input: Minuend � and Subtrahend � Previous borrow �

• Output: Last borrow � , difference �

X YZ

B D

Concep

t

P1 Subtraction

00

−11

Minuend �X

Borrows

Subtrahend �Y

Difference �D

InputOutput

0011

1B Z

Unsigned 1-bit Binary Subtraction

• Input: Minuend � and Subtrahend � Previous borrow �

• Output: Last borrow � , difference �

X YZ

B D

Concep

t

P1 Subtraction

00

−11

Minuend �X

Borrows

Subtrahend �Y

Difference �D

InputOutput

0011

1B Z

X Y Z B D

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Unsigned 1-bit Binary Subtraction

• Implementation using 3-to-8 Decoder

• �

• �

B = Σm(1,2,3,7)

D = Σm(1,2,4,7)

Concep

t

P1 Subtraction

XYZ

1-Bit Binary Subtractor

B

D

BD

Unsigned BinarySubtraction

• Input: Minuend and Subtrahend Previous borrow

• Output: Last borrow, difference

Concep

t

P1 Subtraction

0011010110

−1001100011

InputOutput

0101101001100011

0Minuend �X

Borrows

Subtrahend �Y

Difference �D

B Z

Technology• 1 bit Unsigned Subtractor

Unsigned BinarySubtraction

Concep

t

P1 Subtraction

0011010110

−1001100011

InputOutput

0101101001100011

0Minuend �X0:n−1

Borrows

Subtrahend �Y0:n−1

Difference �D0:n−1

B Z

Technology• 1 bit Unsigned Subtractor

X0Y0Z

1-Bit Binary Subtractor

B

D D0

X1Y1

1-Bit Binary Subtractor

B

D D1

…

Hardware Description Language

Summary

P2 VHDL

VHDL (VHSIC-HDL): Very High Speed Integrated Circuit Hardware Description Language

What is HDL• Designing complex circuits using logic circuit diagrams is inefficient

• Hardware Description Language

• Like programming language, describes hardware structures and behaviours

• More efficient

• Common languages

• Verilog

• VHDL

Concep

t

P2 VHDL

Creating a AND1INV model

Tutoria

l

P2 VHDL

Equivalent

Creating a AND1INV model

Tutoria

l

P2 VHDL

1. Go to the File menu, select New command. Select Model Wizard and click OK

Creating a AND1INV model

Tutoria

l

P2 VHDL

2. Source: Create a new, empty model, Destination: Create a new symbol with the specified model attached. Click Next

Creating a AND1INV model

Tutoria

l

P2 VHDL

2. Source: Create…, Destination: Open the… . Click Next . Select VHDL, Enter name AND1INV.

Creating a AND1INV model

Tutoria

l

P2 VHDL

3. Type the Name and select the Function accordingly, then press Add Single Bit, click Finish to create the model file.

• This is where you define all inputs and outputs

• Input: POS

• Input: NEG

• Output: Out1

Creating a AND1INV model

Tutoria

l

P2 VHDL

3. Type the Name and select the Function accordingly, then press Add Single Bit, click Finish to create the model file.

• This is where you define all inputs and outputs

• Input: POS

• Input: NEG

• Output: Out1

Creating a AND1INV model

Tutoria

l

P2 VHDL

4. The programme will ask you for Pin Location assignment. Just click Next.

Creating a AND1INV model

Tutoria

l

P2 VHDL

Creating a AND1INV model

Tutoria

l

P2 VHDL

Port definition here

Creating a AND1INV model

Tutoria

l

P2 VHDL

Port definition here

Internal description where we implement

Creating a AND1INV model

Tutoria

l

P2 VHDL

5. Type: OUT1 <= POS AND NOT NEG AFTER 1NS; This is the Boolean description of the OUT1 port

OUT1 <= POS AND NOT NEG AFTER 1NS;

Transferring BooleanOperators

Things do not happensimultaneously

Creating a AND1INV model

Tutoria

l

P2 VHDL

5. Type: OUT1 <= POS AND NOT NEG AFTER 1NS; This is the Boolean description of the OUT1 port

OUT1 <= POS AND NOT NEG AFTER 1NS;

Transferring BooleanOperators

Things do not happensimultaneously

Creating a AND1INV model

Tutoria

l

P2 VHDL

6. VHDL -> Compile. A message should say Compile Completed - 0 errors

OUT1 <= POS AND NOT NEG AFTER 1NS;

Transferring BooleanOperators

Things do not happensimultaneously

Creating a AND1INV model

Tutoria

l

P2 VHDL

6. VHDL -> Compile. A message should say Compile Completed - 0 errors

OUT1 <= POS AND NOT NEG AFTER 1NS;

Transferring BooleanOperators

Things do not happensimultaneously

Run Simulation

Tutoria

l

P2 VHDL

6. VHDL -> Run Simulation. The text should turn grey (not editable). Click Run Button to start simulator, click I/O panel Page button

RunI/O Page

Run Simulation

Tutoria

l

P2 VHDL

7. Play with the buttons in the I/O panel

value fixing: 0

decrease value (1 -> 0)increase value (0 -> 1)

Run Simulation

Tutoria

l

P2 VHDL

8. Changes are reflected in the Timing Diagram. Use Zoom panel to Zoom In and Out

Zoom-in

Zoom-out

Reset

Exe1: 1-bit Half Adder

Practic

e

P2 VHDL

• Create a new component in VHDL called HalfAdder1

• Input: X, Y

• Output: S, C

• Don’t use AFTER

158 CHAPTER 3 / COMBINATIONAL LOGIC DESIGN

The half adder can be implemented with one exclusive-OR gate and one AND gate, as shown in Figure 3-40.

Full Adder

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. Besides the three inputs, it has two outputs. Two of the input variables, denoted by X and Y, represent the two significant bits to be added. The third input, Z, rep-resents the carry from the previous lower significant position. Two outputs are neces-sary because the arithmetic sum of three bits ranges in value from 0 to 3, and binary 2 and 3 need two digits for their representation. Again, the two outputs are designat-ed by the symbols S for “sum” and C for “carry”; the binary variable S gives the value of the bit of the sum, and the binary variable C gives the output carry. The truth table of the full adder is listed in Table 3-12. The values for the outputs are determined from the arithmetic sum of the three input bits. When all the input bits are 0, the out-puts are 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output is a carry of 1 if two or three inputs are equal to 1. The maps for the two outputs of the full adder are shown in Figure 3-41. The simplified sum-of-product functions for the two outputs are

S = X YZ + XYZ + XY Z + XYZ

C = XY + XZ + YZ

The two-level implementation requires seven AND gates and two OR gates. However, the map for output S is recognized as an odd function, as discussed in

XY

S

C

FIGURE 3-40Logic Diagram of Half Adder

TABLE 3-12Truth Table of Full Adder

Inputs Outputs

X Y Z C S

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

M03_MANO0637_05_SE_C03.indd 158 23/01/15 1:51 PM

Exe1: 1-bit Half Adder

Practic

e

P2 VHDL

architecture arch1 of HalfAdder is

begin

S <= X XOR Y;

C <= X AND Y;

end arch1;

158 CHAPTER 3 / COMBINATIONAL LOGIC DESIGN

The half adder can be implemented with one exclusive-OR gate and one AND gate, as shown in Figure 3-40.

Full Adder

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. Besides the three inputs, it has two outputs. Two of the input variables, denoted by X and Y, represent the two significant bits to be added. The third input, Z, rep-resents the carry from the previous lower significant position. Two outputs are neces-sary because the arithmetic sum of three bits ranges in value from 0 to 3, and binary 2 and 3 need two digits for their representation. Again, the two outputs are designat-ed by the symbols S for “sum” and C for “carry”; the binary variable S gives the value of the bit of the sum, and the binary variable C gives the output carry. The truth table of the full adder is listed in Table 3-12. The values for the outputs are determined from the arithmetic sum of the three input bits. When all the input bits are 0, the out-puts are 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output is a carry of 1 if two or three inputs are equal to 1. The maps for the two outputs of the full adder are shown in Figure 3-41. The simplified sum-of-product functions for the two outputs are

S = X YZ + XYZ + XY Z + XYZ

C = XY + XZ + YZ

The two-level implementation requires seven AND gates and two OR gates. However, the map for output S is recognized as an odd function, as discussed in

XY

S

C

FIGURE 3-40Logic Diagram of Half Adder

TABLE 3-12Truth Table of Full Adder

Inputs Outputs

X Y Z C S

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

M03_MANO0637_05_SE_C03.indd 158 23/01/15 1:51 PM