05 - pcs924 stub differential relay

1 Introduction

PCS-924 Stub Differential Relay 1-a Date: 2011-08-02

1 Introduction

Table of Contents

1.1 Application ....................................................................................................... 1-1

1.2 Function ........................................................................................................... 1-1

1.3 Features ........................................................................................................... 1-3

List of Figures

Figure 1.1-1 Functional diagram of PCS-924 ............................................................................ 1-1

1 Introduction

PCS-924 Stub Differential Relay 1-b Date: 2011-08-02

1 Introduction

PCS-924 Stub Differential Relay 1-1 Date: 2011-08-02

1.1 Application

PCS-924 is a fully numerical stub differential relay which is mainly designed for protecting T zone

of one and a half breakers arrangement. It is developed based on UAPC (Unified Advanced

Platform for Protection and Control) platform.

The protection function of PCS-924 comprises of current differential protection, phase overcurrent

protection and feeder line end fault protection.

Busbar No.1

Line

52

52

52

Line

Busbar No.2

*

*

*

ICB2

ICB1

ILine

50P87S 50FLE

PCS-924

Figure 1.1-1 Functional diagram of PCS-924

1.2 Function

1. Protection Functions

Current differential protection (87S)

Phase overcurrent protection (50P)

Feeder line end fault protection (50FLE)

2. Logic

User programmable logic

3. Additional function

CT circuit supervision (CTS)

Self diagnostic

1 Introduction


DC power supply supervision

Current drift auto regulation

Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision

events and 1024 device logs.

Disturbance recorder including 64 disturbance records with waveforms (The file format of

disturbance recorder is compatible with international COMTRADE file.)

Clock synchronization

PPS (RS-485)

IRIG-B (RS-485)

PPM (DIN)

SNTP (PTP)

IEEE1588

SNTP (BC)

PPS (DIN)

4. Monitoring

Number of circuit breaker operation (single-phase tripping, three-phase tripping and

reclosing)

Frequency

5. Communication

2 RS-485 communication rear ports conform to IEC 60870-5-103 protocol or DNP3.0 protocol

1 RS-485 communication rear ports for clock synchronization

Up to 4 Ethernet ports (depend on the chosen type of plug-in MON module), IEC 61850, or

IEC 60870-5-103 over TCP/IP

Up to 2 Ethernet ports via optic fiber (ST interface or SC interface, depend on the chosen type

of plug-in MON module)

GOOSE communication function (optional plug-in module)

6. User Interface

Friendly HMI interface with LCD and 9-button keypad on the front panel.

1 front multiplex RJ45 port for testing and setting

1 RS-232 or RS-485 rear ports for printer

Language switchover English + selected language

1 Introduction


Auxiliary software - PCSPC

1.3 Features

The intelligent device integrated with protection, control and monitor provides powerful

protection function, flexible protection configuration, user programmable logic and

configurable binary input and binary output, which can meet with various application

requirements.

High-performance hardware platform and modularized design, MCU (management control

unit) + DSP (digital signal processor). MCU manages general fault detector element and DSP

manages protection and metering. Their data acquisition system is completely independent in

electronic circuit. DC power supply of output relay is controlled by the operation of fault

detector element operates, this prevents maloperation due to error from ADC or damage of

any apparatus.

Multiple setting groups with password protection

Powerful PC tool software can fulfill protection function configuration, modify setting and

waveform analysis.

1 Introduction


2 Technical Data


2 Technical Data

Table of Contents

2.1 Electrical Specifications ................................................................................. 2-1

2.1.1 AC Current Input .................................................................................................................. 2-1

2.1.2 AC Voltage Input .................................................................................................................. 2-1

2.1.3 Power Supply ....................................................................................................................... 2-1

2.1.4 Binary Input .......................................................................................................................... 2-1

2.1.5 Binary Output ....................................................................................................................... 2-2

2.2 Mechanical Specifications.............................................................................. 2-2

2.3 Ambient Temperature and Humidity Range .................................................. 2-2

2.4 Communication Port ....................................................................................... 2-3

2.4.1 EIA-485 Port ........................................................................................................................ 2-3

2.4.2 Ethernet Port ........................................................................................................................ 2-3

2.4.3 Optical Fibre Port ................................................................................................................. 2-3

2.4.4 Print Port .............................................................................................................................. 2-4

2.4.5 Clock Synchronization Port ................................................................................................. 2-4

2.5 Type Tests ........................................................................................................ 2-4

2.5.1 Environmental Tests............................................................................................................. 2-4

2.5.2 Mechanical Tests ................................................................................................................. 2-4

2.5.3 Electrical Tests ..................................................................................................................... 2-4

2.5.4 Electromagnetic Compatibility ............................................................................................. 2-4

2.6 Certifications ................................................................................................... 2-5

2.7 Protective Functions ....................................................................................... 2-6

2.7.1 Current Differential Protection ............................................................................................. 2-6

2.7.2 Phase Overcurrent Protection ............................................................................................. 2-6

2.7.3 Feeder Line End Fault Protection ........................................................................................ 2-6

2 Technical Data


2 Technical Data


2.1 Electrical Specifications

2.1.1 AC Current Input

Standard IEC 60255-27:2005

Phase rotation ABC

Nominal frequency (fn) 505Hz, 605Hz

Rated Current (In) 1A 5A

Linear to 0.05In~40In

Thermal withstand

-continuously

-for 10s

-for 1s

-for half a cycle

4In

30In

100In

250In

Burden < 0.15VA/phase @In < 0.25VA/phase @In

Accuracy 0.5%In

2.1.2 AC Voltage Input

Standard IEC 60255-6, IEC60288

Phase rotation ABC

Nominal frequency (fn) 505Hz, 605Hz

Rated Voltage (Un) 100V~130V

Linear to 1V~170V

Thermal withstand

- continuously

-10s

-1s

200V

260V

300V

Burden at rated < 0.25VA/phase @Un

Accuracy 0.5%Un

2.1.3 Power Supply

Standard IEC 60255-11:2008

Rated Voltage 110Vdc/125Vdc, 220Vdc/250Vdc

Operating Range 80%~120% of rated voltage

Permissible AC ripple voltage 15% of the nominal auxiliary voltage

Burden

Quiescent condition

Operating condition

2 Technical Data


Maximum permissible voltage 120% of rated voltage

Withstand voltage

-continously 2000Vac, 2800Vdc

Response time for logic input

2 Technical Data


Permissible humidity 5%-95%, without condensation

Pollution degree

Altitude

2 Technical Data


2.4.3.3 For Synchronization Port

Characteristic Glass optical fiber

Connector type ST

Fibre type Multi mode

Wave length 820nm

Minimum receiving power Min. -25.0dBm

Margin Min +3.0dB

2.4.4 Print Port

Type RS-232

Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

Printer type EPSON 300K printer

Safety level Isolation to ELV level

2.4.5 Clock Synchronization Port

Type RS-485

Transmission distance 100M@500VDC

2.5.4 Electromagnetic Compatibility

1MHz burst disturbance test IEC 60255-22-1:2007

2 Technical Data


Common mode: class III 2.5kV

Differential mode: class III 1.0kV

Electrostatic discharge test

IEC60255-22-2:2008 class IV

For contact discharge: 8kV

For air discharge: 15kV

Radio frequency interference tests

IEC 60255-22-3:2007 class III

Frequency sweep

Radiated amplitude-modulated

10V/m (rms), f=80~1000MHz

Spot frequency

Radiated amplitude-modulated

10V/m (rms), f=80MHz/160MHz/450MHz/900MHz

Radiated pulse-modulated

10V/m (rms), f=900MHz

Fast transient disturbance tests

IEC 60255-22-4:2008

Power supply, I/O, Earth: class IV, 4kV, 2.5kHz, 5/50ns

Communication terminals: class IV, 2kV, 5kHz, 5/50ns

Surge immunity test

IEC 60255-22-5:2008

Power supply, AC input, I/O port: class IV, 1.2/50us

Common mode: 4kV

Differential mode: 2kV

Conducted RF Electromagnetic

Disturbance

IEC 60255-22-6:2001

Power supply, AC, I/O, Comm. Terminal: Class III, 10Vrms, 150

kHz~80MHz

Power Frequency Magnetic Field

Immunity

IEC 61000-4-8:2001

class V, 100A/m for 1min, 1000A/m for 3s

Pulse Magnetic Field Immunity IEC 61000-4-9:2001

class V, 6.4/16s, 1000A/m for 3s

Damped oscillatory magnetic field

immunity

IEC 61000-4-10:2001

class V, 100kHz & 1MHz100A/m

Auxiliary power supply performance

- Voltage dips

-Voltage short interruptions

IEC60255-11: 2008

Up to 500ms for dips to 40% of rated voltage without reset

100ms for interruption without rebooting

2.6 Certifications

ISO9001:2008

ISO14001:2004

OHSAS18001:2007

ISO10012:2003

2 Technical Data


CMMI L5

EMC: 2004/108/EC, EN50263:1999

Products safety(PS): 2006/95/EC, EN61010-1:2001

2.7 Protective Functions

Note!

The meanings of symbols mentioned in the following sections are given here.

In -- rated secondary current of CT

Un -- rated secondary phase-to-ground voltage of VT

Unn -- rated secondary phase-to-ground voltage of VT

2.7.1 Current Differential Protection

Setting range 0.100In~1.000In

Accuracy 2.5% of setting or 0.02In whichever is greater

2.7.2 Phase Overcurrent Protection


Accuracy 2.5% of setting or 0.01Un, whichever is greater

Time delay 0.01~10.00s

Accuracy 1% of Setting+30ms (at 1.2 times voltage setting)

2.7.3 Feeder Line End Fault Protection


Accuracy 2.5% of setting or 0.01Un, whichever is greater

Time delay 0.01~10.00s

Accuracy 1% of Setting+30ms (at 1.2 times voltage setting)

3 Operation Theory


3 Operation Theory

Table of Contents

3.1 Fault Detector (FD) .......................................................................................... 3-1

3.1.1 Application............................................................................................................................ 3-1

3.1.2 Fault Detector in Fault Detector DSP .................................................................................. 3-1

3.1.3 Protection Fault Detector in Protection Calculation DSP .................................................... 3-2

3.1.4 Function Block Diagram ...................................................................................................... 3-3

3.1.5 I/O Signal ............................................................................................................................. 3-3

3.2 Current Differential Protection ....................................................................... 3-4

3.2.1 Function Description ............................................................................................................ 3-4

3.2.2 Protection Principle .............................................................................................................. 3-4

3.2.3 Function Block Diagram ...................................................................................................... 3-6

3.2.4 I/O Signal ............................................................................................................................. 3-6

3.2.5 Logic .................................................................................................................................... 3-7

3.2.6 Settings ................................................................................................................................ 3-9

3.3 Feeder Line End Fault Protection .................................................................. 3-9

3.3.1 Application............................................................................................................................ 3-9

3.3.2 Protection Principle .............................................................................................................. 3-9

3.3.3 Function Block Diagram .................................................................................................... 3-10

3.3.4 I/O Signal ........................................................................................................................... 3-10

3.3.5 Logic .................................................................................................................................. 3-10

3.3.6 Settings ............................................................................................................................... 3-11

3.4 Phase overcurrent protection ....................................................................... 3-11

3.4.1 Protection Principle ............................................................................................................. 3-11

3.4.2 Function Block Diagram .................................................................................................... 3-12

3.4.3 I/O Signal ........................................................................................................................... 3-12

3.4.4 Logic .................................................................................................................................. 3-12

3 Operation Theory


3.4.5 Settings .............................................................................................................................. 3-13

3.5 Trip Logic ....................................................................................................... 3-13

3.5.1 Application.......................................................................................................................... 3-13

3.5.2 Function Description .......................................................................................................... 3-13

3.5.3 Logic .................................................................................................................................. 3-14

3.5.4 I/O Signal ........................................................................................................................... 3-14

3.5.5 Settings .............................................................................................................................. 3-15

List of Figures

Figure 3.1-1 Flow chart of protection program ........................................................................ 3-3

Figure 3.2-1 3-terminal application ............................................................................................ 3-4

Figure 3.2-2 Logic of 3-terminal current differential protection ............................................. 3-7

Figure 3.2-3 Logic of 2-terminal current differential protection ............................................. 3-8

Figure 3.3-1 Logic of feeder line end fault protection ........................................................... 3-11

Figure 3.4-1 Logic of phase overcurrent protection .............................................................. 3-13

Figure 3.5-1 Simplified tripping logic ...................................................................................... 3-14

List of Tables

Table 3.1-1 Input signal ............................................................................................................... 3-3

Table 3.1-2 Output signal ............................................................................................................ 3-3

Table 3.2-1 Input signals ............................................................................................................. 3-6

Table 3.2-2 Output signals .......................................................................................................... 3-6

Table 3.2-3 Current differential protection settings ................................................................. 3-9

Table 3.3-1 Input signals ........................................................................................................... 3-10

Table 3.3-2 Output signals ........................................................................................................ 3-10

Table 3.3-3 Feeder line end fault protection settings ............................................................ 3-11

Table 3.4-1 Input signals ........................................................................................................... 3-12

Table 3.4-2 Output signals ........................................................................................................ 3-12

Table 3.4-3 Current differential protection settings ............................................................... 3-13

Table 3.5-1 Input signal ............................................................................................................. 3-14

3 Operation Theory

PCS-924 Stub Differential Relay 3-c Date: 2011-08-02

Table 3.5-2 Output signal .......................................................................................................... 3-14

Table 3.5-3 Setting description ................................................................................................ 3-15

3 Operation Theory

PCS-924 Stub Differential Relay 3-d Date: 2011-08-02

3 Operation Theory


3.1 Fault Detector (FD)

3.1.1 Application

The device has plug-in DSP modules with fault detector DSP and protection DSP for fault detector

and protection calculation respectively. Protection DSP with protection fault detector element is

responsible for calculation of protection elements, and fault detector DSP is responsible to

determine fault appearance on the protected power system. Fault detector in fault detector DSP

picks up to provide positive supply to output relays. The output relays can only operate when both

the fault detector in fault detector DSP and a protection element operate simultaneously.

Otherwise, the output relays would not operate. An alarm message will be issued with blocking

outputs if a protection element operates while the fault detector does not operate.

3.1.2 Fault Detector in Fault Detector DSP

Main part of FD is differential current fault detector element and two breakers sum current fault

detector element. They are continuously calculating the analog input signals.

The FD pickup condition in this relay includes:

1. Pickup condition 1: differential current is greater than the setting value

2. Pickup condition 2: two breakers sum current is greater than the setting value

If any of the above conditions is complied, the FD will operate to activate the output circuit

providing with DC power supply to the output relays.

3.1.2.1 Fault Detector Based on Differential Current (pickup condition 1)

The criterion is:

I3Dmax > [87S.I_Biased] Equation 3.1-1

Where:

= A, B or C

I3Dmax = Max( Line_CB2_CB1_ III ), the maximum value of phase differential current of phase

A, phase B and phase C, please refer to Figure 3.2-1 about CB1I , CB2I and LineI .

[87S.I_Biased]: current setting of current differential protection.

If operating condition is met, differential current element will pickup and trigger FD to provide DC

power supply for output relays, the FD operation signal will maintain 7s after differential current

element drops off.

3.1.2.2 Fault Detector Based on Two Breakers Sum Current (pickup condition 2)

The criterion:

3 Operation Theory


Max( CB2_CB1_ II ) > [50P.I_Set] Equation 3.1-2

Where:

= A, B or C

CB1I , CB2I : secondary current of two circuit breakers.

[50P.I_Set]: current setting of phase overcurrent protection

If above condition is met and phase overcurrent protection is enabled, two breakers sum current

element will pickup and trigger FD to provide DC power supply for output relays, the FD operation

signal will maintain 7s after two breakers sum current element drops off.

3.1.3 Protection Fault Detector in Protection Calculation DSP

The protection device is running either of the two programs: one is Regular program for normal

state, and the other is Fault calculation program after protection fault detector picks up.

Under the normal state, the protection device will perform the following tasks:

1. Calculate analog quantity

2. Read binary input

3. Hardware self-check

4. Disconnector position supervision

5. Analog quantity input supervision

Once the protection fault detector element in protection calculation DSP picks up, the protection

device will switch to fault calculation program, for example the calculation of phase overcurrent

protection, and to determine logic. If the fault is within the protected zone, the protection device will

send tripping command.

The protection program flow chart is shown as Figure 3.1-1.

3 Operation Theory


Pickup?

Regular program Fault calculation program

No Yes

Main program

Sampling program

Figure 3.1-1 Flow chart of protection program

The protection FD pickup conditions are the same as the FD in fault detector DSP as shown below.

The operation criteria for the conditions are also the same as that in fault detector DSP. Please

refer to section 3.1.2 for details.

1. Pickup condition 1: differential current is greater than the setting value

2. Pickup condition 2: two breakers sum current is greater than the setting value

When any pickup condition mentioned above is met, the protection device will go to fault

calculation state.

3.1.4 Function Block Diagram

FD

PkpI3P1

Diff.Pkp

OC.Pkp

I3P2

I3P3

3.1.5 I/O Signal

Table 3.1-1 Input signal

No. Input Signal Description Configurable

1 I3P1 Three-phase current input of CT1



Table 3.1-2 Output signal

3 Operation Theory


No. Output Signal Description Configurable

1 FD.Pkp The device picks up

2 FD.Diff.Pkp Differential current fault detector element operates.

3 FD.OC.Pkp Two breakers sum current fault detector element operates.

3.2 Current Differential Protection

3.2.1 Function Description

Generally, differential current is composed of 3-terminal current (current of two breakers and

current of the feeder line, shown as Figure 3.2-1), only when normally closed auxiliary contact of

feeder line disconnector is energized (feeder line disconnector is open), differential current is

composed of 2-terminal current (currents of two breakers).

3.2.2 Protection Principle

3.2.2.1 3-terminal Current Differential Protection

Three groups of current are inputted to the device (3 current circuits per group), as shown in

Figure 3.2-1. CB1_I and CB2_I are secondary phase currents of two circuit breakers, Line_I

are secondary phase currents of the line ( = A, B or C).

Line

52

52

52

Line

*

*

*

PC

S-9

24

02

01

~0

20

60

20

7~

02

12

02

13

~0

21

8

CT

gro

up

1C

T g

rou

p 2

CT

gro

up

3

CT1

CT2

CT3

CB1

CB2

CB3

ICB2

ICB1

ILine

Figure 3.2-1 3-terminal application

When current differential protection is enabled, 3-terminal current differential protection is valid if

normally closed auxiliary contact of feeder line disconnector is open (feeder line disconnector is

closed).

3 Operation Theory


The criterion:

I3D > [87S.I_Biased] Equation 3.2-1

I3D > [87S.Slope]I3R Equation 3.2-2

Where:

I3D: 3-terminal differential current (I3D = Line_CB2_CB1_ III )

I3R: 3-terminal restraint current (I3R = Line_CB2_CB1_ III )

[87S.I_Biased]: current setting of current differential protection

[87S.Slope]: percentage restraint coefficient of current differential protection

When I3D>1.3In, tripping output will operate once current differential protection operates (In:

secondary rated current of CT).

When I3D [87S.I_Biased] Equation 3.2-3

I2D > [87S.Slope]I2R Equation 3.2-4

Where:

I2D: 2-terminal differential current (I2D = CB2_CB1_ II ).

I2R: 2-terminal restraint current (I2R = CB2_CB1_ II ).


[87S.Slope]: percentage restraint coefficient of current differential protection.

When I2D>1.3In, tripping output will operate once current differential protection operates (In:

secondary rated current of CT).

When I2D

3 Operation Theory


protection operates.

Both local circuit breakers are tripped (CB1 and CB2) but transfer tripping is not initiated after

2-terminal current differential protection operates.

3.2.2.3 Differential Current Alarm

If any of the phase differential current is greater than the setting [87S.I_Alm] for 5s, this device will

issue the alarm signal [87S.Alm_Diff]. If the alarmed phase differential current is reverted to

normal, the alarm signal [87S.Alm_Diff] will be restored automatically after 5s.


87S

I3P1 87S.Op

87S.En1

87S.En2

87S.Blk

I3P2

I3P3

89b_DS

87S.Op_2Terminals

87S.St

87S.Op_3Terminals

87S.Valid_89b_DS

87S.Alm_89b_DS

87S.Alm_Diff

3.2.4 I/O Signal

Table 3.2-1 Input signals





4 89b_DS Normally closed auxiliary contact of feeder line disconnector

5 87S.En1 Current differential protection enabling input 1, it can be binary

inputs or logic links. Yes

6 87S.En2 Current differential protection enabling input 2, it can be binary

inputs or logic link. Yes

7 87S.Blk

Current differential protection blocking input, such as function

blocking binary input.

When the input is 1, current differential protection is reset and

time delay is cleared.

Yes

Table 3.2-2 Output signals


1 87S.Op Current differential protection operates.

2 87S.St Current differential protection picks up.

3 87S.Op_2Terminals Current differential protection with two terminals operates. Yes

3 Operation Theory



4 87S.Op_3Terminals Current differential protection with three terminals operates. Yes

5 87S.Valid_89b_DS Disconnector position is valid.

6 87S.Alm_89b_DS Disconnector position is abnormal.

7 87S.Alm_Diff Differential current is abnormal.

3.2.5 Logic

Logic diagram of 3-terminal current differential protection and 2-terminal current differential

protection are shown in following two figures.

&

&

&

&

&

&

&

&

&

20ms 0

>=1

20ms 0

>=1

20ms 0

>=1

&

87S.Op

>=1

BI BI_89b_DS

SIG [87S.En1]

SIG [87S.En2]

SIG [87S.Blk]

&

EN [87S.En]

SET I3DB>[87S.I_Biased]

SET I3DC>[87S.I_Biased]

SET I3DA>[87S.Slope]I3RA

SET I3DB>[87S.Slope]I3RB

SET I3DC>[87S.Slope]I3RC

SIG I3DA>1.3In

SIG I3DC>1.3In

SIG I3DB>1.3In

SET I3DA>[87S.I_Biased]

Figure 3.2-2 Logic of 3-terminal current differential protection

Where:

I3DA: differential current of phase A for 3-terminal current differential protection

I3DB: differential current of phase B for 3-terminal current differential protection

I3DC: differential current of phase C for 3-terminal current differential protection

I3RA: restraint current of phase A for 3-terminal current differential protection

3 Operation Theory


I3RB: restraint current of phase B for 3-terminal current differential protection

I3RC: restraint current of phase C for 3-terminal current differential protection

&

&

&

&

&

&

&

&

&

20ms 0

>=1

20ms 0

>=1

20ms 0

>=1

&

87S.Op

>=1

BI BI_89b_DS

SIG [87S.En1]

SIG [87S.En2]

SIG [87S.Blk]

&

EN [87S.En]

SET I2DB>[87S.I_Biased]

SET I2DC>[87S.I_Biased]

SET I2DA>[87S.Slope]I2RA

SET I2DB>[87S.Slope]I2RB

SET I2DC>[87S.Slope]I2RC

SIG I2DA>1.3In

SIG I2DC>1.3In

SIG I2DB>1.3In

SET I2DA>[87S.I_Biased]

Figure 3.2-3 Logic of 2-terminal current differential protection

Where:

I2DA: differential current of phase A for 2-terminal current differential protection

I2DB: differential current of phase B for 2-terminal current differential protection

I2DC: differential current of phase C for 2-terminal current differential protection

I2RA: restraint current of phase A for 2-terminal current differential protection

I2RB: restraint current of phase B for 2-terminal current differential protection

I2RC: restraint current of phase C for 2-terminal current differential protection

3 Operation Theory


3.2.6 Settings

Table 3.2-3 Current differential protection settings

No. Name Range Step Unit Remark

1 87S.I_Biased (0.050~30.000)In 0.001 A Current setting of current differential

protection

2 87S.I_Alm (0.050~30.000)In 0.001 A Current setting of current differential CT

alarm element

3 87S.Slope 0.3~1.0 0.001 Slope of current differential protection

4 87S.En 0 or 1 1

Enabling or disabling current differential

protection;

0: disable; 1: enable

5 87S.En_CTS_Blk 0 or 1 1

Enabling or disabling CTS blocking

current protection function;

0: disable; 1: enable

3.3 Feeder Line End Fault Protection

3.3.1 Application

Two stages of feeder line end fault protection is available for the device. If feeder line end fault

protection is enabled, feeder line end fault protection is in service when normally closed auxiliary

contact of feeder line disconnector is closed. (feeder line disconnector is open)


The criterion:

ILine_max > [50FLE1.I_Set] or [50FLE2.I_Set] Equation 3.3-1

I3Dmax > [87S.I_Biased] Equation 3.3-2

Where:

ILine_max=Max(ILine_A, ILine_B, ILine_C), ILine_A, ILine_B and ILine_C are secondary phase current of the line.

[50FLE1.I_Set], [50FLE2.I_Set]: current setting of stage 1 and stage 2 of feeder line end fault

protection

I3Dmax=Max( Line_CB2_CB1_ III ), the maximum value of phase differential current of phase A,

phase B and phase C, please refer to Figure 3.2-1 about CB1I , CB2I and LineI .


In order to prevent the device from undesired trip due to error in normally closed auxiliary contact

of feeder line disconnector, feeder line end fault protection is controlled by differential current

element.

3 Operation Theory


Provided that differential current element of feeder line end fault protection operates, if

ILine_max >[50FLE1.I_Set], stage 1 of feeder line end fault protection will operate to initiate transfer

trip after the time delay of [50FLE1.t_Op], if ILine_max >[50FLE2.I_Set], stage 2 of feeder line end

fault protection will operate to initiate transfer trip after the time delay of [50FLE2.t_Op].


50FLEx

50FLEx.StI3P3

50FLEx.Op

50FLEx.En1

50FLEx.En2

50FLEx.Blk

BI_89b_DS

3.3.4 I/O Signal




2 BI_89b_DS normally closed auxiliary contact of feeder line disconnector

3 50FLEx.En1 Stage x of feeder line end fault protection enabling input 1, it can

be binary inputs or logic links. Yes

4 50FLEx.En2 Stage x of feeder line end fault protection enabling input 2, it can

be binary inputs or logic link. Yes

5 50FLEx.Blk

Stage x of feeder line end fault protection blocking input, such as

function blocking binary input.

When the input is 1, feeder line end fault protection is reset and


Yes



1 50FLEx.St Operation signal of stage x of feeder line end fault protection

2 50FLEx.Op Pickup signal of stage x of feeder line end fault protection

3.3.5 Logic

Logic diagram of feeder line end fault protection is shown in the following figure.

3 Operation Theory


SIG [50FLEx.En1]

SIG [50FLEx.En2]

SIG [50FLEx.Blk]

&

EN [50FLEx.En]

SET ILine_max>[50FLEx.I_Set] &

50FLEx.St

50FLEx.t_Op 0ms 50FLEx.Op

BI BI_89b_DS

SET I3Dmax>[87S.I_Biased]

Figure 3.3-1 Logic of feeder line end fault protection

Where:

x=1 or 2

3.3.6 Settings

Table 3.3-3 Feeder line end fault protection settings


1 50FLE1.I_Set (0.050~30.000)In 0.001 A Current setting of stage 1 of feeder

line end fault protection

2 50FLE1.t_Op 0.000~20.000 0.001 s Time delay of stage 1 of feeder line

end fault protection

3 50FLE1.En 0 or 1

Enabling or disabling stage 1 of

feeder line end fault protection

0: disable

1: enable

4 50FLE2.I_Set (0.050~30.000)In 0.001 A Current setting of stage 2 of feeder

line end fault protection

5 50FLE2.t_Op 0.000~20.000 0.001 s Time delay of stage 2 of feeder line

end fault protection

6 50FLE2.En 0 or 1

Enabling or disabling stage 2 of

feeder line end fault protection

0: disable

1: enable

3.4 Phase overcurrent protection


Phase overcurrent protection is based on the sum current of two circuit breakers, the criterion is:

Max( CB2_CB1_ II )>[50P.I_Set] Equation 3.4-1

CB1I , CB2I : secondary current of two circuit breakers.

3 Operation Theory


= A, B or C

[50P.I_Set]: current setting of phase overcurrent protection.

Both local circuit breakers (CB1 and CB2) will be tripped if phase overcurrent protection operates.


50P

50P.StI3P1

50P.Op50P.En1

50P.En2

50P.Blk

I3P2

3.4.3 I/O Signal





3 50P.En1 Phase overcurrent protection enabling input 1, it can be binary

inputs or logic links. Yes

4 50P.En2 Phase overcurrent protection enabling input 2, it can be binary

inputs or logic link. Yes

5 50P.Blk

Phase overcurrent protection blocking input, such as function

blocking binary input.

When the input is 1, phase overcurrent protection is reset and


Yes



1 50P.Op Operation signal of phase overcurrent protection

2 50P.St Pickup signal of phase overcurrent protection

3.4.4 Logic

Logic diagram of phase overcurrent protection is shown in following figure.

3 Operation Theory


SIG [50P.En1]

SIG [50P.En2]

SIG [50P.Blk]

&

EN [50P.En]

SET Max( )>[50P.I_Set] CB2_CB1_ II

50P.t_Op 0ms

&

50P.Op

50P.St

Figure 3.4-1 Logic of phase overcurrent protection

3.4.5 Settings

Table 3.4-3 Current differential protection settings


1 50P.I_Set (0.050~30.000)In 0.001 A current setting of phase overcurrent

element

2 50P.t_Op 0.000~20.000 0.001 s time delay of phase overcurrent

element

3 50P.En 0 or 1 enable phase overcurrent element

3.5 Trip Logic

3.5.1 Application

For any enabled protection tripping elements, their operation signal will convert to appropriate

tripping signals through trip logics and then trigger output contacts by configuration.

3.5.2 Function Description

This module gathers signals from protection tripping elements and then converts the operation

signal from protection tripping elements to appropriate tripping signals.

3 Operation Theory


3.5.3 Logic

SIG Max(I3P3)>0.06I2n

SIG 87S.Op_3Terminals

TT

&

t_Dwell_TT 0

SIG FD.Pkp

&

>=1

SIG 50FLE1.Op

SIG 50FLE2.Op

>=1

0 t_Dwell_TT&

SIG Max(I3P1+I3P2)>0.06I2n


Trp

&

t_Dwell_Trp 0

SIG FD.Pkp

&

>=1


SIG 50P.Op

>=1

0 t_Dwell_Trp&

Figure 3.5-1 Simplified tripping logic

1. [t_Dwell_Trp] is the shortest period of tripping contact operation. The tripping contact shall be

reset under conditions of no current and or protection tripping element reset.

3.5.4 I/O Signal

Table 3.5-1 Input signal

Name Description

I3P1 Three-phase current input of CT1



87S.Op_3Terminals 3-terminal current differential protection operates.

87S.Op_2Terminals 2-terminal current differential protection operates.

50FLE1.Op Operation signal of stage 1 of feeder line end fault protection

50FLE2.Op Operation signal of stage 2 of feeder line end fault protection

50P.Op Operation signal of phase overcurrent protection

Table 3.5-2 Output signal

Name Description

Trp Tripping local two circuit breakers

TT Initiating transfer tripping

3 Operation Theory


3.5.5 Settings

Table 3.5-3 Setting description


1 t_Dwell_Trp 0.000~1000.000 0.001 s the dwell time of tripping command, empirical

value is 0.04

2 t_Dwell_TT 0.000~1000.000 0.001 s the dwell time of transfer tripping command

3 Operation Theory


4 Supervision


4 Supervision

Table of Contents

4.1 General Description ........................................................................................ 4-1

4.2 Supervision Alarms ......................................................................................... 4-1

4.3 Relay Self-supervision .................................................................................... 4-4

4.3.1 Relay Hardware Monitoring ................................................................................................. 4-4

4.3.2 Fault Detector Monitoring .................................................................................................... 4-4

4.3.3 Check Tripping Output Circuit.............................................................................................. 4-4

4.3.4 Check Setting ...................................................................................................................... 4-4

4.4 AC Input Monitoring ........................................................................................ 4-4

4.4.1 Current Drift Monitoring and Auto-adjustment ..................................................................... 4-4

4.4.2 Sampling Monitoring ............................................................................................................ 4-4

4.5 Secondary Circuit Monitoring ........................................................................ 4-5

4.5.1 Opto-coupler Power Supervision ......................................................................................... 4-5

Table of Tables

Table 4.2-1 Alarm description and handling suggestion ........................................................ 4-1

4 Supervision


4 Supervision


4.1 General Description

Protection system is in quiescent state under normal conditions, and it is required to respond

promptly for faults occurred on power system. When equipment is in energizing process before the

LED HEALTHY is on, the equipment need to be checked to ensure no abnormality. Therefore,

the automatic supervision function, which checks the health of the protection system when startup

and during normal operation, plays an important role.

The numerical relay based on the microprocessor operations is suitable for implementing this

automatic supervision function of the protection system.

In case a defect is detected during initialization when DC power supply is provided to the

equipment, the equipment will be blocked with indication and alarm of relay out of service. It is

suggested a trial recovery of the equipment by re-energization. Please contact supplier if the

equipment is still failure.

When a failure is detected by the automatic supervision, it is followed by a LCD message, LED

indication and alarm contact outputs. The failure alarm is also recorded in event recording report

and can be printed If required.

4.2 Supervision Alarms

Hardware circuit and operation status of the equipment are self-supervised continuously. If any

abnormal condition is detected, information or report will be displayed and a corresponding alarm

will be issued.

A minor abnormality may block a certain number of protections functions while the other functions

can still work. However, if severe hardware failure or abnormality are detected, all protection

functions will be blocked and the LED HEALTHY will be extinguished and blocking output

contacts BO_FAIL will be given. The protective device then can not work normally and

maintenance is required to eliminate the failure. All the alarm signals and the corresponding

handling suggestions are listed below.

Note!

If the protective device is blocked or alarm signal is sent during operation, please do find

out its reason with the help of self-diagnostic record. If the reason can not be found at site,

please notify the factory NR. Please Do not simply press button TARGET RESET on the

protection panel or re-energize on the protective device.

Table 4.2-1 Alarm description and handling suggestion

No. Item Alarm description Handing suggestion

1 Fail_Device The device fails.

The signal is issued with other specific alarm

signals, and please refer to the handeling

suggestion other specific alarm signals.

2 Alm_Device The device is abnormal. The signal is issued with other specific alarm

4 Supervision


signals, and please refer to the handeling

suggestion other specific alarm signals.

3 Alm_CommTest The device is in the

communication test mode.

No special treatment is needed, and disable

the communication test function after the

completion of the test.

4 Alm_Setting_OvRange Set value of any setting is out

of scope.

Please reset setting values according to the

range described in the instruction manual,

then re-power or reboot the equipment and

the alarm message will disappear and the

equipment will restore to normal operation

state.

5 Alm_BoardConfig

Mismatch between the

configuration of plug-in

modules and the designing

drawing of an applied-specific

project.

1. Go to the menu InformationBorad

Info, check the abnormality information.

2. For the abnormality board, if the board

is not used, then remove, and if the board is

used, then check whether the board is

installed properly and work normally.

3. After the abnormality is removed,

re-power or reboot the device and the device

will restore to normal operation state.

6 Bxx.Fail_TrpOut

Driving circuits of binary

output relays of BO plug-in

module in slot xx are

damaged.

Please re-insert the corresponding binary

output module and re-power the equipment

after the completion of insertion, and the

device will restore to normal operation state.

7 Fail_SettingSurv

Setting surveillance between

DSP module and MON

module is abnormal.

Please inform the manufacture or the agent

for repair.

8 Fail_Memory Error is found during

checking memory data.

Please inform the manufacture or the agent

for repair.

9 Fail_Settings Error is found during

checking settings.

1. Check CT ratio settings of each side of

transformer to be set in proper range, and if

need, please reset those settings and reboot

or re-power the device.

2. Check overexcitation settings to be set

reasonable, and if need, please reset those

settings and reboot or re-power the device.

3. After above two steps, abnormality may

disappear. Otherwise, a hardware failue

probably ocurrs and please inform the

manufacture or the agent.

10 Fail_DSP DSP chip is damaged.

Chips are damaged and please inform the

manufacture or the agent replacing the

module.

11 Bxx.Alm_OptoDC The power supply of BI 1. check whether the binary input module

4 Supervision


plug-in module in slot xx is

abnormal.

is connected to the power supply.

2. check whether the voltage of power

supply is in the required range.

3. After the voltage for binary input module

restores to normal range, the ALARM LED

will be extinguished and the corresponding

alarm message will disappear and the device

will restore to normal operation state.

12 Fail_Config Software configuation is

incorrect.

Please inform configuration engineers to

check and confirm visualization functions of

the device

13 Fail_Sample AC current samplings are

abnormal.

1. Please make the device out of service.

2. Then check if the analog input modules

and wiring connectors connected to those

modules are installed at the position.

3. Re-power the device and the device will

restore to normal operation state.

14 Alm_PersistFD Fault detector element

operates for longer than 10s.

Please check secondary values and

protection settings. If settings are not set

reasonable to make fault detectors pick up,

please reset settings, and then the alarm

message will disappear and the device will

restore to normal operation state.

15 CTS.Alm CT circuit of corresponding

circuit breaker fails.

Please check the corresponding CT

secondary circuit. After the abnormality is

eliminated, ALARM LED will go off

automatically and device returns to normal

operation state.

16 Fail_SV_QF The quality factor of sample

values is abnormal.

Thess alarms may be issued for electric

transformer applied projects. If alarms are

issued, please check working state of

merging units and the connection between

merging units and the protection device.

17 Alm_Maintenance The device is in maintenance

state.

After maintenance is finished, please

de-energized the binary input

[BI_Maintenance] and then the alarm will

disappear and the device restore to normal

operation state.

18 Alm_TimeSync Time synchronization

abnormality alarm.

1. check whether the selected clock

synchronization mode matches the clock

synchronization source;

2. check whether the wiring connection

between the equipment and the clock

4 Supervision


synchronization source is correct

3. check whether the setting for selecting

clock synchronization (i.e. [Opt_TimeSync])

is set correctly. If there is no clock

synchronization, please set the setting

[Opt_TimeSync] as No TimeSync.

4. After the abnormality is removed, the

ALARM LED will be extinguished and the

corresponding alarm message will disappear

and the device will restore to normal

operation state.

4.3 Relay Self-supervision

4.3.1 Relay Hardware Monitoring

All chips on DSP module are monitored to ensure whether they are damaged or having errors. If

any one of them is detected damaged or having error, the alarm signal [Fail_DSP] is issued with

device being blocked.

4.3.2 Fault Detector Monitoring

When any fault detector picks up for over 10s, an alarm will be issued [Alm_PersistFD] without

protective device blocked.

4.3.3 Check Tripping Output Circuit

Chips controlling the output relays in the output circuit are continually monitored. If any error or

damage is detected in these chips, alarm [Bxx.Fail_TrpOut] will be given and the device will be

blocked.

4.3.4 Check Setting

This relay has 10 setting groups, only one setting group could be activiated (is active) at a time.

The settings of active setting group are checked to ensure they are reasonable. If settings are

checked to be unreasonable or out of setting scopes, a corresponding alarm signal will be issued,

and protective device is also blocked.

4.4 AC Input Monitoring

4.4.1 Current Drift Monitoring and Auto-adjustment

Zero point of current may drift due to variation of temperature or other environment factors. The

equipment continually traces the drift and adjust it to normal value automatically.

4.4.2 Sampling Monitoring

AC current samplings of protection DSP and fault detector DSP are monitored and if the samples

of protection DSP and fault detector DSP are detected to be wrong or inconsistent between them,

4 Supervision


the alarm signal [Fail_Sample] will be issued and the device will be blocked.

4.5 Secondary Circuit Monitoring

4.5.1 Opto-coupler Power Supervision

Positive power supply of opto-coupler is continually monitored. If an error or damage has occurred,

an alarm [Bxx.Alm_OptoDC] will be issued.

4 Supervision


5 Measurement and Recording



Table of Contents

5.1 Measurement ................................................................................................... 5-1

5.2 Recording ........................................................................................................ 5-1

5.2.1 General Description ............................................................................................................. 5-1

5.2.2 Event Recording .................................................................................................................. 5-2

5.2.3 Disturbance Recording ........................................................................................................ 5-2

5.2.4 Present Recording ............................................................................................................... 5-3



5.1 Measurement

PCS-924 performs continuous measurement of the analogue input quantities. The relay samples

24 points per cycle and calculates the RMS value in each interval and updated the LCD display in

every 0.5s. The measurement data can be displayed on the LCD of the relay front panel or on the

local/remote PC via software tool. Navigate the menu to view the sampling value through LCD

screen.

1. RMS Values

Access path: Press key to enter main menu firstly. Select the item Measurements and press

key ENT to enter, and then select submenu Measurements1. Press key ENT to display

corresponding measurement values as below on the LCD.

Measured directly

Magnitude of phase current of CT1 (Ia1, Ib1, Ic1)



Calculated by DSP

Differential current (Id_a, Id_b, Id_c)

Phase Angle

Phase angle of (Ia1-Ib1), (Ib1-Ic1), (Ic1-Ia1)



Phase angle of (Ia1-Ia2), (Ib1-Ib2), (Ic1-Ic2)



5.2 Recording

5.2.1 General Description

PCS-924 provides the following recording functions:

1. Event recording

2. Disturbance recording

3. Present recording

All the recording information except waveform can be viewed on local LCD or by printing.

Waveform could only be printed or extracted with PCS-PC software tool and a waveform analysis

software.



5.2.2 Event Recording

5.2.2.1 General Description

The device can store the latest 1024 disturbance records, 1024 binary events, 1024 supervision

events and 1024 device logs. All the records are stored in non-volatile memory, and when the

available space is exhausted, the oldest record is automatically overwritten by the latest one.

5.2.2.2 Disturbance Records

When any protection element operates or drops off, such as fault detector, distance protection etc.,

they will be logged in event records.

5.2.2.3 Supervision Events

The device is under automatic supervision all the time. If there are any failure or abnormal

condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event

records.

5.2.2.4 Binary Events

When there is a binary input is energized or de-energized, i.e., its state has changed from 0 to 1

or from 1 to 0, it will be logged in event records.

5.2.2.5 Device Logs

If an operator implements some operations on the device, such as reboot protective device,

modify setting, etc., they will be logged in event records.

5.2.3 Disturbance Recording

5.2.3.1 Application

Disturbance records can be used to have a better understanding of the behavior of the power

network and related primary and secondary equipment during and after a disturbance. Analysis of

the recorded data provides valuable information that can be used to improve existing equipment.

This information can also be used when planning for and designing new installations.

5.2.3.2 Design

A disturbance record consists of fault record and fault waveform. A disturbance record is initiated

by fault detector element.

The disturbance record has two types:

1. Fault detector element picks up without operation of protective element.

2. Fault detector element picks up with operation of protective elements.

5.2.3.3 Capacity and Information of Disturbance Records

The device can store up to 64 disturbance records with waveform in non-volatile memory. It is

based on first in first out queue that the oldest disturbance record will be overwritten by the latest

one.



For each disturbance record, the following items are included:

1. Sequence number

Each operation will be recorded with a sequence number in the record and displayed on LCD

screen.

2. Date and time of fault occurrence

The time resolution is 1ms using the relay internal clock synchronized via clock synchronized

device if connected. The date and time is recorded when a system fault is detected.

3. Relative operating time

An operating time (not including the operating time of output relays) is recorded in the record.

4. Faulty phase

5. Protection elements

5.2.3.4 Capacity and Information of Fault Waveform

MON module can store 64 pieces of fault waveform oscillogram in non-volatile memory. If a new

fault occurs when 64 fault waveform have been stored, the oldest will be overwritten by the latest

one.

Each fault record consists of all analog and digital quantities related to protection, such as original

current and voltage, differential current, alarm elements, and binary inputs and etc.

Each time recording includes 10-cycle pre-fault waveform, and 250 cycles at least and 500 cycles

at most can be recorded.

5.2.4 Present Recording

Present recording is a waveform triggered manually on on the devices LCD or remotely through

PCS-PC software. Recording content of present recording is same to that of disturbance

recording.

Each time recording includes 10-cycle waveform before triggering, and 250 cycles at most can be

recorded.

6 Hardware


6 Hardware

Table of Contents

6.1 General Description ........................................................................................ 6-1

6.2 Typical Wiring .................................................................................................. 6-4

6.2.1 Conventional CT/VT (For reference only) ........................................................................... 6-4

6.2.2 ECT/EVT (For reference only) ............................................................................................. 6-6

6.3 Plug-in Module Description ............................................................................ 6-8

6.3.1 PWR Plug-in Module (Power Supply) ................................................................................. 6-8

6.3.2 MON Plug-in Module (Management) ................................................................................. 6-10

6.3.3 AI Plug-in Module (Analog Input) ....................................................................................... 6-13

6.3.4 DSP Plug-in Module (Fault Detector and Protection Calculation) .................................... 6-15

6.3.5 NET-DSP Plug-in Module (GOOSE and SV) .................................................................... 6-16

6.3.6 BI Plug-in Module (Binary Input)........................................................................................ 6-16

6.3.7 BO Plug-in Module (Binary Output) ................................................................................... 6-20

6.3.8 HMI Module........................................................................................................................ 6-22

List of Figures

Figure 6.1-1 Rear view of fixed module position ..................................................................... 6-1

Figure 6.1-2 Hardware diagram .................................................................................................. 6-2

Figure 6.1-3 Front view of PCS-924 ........................................................................................... 6-3

Figure 6.1-4 Typical rear view of PCS-924 ................................................................................ 6-4

Figure 6.2-1 Typical wiring of PCS-924 (conventional CT/VT) ................................................ 6-5

Figure 6.2-2 Typical wiring of PCS-924 (ECT/EVT) .................................................................. 6-7

Figure 6.3-1 View of PWR plug-in module ................................................................................ 6-9

Figure 6.3-2 Output contacts of PWR plug-in module ............................................................. 6-9

Figure 6.3-3 View of MON plug-in module .............................................................................. 6-11

Figure 6.3-4 Connection of communication terminal ............................................................ 6-13

6 Hardware


Figure 6.3-5 View of AI plug-in module ................................................................................... 6-14

Figure 6.3-6 View of DSP plug-in module ............................................................................... 6-15

Figure 6.3-7 View of NET-DSP plug-in module ....................................................................... 6-16

Figure 6.3-8 View of BI plug-in module (NR1503) .................................................................. 6-17

Figure 6.3-9 View of BI plug-in module (NR1504) .................................................................. 6-17

Figure 6.3-10 View of BO plug-in module (NR1521A) ............................................................ 6-21

Figure 6.3-11 View of BO plug-in module (NR1521C) ............................................................ 6-21

Table of Tables

Table 6.3-1 Terminal definition and description ....................................................................... 6-9

Table 6.3-2 Terminal definition of AI module .......................................................................... 6-14

6 Hardware


6.1 General Description

PCS-924 adopts 64-bit microchip processor CPU produced by FREESCALE as control core for

logic calculation and management function, meanwhile, adopts high-speed digital signal processor

DSP for all the protection calculation. 24 points are sampled in every cycle and parallel processing

of sampled data can be realized in each sampling interval to ensure ultrahigh reliability and safety

of protection equipment.

PCS-924 is comprised of intelligent plug-in modules, except that few particular plug-in modules

position cannot be changed in the whole device (gray plug-in modules as shown in Figure 6.1-1),

other plug-in modules like AI (analog input) and IO (binary input and binary output) can be flexibly

configured in the remaining slot positions.

MO

N m

od

ule

DS

P m

od

ule

PW

R m

od

ule

01 04 05 06 07 00

AI

mo

du

le

BI

mo

du

le

BO

mo

du

leSlot No.

02 03 08 09 10 11 12 13 14 15

BI

mo

du

le

BO

mo

du

le

BO

mo

du

le

BO

mo

du

le

Figure 6.1-1 Rear view of fixed module position

PCS-924 has 16 slots, PWR module, MON module and DSP module are assigned at fixed slots.

Besides 3 fixed modules are shown in above figure, there are 13 slots can be flexibly configured.

AI plug-in module, BI plug-in module and BO plug-in module can be configured at position

between slot B02, B03 and B06~B15. It should be pay attention that AI plug-in module will occupy

two slots.

This device is developed on the basis of our latest software and hardware platform, and the new

platform major characteristics are of high reliability, networking and great capability in

anti-interference great capability in anti-interference. See Figure 6.1-2 for hardware diagram.

6 Hardware


Conventional CT/VT

Exte

rnal

Bin

ary

Input

Outp

ut R

ela

y

+E

Pickup

Relay

Protection

Calculation

DSP

A/D

LCD

Fault

Detector

DSP

A/D

CPU

ECVT

ECVT

Power

SupplyUaux

Keypad

LED

Clock SYN

PRINT

RJ45

ETHERNET

Figure 6.1-2 Hardware diagram

The working process of the device is as shown in above figure: current and voltage from

conventional CT/VT are converted into small voltage signal and sent to DSP module after filtered

and A/D conversion for protection calculation and fault detector respectively (ECVT signal is sent

to the relay without small signal and A/D convertion). When DSP module completes all the

protection calculation, the result will be recorded in 64-bit CPU on MON module. DSP module

carries out fault detector, protection logic calculation, tripping output, and MON module perfomes

SOE (sequence of event) record, waveform recording, printing, communication between

protection and SAS and communication between HMI and CPU. When fault detector detects a

fault and picks up, positive power supply for output relay is provided.

The items can be flexibly configured depending on the situations like sampling method of device

(conventional CT/VT and ECT/EVT), the mode of binary output (conventional binary output and

GOOSE binary output), and whether it needs independent binary output for pole discrepancy

protection. The configurations for PCS-900 series based on microcomputer are classified into

standard and optional modules.

Table 6.1-1 PCS-924 module configuration

No. ID Module description Remark

1 NR1101/NR1102 Management module (MON module) Standard

2 NR1401 Analog input module (AI module ) Standard

3 NR1161 Protection calculation and fault detector module (DSP module) Standard

4 NR1503/NR1504 Binary input module (BI module) Standard

5 NR1521 Binary output module (BO module) Standard

6 NR1301 Power supply module (PWR module) Standard

7 NR1136 GOOSE and SV from merging unit by IEC61850-9-2 (NET-DSP Option

6 Hardware


No. ID Module description Remark

module)

8 Human machine interface module (HMI module) Standard

MON module provides functions like management function, event record, setting

management etc.

AI module converts AC current and voltage from current transformers and voltage

transformers respectively to small voltage.

DSP module performs filtering, sampling, protection calculation and fault detector calculation.

BI module provides binary inputs, the binary inputs are opto-couplers of rating

24V/110V/125V/220V/250V (configurable).

BO module provides output contacts for tripp[ing, and signal output contact for annunciation

signal, remote signal, fault and disturbance signal, operation abnormal signal etc.

PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of

the device.

HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user

as human-machine interface.

NET-DSP module receives and sends GOOSE messages, sampled values (SV) from

merging unit by IEC61850-9-2 protocol.

PCS-924 series is made of a 4U height 19 chassis for flush mounting. Components mounted on

its front include a 320240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex

RJ45 port. A monolithic micro controller is installed in the equipment for these functions.

Following figures show front and rear views of PCS-924 respectively.

ENT

ES

CG

RP

PCS-9241

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

HEALTHY

ALARM STUB DIFFERENTIAL RELAY

Figure 6.1-3 Front view of PCS-924

20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),

others are configurable.

For the 9-button keypad, ENT is enter, GRP is group number and ESC is escape.

6 Hardware


NR1102 NR1401

DANGER

NR1161

1

2

NR1504 NR1521 NR1521 NR1521 NR1521 NR1301

11

1

9

3

10

8

7

6

4

5

2

12

BO_COM1

BO_ALM

OPTO+

BO_FAIL

BO_ALM

BO_COM2

OPTO-

PWR+

PWR-

GND

BO_FAIL

5V ALM

BO_ALM BO_FAIL

OK

NR1504

Figure 6.1-4 Typical rear view of PCS-924

6.2 Typical Wiring

6.2.1 Conventional CT/VT (For reference only)

MO

N m

od

ule

DS

P m

od

ule

PW

R m

od

ule

01 04 05 06 07 00

AI

mo

du

le

BI

mo

du

le

BO

mo

du

le

Slot No.02 03 08 09 10 11 12 13 14 15

NR1301

BO

mo

du

le

BO

mo

du

le

NR1521ANR1504NR1102 NR1401 NR1161 NR1521C NR1521B

The following typical wiring is given based on above hardware configuration

6 Hardware


Ia

Ib

Ic

0201

0202

0203

0204

0205

0206

Cu

rren

t of C

T1

0225

0010

0011

0001

0002

0003

BO_FAIL

BO_ALM

0004

0005

0006

BO_FAIL

BO_ALM

0007

0008

0012

Power

Supply

PWR+

PWR-

OPTO+

OPTO-

External DC power

supply

Power supply for

opto-coupler (24V)

COM

COM

Multiplex

RJ45 (Front)Grounding

Bus

0801

0802

0807

0809

0814

0821

0808

0816

0815

+

+

+

+

+

+

Not used

Not used

Power supply supervision

BI_01

BI_06

BI_07

BI_12

BI_13

BI_18

0822-

PT

INT

ER

0101

0102

0103

0105

0106

0107SGND

RTS

TXD

SYN+

SYN-

SGND

Clo

ck S

YN

PR

INT

0104

0101

0102

0103

485-1A

485-1B

SGND

CO

M

0104

1101

1102

1103

1104

1105

1106

1121

1122

1201

1202

1203

1204

1205

1206

1221

1222

1301

1302

1303

1304

1305

1306

1317

1318

1319

1320

1321

1322

BO_01

BO_02

BO_03

BO_11

BO_01

BO_02

BO_03

BO_11

BO_01

BO_02

BO_03

BO_09

BO_10

BO_11

Co

ntro

lled

by fa

ult d

ete

cto

r

ele

me

nt

Sig

na

l Bin

ary

Ou

tpu

t (op

tion

)

Firs

t 9 c

on

tacts

co

ntro

lled

by fa

ult d

ete

cto

r

ele

me

nt a

nd

last 2

co

nta

cts

with

ou

t co

ntro

lled

by

fau

lt de

tecto

r ele

me

nt (o

ptio

n)

*BI p

lug

-in m

od

ule

ca

n b

e in

de

pe

nd

en

t co

mm

on

term

ina

l

To

the

scre

en

of o

the

r co

axia

l

ca

ble

with

sin

gle

po

int e

arth

ing

Ia

Ib

Ic

0207

0208

0209

0210

0211

0212

Cu

rren

t of C

T2

Ia

Ib

Ic

0213

0214

0215

0216

0217

0218C

urre

nt o

f CT

3

Figure 6.2-1 Typical wiring of PCS-924 (conventional CT/VT)

6 Hardware


01

NR1301

PWR

09080705040302 001312

NR1102

BOBIMON

NR1521NR1504

PCS-924 (conventional CT/VT and conventional binary output)

NET-

DSP

NR1136

PCS-924 (conventional CT/VT and GOOSE binary output)

NR1521

BO

NR1521

BO

06 10 11 14 15

NR1521

BO

Slot No.

Module ID

01

NR1301

PWR

09080705040302 001312

NR1102

BIAI DSPMON

NR1504NR1161NR1401

06 10 11 14 15Slot No.

Module ID

BI

NR1504

AI

NR1401

DSP

NR1161

6.2.2 ECT/EVT (For reference only)

MO

N m

od

ule

DS

P m

od

ule

PW

R m

od

ule

01 04 05 06 07 00

AI

mo

du

le

BI

mo

du

le

BO

mo

du

le

Slot No.02 03 08 09 10 11 12 13 14 15

NR1301

BO

mo

du

le

BO

mo

du

le

NR1521ANR1503NR1102 NR1401 NR1161 NR1521C NR1521B

The following typical wiring is given based on above hardware configuration.

6 Hardware


SV from

ECT/EVT

RX

0225

0010

0011

0001

0002

0003

BO_FAIL

BO_ALM

0004

0005

0006

BO_FAIL

BO_ALM

0007

0008

0012

Power

Supply

PWR+

PWR-

OPTO+

OPTO-

External DC power

supply

Power supply for

opto-coupler (24V)

COM

COM

Multiplex

RJ45 (Front)

Grounding

Bus

0801

0802

+BI_01

-

PT

INT

ER

0101

0102

0103

0105

0106

0107SGND

RTS

TXD

SYN+

SYN-

SGND

Clo

ck S

YN

PR

INT

0104

0101

0102

0103

485-1A

485-1B

SGND

CO

M

0104

1101

1102

1103

1104

1105

1106

1121

1122

1201

1202

1203

1204

1205

1206

1221

1222

BO_01

BO_02

BO_03

BO_11

BO_01

BO_02

BO_03

BO_11

Co

ntro

lled

by fa

ult d

ete

cto

r

ele

me

nt

Sig

na

l Bin

ary

Ou

tpu

t (op

tion

)

0803

0804

+BI_02

-

0805

0806

+BI_03

-

0821

0822

+BI_11

-

Phase A

Phase B

Phase C

MU

TX

FO

inte

rface

for S

V c

ha

nn

el

Up

to 8

(LC

Typ

e)

IRIG-B

*BI p

lug

-in m

od

ule

ca

n b

e c

om

mo

n n

eg

ativ

e

term

ina

l

To

the

scre

en

of o

the

r co

axia

l

ca

ble

with

sin

gle

po

int e

arth

ing

Figure 6.2-2 Typical wiring of PCS-924 (ECT/EVT)

PCS-924 ECT/EVT, GOOSE binary output and binary output

01

NR1301

PWR

09080705040302 001312

NR1102

DSP BIMON

06 10 11 14 15Slot No.

Module ID

NET-

DSP

NR1136 NR1504NR1161

PCS-924 ECT/EVT, conventional binary output and binary output

01

NR1301

PWR

09080705040302 001312

NR1102

DSP BOBIMON BO BO

06 10 11 14 15Slot No.

Module ID

NET-

DSP

NR1136 NR1521NR1504NR1161 NR1521 NR1521 NR1521

BOBI

NR1504

In the protection system adopting electronic current and voltage transformer (ECT/EVT), the

merging unit will merge the sample data from ECT/EVT, and then send it to the device through

6 Hardware


multi-mode optical fibre. DSP module receives the data from merging unit through the optical-fi

05 - pcs924 stub differential relay

Documents

protection function

introduction pcs

powerful protection

application pcs

s phase overcurrent

functional diagram of

communication rear ports

ethernet ports