060316 verilog(gate level))access.ee.ntu.edu.tw/course/under_project_94/pdf/... · 2010-07-14 ·...

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Graduate Institute of Electronics Engineering, NTU

UnderUnder--Graduate ProjectGraduate Project

Speaker : ChenjoProf. : Andy Wu


pp. 2

OutlineOutlinevBasic Concept of Verilog HDLvGate Level ModelingvSimulation & VerificationvSummary


pp. 3

What is What is VerilogVerilog HDL ?HDL ?v Hardware Description LanguagevMixed level modelingv BehavioralØ Algorithmic ( like high level language)ØRegister transfer (Synthesizable)

v Register Transfer Level (RTL)ØDescribing a system by the flow of data and control signals

within and between functional blocksØDefine the model in terms of cycles, based on a defined clock

v StructuralØGate (AND, OR ……)Ø Switch (PMOS, NOMS, JFET ……)


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An ExampleAn Example11--bit Multiplexerbit Multiplexer

in1

in2out

0

1

sel

if (sel==0) out = in1;else out = in2;

out = (sel’‧in1) + (sel‧in2)

sel in1 in2 out

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

to “select” output


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Gate Level DescriptionGate Level Description

a1

a2

in1

in2

sel

outo1

iv_sel a1_o

a2_on1

iv_sel

Gate Level: you see only netlist (gates and wires) in the code


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VerilogVerilog Language RulesLanguage Rulesv Verilog is a case sensitive language (with a few exceptions)v Identifiers (space-free sequence of symbols)v upper and lower case letters from the alphabetv digits (0, 1, ..., 9) (cannot be the first character)v underscore ( _ )v $ symbol (only for system tasks and functions)v Max length of 1024 symbols

v Terminate lines with semicolon ;v Single line comments:v // A single-line comment goes here

v Multi-line comments:v /* Multi-line comments like this */


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VerilogVerilog HDL SyntaxHDL Syntax

declaration syntax

module name in/out port

port/wiredeclaration

kernel hardwaregate-connection/behavior


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Module Module v Basic building block in Verilog.v Module

1. Created by “declaration” (can’t be nested)2. Used by “instantiation“Interface is defined by portsMay contain instances of other modulesAll modules run concurrently


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InstancesInstancesv A module provides a template from which you can

create actual objects.vWhen a module is invoked, Verilog creates a unique

object from the template.v Each object has its own name, variables, parameters

and I/O interface.


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Module Instantiation Module Instantiation

Adder

Adder Adder

Adder_tree

instance example


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Port ConnectionPort Connection

v Connect module port by order listØ FA1 fa1(c_o, sum, a, b, c_i);

v Not fully connectedØ FA1 fa3(c_o,, a, b, c_i);

v Connect module port by name .PortName( NetName ) Ø FA1 fa2(.A(a), .B(b), .CO(c_o),.CI(c_i), .S(sum));ØRecommended


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Register and NetRegister and Netv Registersv Keyword : reg, integer, time, realv Event-driven modelingv Storage element (modeling sequential circuit)v Assignment in “always” block

v Netsv Keyword : wire, wand, wor, tri

triand, trior, supply0, supply1v Doesn’t store value, just a connectionv input, output, inout are default “wire”v Can’t appear in “always” block assignment


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Wire & Wire & RegRegv regv A variable in Verilog

v Use of “reg” data type is not exactly synthesized to a really register.

v Use of wire & regvWhen use “wire”è usually use “assign” and “assign” does

not appear in “always” blockvWhen use “reg”è only use “a=b” , always appear in “always” block

module test(a,b,c,d);input a,b;output c,d;reg d;assign c=a;always @(b)

d=b;endmodule

module test(a,b,c,d);input a,b;output c,d;reg d;assign c=a;always @(b)

d=b;endmodule


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Logic SystemLogic Systemv Four values: 0, 1, x or X, z or Z // Not case sensitive herev The logic value x denotes an unknown (ambiguous) valuev The logic value z denotes a high impedance

v Primitives have built-in logicv Simulators describe 4-value logic

ab

y

0 1

x

a

b

y

x

xx

z

z z z zx x x x

0 1 X Z0 0 0 0 01 0 1 X XX 0 X X XZ 0 X X X


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Number RepresentationNumber Representationv Format: <size>’<base_format><number>v <size> - decimal specification of number of bitsØ default is unsized and machine-dependent but at least 32 bits

v <base format> - ' followed by arithmetic base of numberØ <d> <D> - decimal - default base if no <base_format> givenØ <h> <H> - hexadecimalØ <o> <O> - octalØ <b> <B> - binary

v <number> - value given in base of <base_format>Ø _ can be used for reading clarityØ If first character of sized, binary number 0, 1, x or z, will extend

0, 1, x or z (defined later!)


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Number RepresentationNumber RepresentationvExamples:v6’b010_111 gives 010111v8’b0110 gives 00000110v4’bx01 gives xx01v16’H3AB gives 0000001110101011v24 gives 0…0011000v5’O36 gives 11110v16’Hx gives xxxxxxxxxxxxxxxxv8’hz gives zzzzzzzz


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Net ConcatenationsNet ConcatenationsvA easy way to group nets

Sign extension{{8{byte[7]}},byte}

8‘b01010101{4{2‘b01}}

{a, b[3], b[2], b[1], c, 1’b1, 1’b0}{a,b[3:1],c,2’b10}

{b[7], b[6], b[5], b[4], c[3], c[2], c[1], c[0]}{b[7:4],c[3:0]}

{cout, sum}{cout, sum}

MeaningsRepresentation


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Compiler Directives Compiler Directives v `definev `define RAM_SIZE 16v Defining a name and gives a constant value to it.

v `includev `include adder.vv Including the entire contents of other verilog source file.

v `timescalev `timescale 100ns/1nsv Setting the reference time unit and time precision of your

simulation.


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System TasksSystem Tasksv $monitorv $monitor ($time,"%d %d %d",address,sinout,cosout);v Displays the values of the argument list whenever any

of the arguments change except $time.v $displayv $display ("%d %d %d",address,sinout,cosout);v Prints out the current values of the signals in the

argument listv$finishv $finishv Terminate the simulation

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Gate Level ModelingGate Level Modeling


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Gate Level ModelingGate Level ModelingvStepsvDevelop the boolean function of outputvDraw the circuit with logic gates/primitivesvConnect gates/primitives with net (usually wire)

vHDL: Hardware Description LanguagevFigure out architecture first, then write code.


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PrimitivesPrimitivesvPrimitives are modules ready to be instancedvSmallest modeling block for simulatorvVerilog build-in primitive gatevand, or, not, buf, xor, nand, nor, xnorvprim_name inst_name( output, in0, in1,.... );ØEX. and g0(a, b, c);

vUser defined primitive (UDP)vbuilding block defined by designer


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Case StudyCase Study11--bit Full Adderbit Full Adder

A B

CiCo

S

FullAdder


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v co = (a•b) + (b•ci) + (ci•a);


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vsum = a b ci


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vFull Adder ConnectionvInstance ins_c from FA_covInstance ins_s from FA_sum

abc

sum

abbcca

co

carry out connection

sum connection

full adder

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Timing and DelaysTiming and Delays


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Delay Specification in PrimitivesDelay Specification in PrimitivesvDelay specification defines the propagation

delay of that primitive gate.

not #10 (out,in);


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Types of Delay ModelsTypes of Delay Modelsv Distributed Delayv Specified on a per element basicv Delay value are assigned to individual in the circuit

ab

c

d

e

f

out

#5

#7

#4

module and4(out, a, b, c, d);……and #5 a1(e, a, b);and #7 a2(f, c, d);and #4 a3(out, e, f);

endmodule


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Types of Delay ModelsTypes of Delay Modelsv Lumped Delayv They can be specified as a single delay on the output gate of

the modulev The cumulative delay of all paths is lumped at one location

ab

c

d

e

f

out#11

module and4(out, a, b, c, d);……and a1(e, a, b);and a2(f, c, d);and #11 a3(out, e, f);

endmodule


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Types of Delay ModelsTypes of Delay Modelsv Pin-to-Pin Delayv Delays are assigned individually to paths from each input to

each output.v Delays can be separately specified for each input/output

path.

ab

c

d

e

f

out

Path a-e-out, delay = 9Path b-e-out, delay =9Path c-f-out, delay = 11Path d-f-out, delay = 11


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Timing Checks Timing Checks vsetup and hold checks

setuptime

holdtime

clock

data

specify $setup(data, posedge clock, 3);

endspecify

specify $hold(posedge clock, data, 5);

endspecify

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Simulation & VerificationSimulation & Verification


pp. 34

Test Methodology Test Methodology v Systematically verify the

functionality of a model. v Simulation:

(1) detect syntax violations in source code

(2) simulate behavior (3) monitor results

DesignTop Module

input ports

output ports

Test bench

data_oEqual?

answer_o

data_i


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Testbench for Full AdderTestbench for Full Addermodule t_full_add();reg a, b, cin; // for stimulus waveformswire sum, c_out;full_add M1 (sum, c_out, a, b, cin); //DUTinitial #200 $finish; // Stopwatchinitial begin // Stimulus patterns$fsdbDumpfile(“t_full_add.fsdb”);$fsdbDumpvars;#10 a = 0; b = 0; cin = 0; // Statements execute in sequence#10 a = 0; b = 1; cin = 0; #10 a = 1; b = 0; cin = 0; #10 a = 1; b = 1; cin = 0; #10 a = 0; b = 0; cin = 1; #10 a = 0; b = 1; cin = 1; #10 a = 1; b = 0; cin = 1; #10 a = 1; b = 1; cin = 1;endendmodule


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Simulation ResultsSimulation Results

MODELING TIP

A Verilog simulator assigns an initial value of x to allvariables.


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Example: Propagation Delay Example: Propagation Delay v Unit-delay simulation reveals the chain of events

module Add_full (sum, c_out, a, b, c_in);output sum, c_out;input a, b, c_in;wire w1, w2, w3;

Add_half M1 (w1, w2, a, b);Add_half M2 (sum, w3, w1, c_in);or #1 M3 (c_out, w2, w3);

endmodule

module Add_half (sum, c_out, a, b);output sum, c_out;input a, b;

xor #1 M1 (sum, a, b); // single delay value formatand #1 M2 (c_out, a, b); // others are possible

endmodule


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Simulation with delaySimulation with delay


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SummarySummaryv Design modulev Gate-level or RT-levelv Real hardwareØ Instance of modules exist all the time

v Each module has architecture figureØ Plot architecture figures before you write verilog codes

v Test benchv Feed input data and compare output values versus timev Usually behavior levelv Not real hardware, just like C/C++


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NoteNotev Verilog is a platformØ Support hardware design (design module)Ø Also support C/C++ like coding (test bench)

v How to write verilog wellØ Know basic concepts and syntaxØGet a good reference (a person or some code files)Ø Form a good coding habit

Naming rule, comments, format partition (assign or always block)v HardwareØCombinational circuits

畫圖(architecture), then 連連看(coding)Ø Sequential circuits

register: element to store data

060316 verilog(gate level))access.ee.ntu.edu.tw/course/under_project_94/pdf/... · 2010-07-14 ·...

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