1 2004 winter itrs conference lithography international technical working group

1

2004 Winter ITRS Conference

Lithography International Technical Working Group

2

Lithography iTWG Participants at Winter Meeting

Japan

Masaomi Kameyama (Nikon)

Isamu Hanyu (Fujitsu)

Masaru Sasago (Matsushita)

Naoya Hayashi (Dai Nippon Printing)

Iwao Higashikawa (Toshiba)

Masaki Yamabe (Fujitsu)

Europe

Mauro Vasconi (ST Microelectronics)

Reiner Garreis (Carl Zeiss SMT)

Andreas Dorsel (Carl Zeiss SMT)

Korea

Hanku Cho (Samsung)

Taiwan

Burn Lin (TSMC)

Benjamin Lin (UMC)

US

Scott Hector (SEMATECH and Freescale Semiconductor)

Giang Dao (SEMATECH and Intel)

3

Highlights of Plans for 2005 Lithography Update

• Agreed on larger printed CD in resist and 75/25 error budget allocation for litho and etch

• Developed plan to determine effect of CD variability on device performance with Design, PIDS and FEP and consider increasing CD tolerance to >10%

• Proposed definition of LWR and LER with Metrology TWG to account for metrology, transistor and interconnect performance

• Propose to reduce overlay tolerances to reflect use of dedicated tools to achieve better performance than shown in 2004 roadmap

• Plan to update potential solutions

4

High level agenda for Litho iTWG meetings in 2005

• SPIE: Should we plan a meeting at SPIE in February? No

• Spring: Review changes for year, each region proposes potential solutions

• Summer: Each iTWG chair reports on results of review of changes and potential solutions by each iTWG; identify items that should be addressed in next update year; editing of difficult challenges tables

• Winter: Start debating items identified at summer meeting and plan for next update year and

5

Agenda for 2004 Winter iTWG and Cross TWG meetings

• Cross TWG preparations– Factory– Metrology– CSNTG– Modeling– Yield– Metrology– ESH

• Brief review of 2004 update• Discuss 2005 changes

6

Topics for Cross TWG MeetingsLitho Factory Integration

• APC challenges (provided presentation by Vasconi)– Tool-to-tool matching for high mix fabs

• Environment control (airborne molecular contamination)• Mask quality control—cumulative mask defects• Mask shop operations• Tool footprint, height and weight for future nodes; vibration

requirements for fab vs. equipment isolators• Gas usage requirements (for purging, EUV source fuel and debris

buffering, etc.)• Litho cell throughput—integrated throughput requires large area track

with many modules and faster mask exchange times– Traffic jam of carriers in litho sector and mask storage capacity– Mask automation interfaces

• House water quality and pressure for immersion lithography; cooling water temperature and flow rate for EUV

• EM effects on mask and equipment

7

Topics for Cross TWG Meetings Litho Metrology

• LER/LWR – Presentation by Hitachi– Propose metrology centric definition in ITRS but values should be broken into low

and high spatial frequency regimes and determined based on effects on device performance

– Low frequency roughness (affects transistor drive current, Vt and leakage current)– High frequency roughness (may affect interconnect reliability but smoothed by

dopant diffusion and requires additional study)

• CD control– Increase in ADI (printed in resist) to ACI (after etch) CD bias proposed for 2005

• Tool-to-tool matching requirements– Becoming very critical for mask and wafer CD metrology (see Microlithography

World November 2004 and Leica presentation at SPIE BACUS September 2004)– Difficulty of achieving this might be noted with separate values for repeatability and

matching

• Incorporating CD measurements into APC, scatterometry• EUV tool components metrology

8

Roughness definitions (reported as rms values)

• LWR = all spatial wavelengths between 1 micron and 20 nm over a 2 micron length with a spacing of 10 nm.

• LER = all spatial wavelengths between 1 micron and 15nm taken over a 2 micron length with a spacing of 7.5nm. – For monitoring specular scattering—measure from

15nm to twice the smallest interval using the smallest possible interval.

– Longer wavelengths affect reliability, and short wavelengths increase line resistivity

– Measure sidewall after barrier metal deposition

9

Topics for Cross TWG Meetings Litho CSNTG

• CD control– US and Japan TWG studies concluded that <4nm 3 CD control has no

known solutions

– CD control will remain red for the present and future nodes

– Printed gate length in resist values to be re-evaluated in 2005

• LWR/LER effects on device performance– Propose metrology centric definition in ITRS but values should be broken

into low and high spatial frequency regimes and determined based on effects on device performance

– The low and high frequency cutoffs should be based on device performance effects

• DFM– Propose section on DFM in Litho (coordinate with Design and Yield)

• Litho field size adjustment (22 by 32mm now; should it be larger?)

10

Results of logic device CD value survey

• Survey reflects present status of lithography in manufacturing at six companies which responded– Significant trim bias is used– M1 contacted half pitch in most cases is larger than 107 nm

predicted for 2004 in 2003 update of ITRS

0

1

2

3

4

>13

0

>12

0

>11

0

>10

0

>90

>80

>70

>60

>50

>40

>30

>20

>10 0

Linewidth or pitch bins (nm)

Nu

mb

er o

f re

spo

nd

ents

Min M1 1/2 pitch

Min printed Lg

Min etched Lg

Trim used

Minimum value in range

11

01234

13

%

12

%

11%

10

%

9%

8%

Linewidth or pitch bins (nm)

Nu

mb

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f re

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% 3 sigma Lg % actual 3 sigma, printed Lg % actual 3 sigma, etched Lg

Results of logic device CD control survey

• Majority are not meeting the 10% CD Control targets at present.• Majority support the 75/25 Litho/FEP responsibility split. (not shown in chart)• Relaxing the nominal Printed Gate Length target does not solve the problem - need

consensus on relaxation of gate length control from 10% to 12% in order to change cell colors from red.

• Majority will not approve relaxation of the 10% target, citing their company designers and specified finished product performance as reason for inflexibility.

Minimum value in range

12

Simulations indicated larger CD in resist provides better total CD

control. They also indicated that ITRS total CD control values will

probably not be achieved, starting at the 65nm node.

13

Trends to manage CD control and yield• Present approaches are not enough

– More stringent design rule restrictions• Single orientation, pitch restrictions

– Larger CD on resist and larger etch bias– Relaxed minimum half pitch– Use of RET on more layers– Field by field and within field dose corrections

• Further actions--DFM– Automation of software analysis of weak spots in design and feedback to physical

layout of cells• RET applied to library cell layouts

– Coordinates of weak points provided to mask and wafer CD metrology tools• Focus and exposure are optimized for printing hot spot regions with maximum process

latitude rather than for CD of CD bars.

– Identification of critical timing paths to locally specify CD control and intensity of RET– Test programs optimized to detect electrical effects at weak points – Local corrections of mask to account for variations of scanner—mask specification to

particular scanners – Software for reduction of slivers in design data is also being developed to reduce

mask CD error and writing time.

Based on AMD, Cadence, Cypress, IBM, Intel, ASML, PLAB, TI and Toshiba presentations at SPIE, PMJ, IEEE Litho and BACUS

Example of content that may be included in text of Litho chapter for 2005

Example of content that may be included in text of Litho chapter for 2005

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Topics for Cross TWG Meetings Litho Modeling

• Polarization effects with NA>0.85, including illumination and mask effects

• Simulation accuracy for RET for low k1

• LWR effect on devices• DFM• Full chip predictive patterning simulation• Stray light simulation accuracy

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Topics for Cross TWG Meetings Litho Yield

• DFM challenges—predictive simulation of patterning performance and correction of design and mask data (check for weak designs)– Propose section in 2005 Litho ITRS chapter to be

coordinated with Design and Yield iTWGs

• Metrology for shorts and opens• Immersion-related defects• Low k1 process effects on yield and device

performance effects of larger CD variation—deterministic errors driving yield loss– How does this fit with yield models?

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Topics for Cross TWG Meetings Litho ESH

• PFOS reduction and ban affects resist and developer material selection

• EUV challenges with sources– Power requirements– Proposal to use Li droplets

17

Summary of 2004 Update to Lithography Chapter of the ITRS


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Changes to Lithography Tables in 2004• CD control (total CD control)

– US and Japan TWG studies concluded that <4nm 3 CD control has no known solutions

– CD control will remain red for the present and future nodes– Printed gate length in resist values to be re-evaluated in 2005

• Definition of potential solutions– More specific criteria for N to N+2 nodes – N+3 node and beyond may be more broad ranging and inclusive

• Difficult challenges updated, emphasizing needs for immersion• Changes to coloring, footnotes, etc.

– Definition of overlay in overall lithography requirements Tables 77a and 77b– Mask table values updated– Resist table values updated

• More discussion needed (2005 updates probable)– LWR/LER definitions and values with input from PIDS, FEP and Metrology– APC requirements

2004 Lithography exposure tool potential solutions

Notes: EPL is a potential solution at the 65, 45 and 32-nm nodes for one geographical region, and PEL is a potential solution at the 32-nm node for one geographical region. RET will be used with all optical lithography solutions, including with immersion; therefore, it is not explicitly noted.

Unofficial version of Figure 34; Not for publication

Technology Node

2007 2013 20192004 20162010

hp90 hp65 hp32 hp16hp22hp45

Research Required

Development Underway

Qualification/Pre-Production

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EUV193nm immersion + LFD157nm immersion + LFD, ML2Imprint

22

EUVInnovative 157nm or 193 nm immersionML2Imprint, innovative technology

16Innovative technology

ML2, EUV + RET, imprint

45193nm immersion + LFDEUVML2, 157nm immersion, PEL

RET = Resolution enhancement technologyLFD = Lithography friendly design rulesML2 = Maskless lithography

Lithography Potential Lithography Potential Solutions in 2004 UpdateSolutions in 2004 Update

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Summary of 2004 Lithography Chapter Updates

• Defined new criteria for evaluating near-term potential solutions

• Stronger emphasis on difficult challenges related to immersion lithography

• Continued emphasis on challenges for implementing cost-effective post-optical lithography solutions

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2003 ITRS potential solutions

Technology Node

2007 2013 20192004 20162010


2003 2005 2006 2008 2009 2011 2012 2014 2015 2017 2018

Research Required Development Underway Qualification/Pre -Production Continuous Improvement

This legend indicates the time during which research, developmen t, and qualification/pre -production should be taking place for the solution.

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32

EUV157 nm immersion + RET + litho -friendly designsEPL, imprint lithographyML2

Narrowoptions

22Narrowoptions

EUV, EPLML2, imprint lithographyInnovative technology

16Narrowoptions

Innovative technologyML2, EUV + RET

45

157 nm + RET + litho -friendly designsImmersion 193 nm lithography + RET + litho -friendly designsEPL, PEL, ML2PEL

Narrowoptions

Technology Node

2007 2013 20192004 20162010


2003 2005 2006 2008 2009 2011 2012 2014 2015 2017 2018

Research Required Development Underway Qualification/Pre -Production Continuous Improvement

This legend indicates the time during which research, developmen t, and qualification/pre -production should be taking place for the solution.

Technology Node hp90 hp65 hp32 hp16hp22hp45

2003 2005 2006 2008 2009 2011 2012 2014 2015 2017 20182007 2013 20192004 20162010

hp90 hp65 hp32 hp16hp22hp45hp90 hp65 hp32 hp16hp22hp45

2003 2005 2006 2008 2009 2011 2012 2014 2015 2017 20182003 2005 2006 2008 2009 2011 2012 2014 2015 2017 2018

Research Required Development Underway Qualification/Pre -Production Continuous ImprovementResearch Required Development Underway Qualification/Pre -Production Continuous ImprovementResearch RequiredResearch Required Development UnderwayDevelopment Underway Qualification/Pre -ProductionQualification/Pre -Production Continuous ImprovementContinuous Improvement



DRAM Half Pitch (dense lines)

-

90 193 nm + RET

65Narrowoptions


32


Narrowoptions

22Narrowoptions


16Narrowoptions


45


Narrowoptions

90 193 nm + RET

65Narrowoptions


32


Narrowoptions

22Narrowoptions


16Narrowoptions


45


Narrowoptions

193 nm + RET193 nm + RET193 nm + RET

Narrowoptions


193 nm + RET + LFD157 nm + RET + LFD193 nm immersion EPL, PEL


Narrowoptions

friendly designs

ML2

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Narrowoptions


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90

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157 nm + RET + LFD 193 nm immersion + RET + LFDEUV, EPL, PEL, ML2

EUV157 nm immersion + RET + LFDEPL, imprintML2

EUV, EPLML2, imprintInnovative technology


Unofficial version of 2003 table; Not for publication

RET = Resolution enhancement technologyLFD = Lithography friendly design rules

DR

AM

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nm

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New criteria for potential solutions

• All infrastructure (masks, tools, resist,…) needs to be in place to meet the ramp for the specified node

• Technology must be planned to be used by IC makers in at least two geographical regions– For N+3 and later nodes with black coloring, the requirement

to have more than one region support is not applicable

• Technology should be targeting leading edge critical layer needs

• Consideration (not a requirement): 100 tools worldwide over the life of that tool generation

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Proposed process for evaluating potential solutions

• Each regional TWG will evaluate options known to that TWG for each node against criteria

• Each TWG will judge the potential readiness of the technology for that node and make a recommendation to iTWG on whether to include it at that node– The process for deciding on a recommendation to the iTWG will

established within each regional TWG.

– Each TWG will judge the probability and or widespread use of each potential solution at each node. The potential solutions that qualify for each node will be ranked with highest probability and most widespread adoption ranked higher than other potential solutions

• A solution will be added if at least two regional TWGs support its inclusion.

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Transition of ITRS Litho Potential SolutionsTransition of ITRS Litho Potential Solutions

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Difficult Challenges - Short Term (1)

Five difficult challenges 50 nm before 2009.

Summary of issues

Optical masks with features for resolution enhancement and post-optical mask fabrication

Registration, CD control, defect control for optical masks

Development of defect free multi-layer EUV substrates or EPL membrane masks

Equipment infrastructure (writers, inspection, repair)

Data volume Cost control and

return-on-investment (ROI)

Achieving constant/improved ratio of exposure related tool cost to throughput over time

Cost-effective resolution enhanced optical masks and post-optical masks.

Sufficient lifetime for exposure tool technologies Resources for developing multiple technologies

at the same time. ROI for small volume products

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Difficult Challenges - Short Term (2)

Five difficult challenges 50 nm before 2009.

Summary of issues

Process control Processes to control gate CDs to less than 4 nm 3

New and improved alignment and overlay control methods independent of technology option to 19 nm overlay

Accuracy of OPC, especially in presence of polarization effects

Control of flare in exposure tool Lithography friendly design and design for

manufacturing Resists for 193nm

and 193nm immersion lithography

Outgassing and leaching during immersion, LER, SEM induced CD changes, defects 30 nm.

Resists with high index Defect control Control of defects caused in immersion

environment

27

Difficult Challenges - Long Term (1)Five difficult

challenges 45 nm beyond 2010.

Summary of issues

Mask fabrication and process control

Defect-free NGL masks, especially for 1X masks for imprint and EUVL mask blanks free of printable defects.

Timeliness and capability of equipment infrastructure (writers, inspection, repair), especially for 1X masks.

Mask process control methods and yield enhancement.

Pellicles for 157nm immersion and protection of EUV masks from defects without pellicles

Metrology and defect inspection

Resolution and precision for critical dimension measurement down to 7 nm, including line width roughness metrology for 2.2nm 3sigma.

Metrology for overlay down to 7.2 nm Defect inspection for patterned wafers for defects <

30 nm. Cost control and return

on investment (ROI) Achieving constant/improved ratio of exposure related

tool cost to throughput. Development of cost-effective optical and NGL masks. Achieving ROI for industry with sufficient lifetimes for

the technologies and for small volume products.

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Difficult Challenges - Long Term (2)Five difficult

challenges 45 nm beyond 2010.

Summary of issues

Gate CD control improvements; process control; resist materials

Development of processes to control gate CD < 4 nm (3 sigma) with appropriate line width roughness.

Development of new and improved alignment and overlay control methods independent of technology option to < 7.2 nm overlay, especially for nanoimprint.

Process control and design for low k1 optical lithography

Resists including high index, high index fluids and high index optical materials to extend optical immersion to its limits

Limits of chemically amplified resist sensitivity for <50-nm linewidths due to acid diffusion length

Tools for mass production

Optical and NGL exposure tools capable of meeting requirements of the ITRS

High output, cost-effective EUV light sources CaF2 cost, yield and quantity for 157nm immersion

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Lithography ITWG Chairmen and Co-chairmen for 2004

Region Chairmen Co-ChairmenTaiwan Burn J. Lin G. C. HungJapan Masaomi Kameyama Isamu HanyuKorea Han-Ku Cho

Europe Mauro Vasconi Jan-Willem GemminkUSA Scott Hector Maureen Hanratty

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Proposed Updates to Lithography Chapter of the 2005 ITRS


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High level action items for 2005 update Each region to propose potential solutions for each node based on process

agreed in July 2004 (by April 2005) (Hector to send out spreadsheet for 2005 inputs by December 31, 2004)

Check Metrology and FEP tables for consistency with Litho (Hector by September 2005)

o Provide contamination levels for lens, mask and wafer purging at 193nm, EUV and 157nm to Yield and Factory Integration TWGs (Kameyama)

o Nikon and Canon discussing requirements, and resulting agreement will be sent to ASML by February 2005

o Review Mask tables with industry stakeholders and send results to iTWG (Hector in February 2005)

o Include APC in 2005 text and review APC section in Metrology (European TWG by April 2005) (Metrology to send text to the European TWG)

o Litho iTWG to send quantitative data to Factory Integration iTWG where possible on EUV tool requirements, tool footprint, height and weight ranges, mask inspection and handling requirements in the fab (Hector to collect data)

o Factory Integration to send data to Litho on mask shop data handling from DPI and Litho to send papers on progressive defects to Factory Integration (Hector)

o Litho needs to identify owner to help Metrology with text on sensors inside litho tools (Hector)

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High level action items for 2005 update (cont.)o Communicate proposed resist tables updates to iTWG resist experts (Hector by December

31, 2004)

o Develop qualitative tables and/or text for DFM, progression of RET approaches, R&D ROI, 450mm issues and cost of ownership for 2005 text (Hector by April 2005)

o Find owner for 1X mask tables (Hector by February 2005)

o Send LER white paper and references to Design and PIDS TWG (Hector)

o Consider whether to include EPL tables in 2005 (Kameyama to discuss with Japan TWG)

o Report back to TNSG on what % CD variation will result in 4nm and 3.5nm 3sigma CD control values (Hector by December 31, 2004)

o Check to see if +-2 degrees C water temperature control input to lithography tools is OK (Kameyama by April 2005)

o Yield TWG will send yield model survey results to Litho by the end of January 2005, Litho to review and provide feedback promptly (Hector)

o Litho TWG to review M&S cross cut text and send comments to Modeling TWG (Hector

o Litho to provide input on DFM and cost savings sections of M&S draft 2005 chapter (Hector after July meeting)

o Metrology to send LWR/LER definitions to FEP, PIDS and Interconnect

o Prepare proposed change to overlay requirements (Hector by February)

o Provide ESH TWG range of power requirements for EUV sources (Hector)

o Provide contact at Cymer for ESH TWG regarding use of Li in EUV sources (Hector)

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Possible 2005 Updates• Text

– Table showing progression of low k1 methods (Hector)– DFM section (Hector to complement Design chapter content)– APC detail in chapter (Vasconi)– Cost of ownership factors and throughput factors in text (formula and sensitivity)

(Hector)

• CD control– Increase printed gate CD in resist– Consider separate flash CD control requirement (e. g. DRAM is presently

>10%) (keep at 10%)

• Litho field size limit (presently 22by32mm, should it be larger?)• Review colors and values in overall litho, resist and mask tables

– Overlay split into tool-tool (same) and tool-to-itself (20% of half pitch) lines

• Resist table content changes• Potential solutions

– Each TWG to propose changes by July (preview in April)– Consider having potential solutions tables for high and low volume applications

(No) (Explore some text to explain potential for two solutions)

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Example table: Increasing complexity of RETNode 180nm 130nm 90nm 65nm 45nmk 1 range 0.5 - 0.65 0.49 - 0.52 0.47 - 0.53 0.40 - 0.43 0.31 - 0.40

Design rulesMinor restriction

Allow OPC and PSM

Allow OPC, PSM, SRAF

(Restrictions)Minimum pitch and linewidth Pitch

Contact location and pitch

Contact location, pitch and orientation

Masks

Rule-based OPCMBOPC for gate

Model-based OPC (MBOPC)SRAF on poly

Model-based OPC w/ SRAF

Model-based OPC w/ SRAF

Model-based OPC, SRAF, polarization corrections

(Gate)APSM and hiT EPSM

APSM, hiT EPSM, dual dipole?

(Contacts/vias)Resist

Thickness<500-nm thickness

<300-nm thickness

SubstrateEtch

ToolOff-axis illumination Quadrupole

Cross wafer dose adjustments

Process controlOffsets from previous lots Automated process control with downloaded offsets

<200-nm thicknessARC

Litho friendly design rules

Dose adjustment along scan

cPSM and EPSM

Custom illumination Automated NA/sigma control

Selection based on aberrations Aberration monitoring

Custom by layer type

ARC, hard masksPost development resist width reduction

EPSM EPSM / HiT PSM

35

Proposed Changes to ITRS Lithography Requirements

• Consider update of tables to larger CD in resist (printed gate length) No change in 2004, subject to further discussions for 2005

• Re-evaluate all colors– Examine long term coloring in context of primary solution at each

node

– No proposed changes to colors in Table 77b due to legitimately no known solutions to each box colored red.

• Overlay…

36

Proposed Changes to ITRS Resist Tables Re-evaluate all colors in resist tables

Input from resist suppliers toward matching capability (colors) with requirements (numbers)

Re-examine defect size in resist films Spin coated resist defects saturates at 0.01 cm-2, will it really remain constant?

Back surface particles updated based on FEP values Requirement for immersion-induced defects (revisit this in July—maybe 2006) Improved LWR/LER definition and requirement values LER specification for contact holes (striations,… as opposed to lack of

roundness) Resist requirements for contacts

Separate line or footnote describing option of shrinking contact size in resist before etch

Include statement about resist parameters applying to poly and or contacts in text

Resist aspect ratio inconsistent (aspect ratio up to 3.5 possible; make sure that resist thickness matches aspect ratio requirements)

Effect of resist diffusion length on tradeoff between LER/sensitivity/CD control for chemically amplified resists (address need for new resist approaches)

Legend: Proposed changeo In progress• or – Not yet addressed

37

Proposed Changes to ITRS Lithography Optical Mask Table 79a

• Extend tables to the 22nm half pitch nodeo Re-evaluate MEEF for contacts and lines

o SEMATECH simulation results available for lines

o Look at DOF budget to set mask blank flatness targets• Re-evaluate colors for all parameters

Proposed changes to be discussed at SEMATECH with mask industry reps in February 2005 (Open to all)

Sent results to iTWG chair persons for further review• Mask reflectivity drops too slow—removed in 2004• Relaxed CD specs for APSM may not be realistic; some error budget

should be shared• BIM CD control for masks important for active layer cycle time


38

Proposed Changes to ITRS Lithography Optical Mask Table 79a (2)

• Definition of OPC sizes in Optical Mask Table– European iTWG to make proposal– Delay to 2005

• How is linearity defined?– European iTWG to make proposal Review on 2-4-2004 concluded that linearity needs to be extended down to

minimum SRAF size

• Magnification Propose no change at this point due to exposure tool supplier statements

that no change is expected at first node with immersion

o Values for inserted years based on linear interpolation, accurate formulas need to be used

o Fix footnote F. It is contradictory.o Adjust image placement down to 15 nm in 2004 and retain scaling from

there.


39

Proposed Changes to ITRS Lithography Mask Tables (2)

• EUV maskso Re-evaluate MEEF with rigorous EM simulation, including flare

• Propose technology parameter set on prior slide for 32nm node, will increase NA to 0.30 for later nodes

• Redefine parameters as needed based on recent SEMI standards updates

No changes in 2004 but likely to be changes in 2005 to flatness values

o Use rigorous EM simulation to quantify sidewall angle toleranceso Consider mask blank defect specifications based on FWHM and height

of defects at surface of multilayer rather than PSL equivalent substrate defects

o Values for inserted years based on linear interpolation, accurate formulas need to be used

EPL masks Propose to remove table in 2005 due to EPL becoming regional

solution 1X mask tables?

PEL Nanoimprint


40

Calculated MEEF values: 90nm node

Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

LegendELS Equal Lines and Spaces Design APSM Alternating PSMSD Semi Dense Design EPSM Embedded (Attenuated) PSMD Dense DesignIso Isolated Line DesignLW Linewidth

90nmParameters ELS D SD IsoWavelength 193nm 193nm 193nm 193nmNumerical Apeture 0.75 0.75 0.75 0.75Mask Type Cr-CrOx EPSM EPSM EPSMMask Pitch 720nm 855nm 1280nm 2150nmWafer Pitch 180nm 213.75nm 320nm 537.5nmMask Linewidth 360nm 215nm 215nm 215nmWafer Linewidth 90nm 53.75nm 53.75nm 53.75nmIllumination Type Quasar™ Quasar™ Quasar™ Quasar™Outer Sigma 0.8 0.7 0.7 0.7Inner Sigma 0.6 0.1 0.1 0.1Magnification 4 4 4 4MEEF 2.6 3.7 2.9 3.2Linewidth for MEEF 320nm 255nm 255 255nmDOF for Linewidth 1098.44nm 201.234 48.98nm 61.28nm

41

Calculated MEEF values: 90nm node with APSM



90nmParameters ELS D SD IsoWavelength 193nm 193nm 193nm 193nmNumerical Apeture 0.75 0.75 0.75 0.75Mask Type AltPSM AltPSM AltPSM AltPSMMask Pitch 720nm 860nm 1280nm 2150nmWafer Pitch 180nm 215nm 320nm 5375nmMask Linewidth 360nm 215nm 215nm 215nmWafer Linewidth 90nm 53.75nm 53.75nm 53.75nmMaskPhase Width 460nm 735nm 1145nm 2015nmIllumination Type Circular Circular Circular CircularSigma 0.3 0.3 0.3 0.3Magnification 4 4 4 4MEEF 0.8 0.2 0.1 0.2Biased LW for MEEF 400nm 255nm 205nm 225nmDOF for Linewidth 620.313nm 245.953nm 380.42nm 1098nm

42




65nmParameters ELS D SD IsoWavelength 193nm 193nm 193nm 193nmNumerical Apeture 0.93 0.85 0.85 0.85Mask Type Cr-CrOx EPSM EPSM EPSMMask Pitch 520nm 610nm 920nm 1400nmWafer Pitch 130m 152.5 230nm 350nmMask Linewidth 260nm 140nm 140nm 140nmWafer Linewidth 65nm 35nm 35nm 35nmIllumination Type Quasar™ Quasar™ Quasar™ Quasar™Outer Sigma 0.95 0.9 0.9 0.9Inner Sigma 0.7 0.1 0.1 0.1Magnification 4 4 4 4MEEF 4.9 6.0 7.8 5.5Linewidth for MEEF 270nm 180nm 180nm 180nmDOF for Linewidth 635.469nm 39.53nm 14.0625nm 47.95nm

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65nmParameters ELS D SD IsoWavelength 193nm 193nm 193nm 193nmNumerical Apeture 0.93 0.85 0.85 0.85Mask Type AltPSM AltPSM AltPSM AltPSMMask Pitch 520nm 610nm 920nm 1400nmWafer Pitch 130nm 152.5nm 230nm 350nmMask Linewidth 260nm 140nm 140nm 140nmWafer Linewidth 65nm 35nm 35nm 35nmMaskPhase Width 360nm 560nm 840nm 1360nmIllumination Type Circular Circular Circular CircularSigma 0.2 0.2 0.2 0.2Magnification 4 4 4 4MEEF 0.6 0.2 0.1 0.5Biased LW for MEEF 260nm 140nm 160nm 140nmDOF for Linewidth 990.99nm 323.438nm 201.56nm 65.17nm

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45nmParameters ELS D SD IsoWavelength 193nm 193nm 193nm 193nmNumerical Apeture 1.22 1.22 1.22 1.22Mask Type Cr-CrOx EPSM EPSM EPSMMask Pitch 360nm 440nm 660nm 1000nmWafer Pitch 90nm 110nm 165nm 250nmMask Linewidth 180nm 100nm 100nm 100nmWafer Linewidth 45nm 25nm 25nm 25nmIllumination Type Quasar™ Quasar™ Quasar™ Quasar™Outer Sigma 1 0.8 0.8 0.8Inner Sigma 0.8 0.1 0.1 0.1Magnification 4 4 4 4MEEF 2.8 No Value 4.7 4.2Linewidth for MEEF 160nm No Value 140nm 140nmDOF for Linewidth 791.719nm No Value 4.21875nm 1.5625nm

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45nmParameters ELS D SD IsoWavelength 193nm 193nm 193nm 193nmNumerical Apeture 1.22 1.22 1.22 1.22Mask Type AltPSM AltPSM AltPSM AltPSMMask Pitch 360nm 440nm 660nm 1000nmWafer Pitch 90nm 110nm 165nm 250nmMask Linewidth 180nm 100nm 100nm 100nmWafer Linewidth 45nm 25nm 25nm 25nmMaskPhase Width 255nm 440nm 630nm 980nmIllumination Type Circular Circular Circular CircularSigma 0.2 0.2 0.2 0.2Magnification 4 4 4 4MEEF 1.1 0.2 0.1 0.4Biased LW for MEEF 200nm 100nm 140nm 140nmDOF for Linewidth 698.438nm 97.625nm 135.94nm 60.94nm

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32nmParameters ELS D SD IsoWavelength 13.5nm 13.5nm 13.5nm 13.5nmNumerical Apeture 0.25 0.25 0.25 0.25Mask Type EUV EUV EUV EUVMask Pitch 256nm 304nm 456nm 720nmWafer Pitch 64nm 76nm 114nm 180nmMask Linewidth 128nm 72nm 72nm 72nmWafer Linewidth 32nm 18nm 18nm 18nmIllumination Type Circular Circular Circular CircularOuter Sigma 0.7 0.7 0.7 0.7Inner Sigma 0 0 0 0Magnification 4 4 4 4MEEF 1.1 1.2 1.0 1.1Linewidth for MEEF 118nm 62nm 82nm 92nmDOF for Linewidth 466.5nm 137.672nm 126.457nm 121.816nmAngle of Incidence 6 6 6 6

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Simulation Parameters• Used Panoramic Technologies simulator• Focus Plane

– -500nm to +500nm in steps of 100nm– Allows for process windows and Depth of Focus to be

measured

• Mask Linewidth Bias– -50nm to +50nm in steps of 10nm– -40nm to +40nm for 32nm EUV Mask in steps of 10nm– Allows for a reasonable wafer linewidth variance of 2.5nm

• Mask type varied– MoSiON; n=2.489+i0.661; thickness = 65.4nm– 50 nm of Cr with 20 nm of CrOx for absorbers. The complex indices

of refraction for Cr and CrOx were 0.8418+i1.6472 and 1.6364+i0.6502.

– Used etch depth of 172nm, with fused silica index of 1.563.

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Image CD vs Mask CD

82

86

90

94

98

82 86 90 94 98

Mask CD Normalized to Wafer Scale (nm)

Imag

e C

D (

nm

)Determining the MEEF

• 3 pt average CD and slope

Ideal casey = 1x

Actual casey = 2.8125x - 162.96

3 points allow a linear measurement of a nonlinear relationship

49

Parameters for MEEF determination

• Values for 65-nm node agreed upon by subset of the US Lithography Technical Working Group in 2003

• k1 is for MPU half pitch

Intrafield contributors (used to calculate image)ITRS node (nm) 130 90 65 45

minimum MPU half pitch (nm) 160 120 76 55Linewidth with minimum half pitch (nm) 100 70 40 27semi-dense MPU half pitch (nm) 240 180 120 85Exposure wavelength (nm) 248 193 193 193NA 0.8 0.75 0.85 1.22k1 0.52 0.47 0.33 0.351sigma intrafield focus variation (nm) * 45 30 30 251sigma intrafield dose variation (%) * 0.20% 0.20% 0.20% 0.50%Minimum focus error, fmin (nm) 0 0 0 0

Maximum focus error, fmax (nm) 100 100 50 25Mean aberration level (waves rms) 0.02 0.014 0.014 0.014Binary and embedded PSM masksInner sigma 0.55 0.55 0.55 0.55Outer sigma 0.85 0.85 0.85 0.85alt PSM sigma 0.4 0.4 0.3 0.3Flare** 2% 2% 2% 4%* Gaussian distribution** Flare is doubled for altPSM; assume 25% average pattern density

50

MEEF simulation assumptions for 32nm nodeIntrafield contributors (used to calculate image)

Technology parameters193nm immersion EUV

minimum MPU half pitch (nm) 45 45Linewidth with minimum half pitch (nm) 40 40Exposure wavelength (nm) 193 13.5NA 1.34 0.251sigma intrafield focus variation (nm) * 25 251sigma intrafield dose variation (%) * 0.75% 1.05%Minimum mean focus error, fmin (nm) 0 0

Maximum mean focus error, fmax (nm) 50 50Mean aberration level (waves rms) *** 0.045 0.045Aberration variation within field 0% 0%Sigma 0.3 0.7Bias on isolated lines (nm at 1X) -10 -1Flare** 4% 10%Flare variation (1sigma) 0% 1%Mask CD control (nm 3sigma) 1.8 1.3* Gaussian distribution** Assume 25% average pattern density

1 2004 winter itrs conference lithography international technical working group

Documents

larger cd

metrology twg

cd bias

wafer cd metrology

total cd control

cd control targets

changes slide

range slide