1 clemson ece laboratories ece 311 – electronics lab i pre-labs for ece 311 created by steven...

1Clemson ECE Laboratories

ECE 311 – Electronics Lab I

Pre-labs for ECE 311

Created by Steven Chambers in Fall 2012

Last Updated: 12/20/2012


LABORATORY 0 – LABORATORY DEMONSTRATION


Introduction to Laboratory 0

• Curve Tracer– Plots I-V curve for two and three terminal devices – Can plot a family of curves for different bias

conditions– Used in this lab to give characteristics of diodes

and transistors– Current/Voltage/Power limitations used to prevent

destruction of device under test (DUT)


Background Information

• Bipolar Junction Transistor (BJT)– Three terminal device (Emitter, Base, Collector)– Base current controls Collector-Emitter current– I-V curve

• Y-axis: IC

• X-axis: VCE

• Family of curvesrepresents differentIB values

• As IB increases,IC increases for the same VCE value


Contact Information

• Instructor:

Name:

Email:

Office:

Phone:

Office Hours: As needed (email for appointment)

• Lab Coordinator:

Name: Dr. Timothy Burg

Email: [email protected]

Office: 307 Fluor Daniel (EIB)

Phone: (864)-656-1368


Mandatory Safety Video


Preparations for Next Week

• B2SPICE– Circuit simulation software– Uses computer models to predict circuit behavior– All parts used are considered ideal

• Observed value will differ from simulated value, but still good estimation

– Tests most often used in this lab are DC Sweep, Transient testing, and frequency sweep

– DC Sweep used for both simulations of next weeks lab


Preparations for Next Week

• For Part 2: Click Sweeps tab under DC Sweep

• Then click Set up Sweeps

The dialogue to the right willappear.Use thesesettings to properly sweep the Rfrom 100 to1000 to 10k ohms.


LABORATORY 1 – DIODE CHARACTERISTIC


Introduction to Lab 1

• Diode – Allows current to flow inone direction under forward bias

• rd – dynamic forward resistancerd = ΔVD/ ΔID (reciprocal of I-V slope)

• RD – static forward resistance RD = VD/ID

• Vγ – cut-in voltagepoint where appreciable current conduction begins

• n – ideality factordependent upon physical characteristics of diodes

• VBR – breakdown voltage

• IS – reverse saturation currentcurrent that flows under reverse bias

• VT – thermal voltage = 0.0285V at room temperature

ID

- VD +


Diode Characteristic

• Part 1A will replicate forward bias on curve tracer • Part 1B will replicate reverse bias on a Zener diode

– Zener diodes have a lower VBR because they are designed to keep a constant voltage drop across it


Ideality Factor

• “The ideality factor, n, depends on the type of semiconductor material used in the diode, the manufacturing process, the forward voltage, and the temperature.”

• Its value generally varies between 1 and 2. For voltages less than about 0.5 V, n ~ 2; for higher voltages, n ~ 1. (experiment shows values typically 1.15 ≤ n ≤ 1.2)

• The ideality factor, n, can readily be found by plotting the diode forward current on a logarithmic axis vs. the diode voltage on a linear axis.


Finding Ideality factor, n

Pick two pointswhere currents are 10 times different

Find = ?

∆𝑉 𝐷=2.3 ×𝑛×𝑉 𝑇=2.3 ×𝑛× 0.0258=0.0593𝑛=𝑛×59 .3𝑚𝑉

𝒏=∆𝑽 𝑫

𝟓𝟗 .𝟑𝒎𝑽


Cut-in Voltage Vγ:

0.4V to 0.7V for silicon0.2V to 0.4V for germanium

“If the applied voltage exceeds Vγ, the diode current increases rapidly.”


Diode Resistance

Three diode resistances are commonly calculated:

• DC or Static forward resistance, RF or RD

• AC or Dynamic forward resistance, rf or rd

• Reverse resistance, rr

– the reciprocal of the slope of the reverse characteristic, prior to breakdown

Applying the diode equation and differentiating


Junction Capacitance of Diode ( Cj )


Experiment: Measurement of diode characteristics

• Forward I-V Characteristic– Use the curve tracer to obtain the forward

characteristics of the silicon 1N4004 diode.

– follow the steps mentioned in lab manual for selecting Vmax =2V, Imax = 2mA and Pmax =0.4W

– Fill out table 1.1 and perform calculations to find RF and rd


Reverse I-V Characteristic

• Use Zener diode (this one looks transparent)– Note the reverse breakdown voltage

(around -14.6V)


SIMPLE DIODE CIRCUIT

Build the circuit

Measure the output voltage, V0

Vary the Vin from 0V to 5V for R= 100Ω change R = 1k Ω and 10k Ω

Fill out table 1.2


Preparations for Next Lab

• Post Lab 1– All questions under Lab Report section (Part 1 and

Part 2) should be answered• Pre Lab 2

– Figures 2.3 and 2.5 will be simulated– Use a sinusoidal voltage source set to 60 Hz and 4

volt amplitude (8 V peak to peak)– Run transient test for 4 periods (f = 60 Hz T = 1/f

start time = 0)


LABORATORY 2 – POWER SUPPLY OPERATION


Half-wave Rectifier

• Diode forward biased for Vin > Vγ

• Diode reverse biased for Vin < Vγ

• Allows current to conduct for roughly half of AC cycle

• Vm = Vp - Vγ


Full-wave Rectifier

• D2 and D3 forward biased when Vin > 2Vγ

• D1 and D4 forward biased when Vin < 2Vγ

• Vm = Vp – 2Vγ

• Output frequency is twice that of input• Output does not share common ground with input


Filtering

• Adding a capacitor in parallel with load resistor creates a filter

• Capacitor will charge up on first half of cycle then discharge slowly based on capacitance

• This creates a voltage source with ripple

• Vr = Vm – Vmin



• Post Lab 2– 3 questions under Lab Report

• Pre Lab 3 – First Design Lab– I will split the class. Half the class will come for

the first hour. Other half will come for the second.– Bring your design calculations with you to lab– Please print ECE 311 – Lab 3 Lab Summary page

from lab manual and bring with you to next lab. This will be turned in as your post lab prior to leaving lab next week.


LABORATORY 3 – POWER SUPPLY DESIGN


Power Supply Design Calculations

• This lab is to be completed individually

• Remember Vin is measured after the source resistor Rs

• Fill out Lab Summary sheet and turn in before your leave



• Pre Lab 4

– Simulate circuits 4.5(a) (Vb = 0 and 2 V), 4.6(a) (Vb = 0 and 2 V), 4.7, and 4.8

– There is an error in the prelab statement. DO NOT SIMULATE FIGURE 4.4(a).

• Lab Report: You are to complete a formal lab report on your choice of Lab 1-3. You have 2 weeks to complete the report. It is to be submitted electronically before 5 PM on 10/9.– Follow report format in the lab manual and look to

the rubric uploaded on blackboard to see how it will be graded


LABORATORY 4 – DIODE CLIPPERS AND CLAMPERS


Clipper

• Circuit that limits the output voltage to either an upper or lower limit (or both) through the use of diodes and voltage sources

• Diode begins conducting and holds output to a desired level (V + Vγ in the configuration seen below)

• Diode and battery orientation determine whether circuit is positive or negative clipper


Clamper

• Circuit that shifts the DC value of an input voltage through the use of a diode and capacitor

• Diode conducts on negative half cycle to allow capacitor to charge

• Once charged, capacitor passes AC signal shifted by the charge built on C

• Diode polarity determines positive or negative clamping (positive pictured below)

• RC time constant must be much larger than input signal period


Note on circuit connection

• The NI-Elvis VPS is internally grounded• This means no physical wire connection on your

board is required to ground the voltage source

• For Vb = 0, connect diode straight to ground

• For non-zero Vb, connect diode to VPS supply + or supply -

Connection already madewithin NI-Elvis board




• Pre Lab 5 – Be familiar with BJT transistor operation and read

through lab• I do not require you to bring in graph paper• Remember: Lab report due next week


LABORATORY 5 – BIPOLAR JUNCTION TRANSISTOR CHARACTERISTICS


Bipolar Junction Transistor

• Three terminal device: Collector, Emitter, Base• Collect-Emitter current controlled by B-E current• Four regions of operation NPN (PNP):

– Cutoff – Both P-N Junctions reverse biased– Saturation – Both P-N Junctions forward biased– Forward Active – B-E (B-C)

forward biased, B-C (B-E)reverse biased

– Inverse Active – B-E (B-C) reverse biased, B-C (B-E)forward biased N P N P N P


Output Characteristic

Cutoff

Forward Active

Saturation


Transistor Parameters

• hFE = IC/IB = β – dc current gain

• hfe = ΔIC/ΔIB = βo – small signal (ac) current gain

• hie = ΔVBE/ΔIB = rπ – input resistance

• hoe = ΔIC/ΔVCE – output conductance

• hre = ΔVBE/ΔVCE – voltage feedback ratio

• hie can be approximated from βVT/ICQ

• VA – Early Voltage



• Post Lab 5 – 6 questions under Lab Report

• Pre Lab 6 – Figure 6.2 DC Sweep to find Q point– Figure 6.1 Transient analysis for various R– Use transient setup given in pre lab

• Remember: Electronic copy of lab report due tonight by 5 pm


LABORATORY 6 – BJT COMMON-EMITTER CIRCUIT BIAS


Common Emitter Bias Circuit

• Emitter is used as a reference point for both input and output

• R1 and R2 form a bias network to set a desired base current

• RC used to set output voltage levels

• RE helps reduce circuitvariation with β but also reduces AC voltage gain


Q-Point

• Bias circuit is used to select an operating (Q) point• Q point should be well into the forward active region

to get a properly behaving amplifier circuit• When adding a small signal AC voltage, the output

voltage will shift with the AC input based on gain• If the Q point is too close to saturation or cutoff,

output waveform will distort and circuit will not behave as a proper amplifier


Common Emitter Amplifier

• AC input signal can be added to base terminal (C1 used to filter out any DC component)

• VO is takes from collector terminal to ground (C2 once again used to remove DC component)

• CE added to increase AC gain; Emitter isshorted to groundfor AC – We will explore this morenext week in Lab 7




• Pre Lab 7 – Simulate circuit 7.1 for the 10 different

configurations given in the lab manual


LABORATORY 7 – BJT COMMON-EMITTER CIRCUIT VOLTAGE GAIN


Common Emitter Amplifier

• Once Q point is established, small AC signal can be added to base

• This signal is amplified and seen at the collector terminal


Hybrid-π Equivalent Circuit

• Used to model BJT response to small signal AC input

• gm = ICQ/VT

• Ro = VA/ICQ

• Rπ = β/gm

• When applied to overall circuit, can provide small signal voltage gain from input vs output transfer function


Effect of Emitter Capacitor

• With CE:

• Without CE:

• With CE, two sides of circuit only share a common ground; without CE, RE adds a feedback loop which produces a voltage divider, reducing Vπ and the gain


Frequency Response

• Capacitors in this circuit have been selected so they essentially provide 0 impedance at circuit operating frequency.

• As frequency is changed, the capacitors start to produce an appreciable impedance; thus, lowering the gain of the circuit.



• Post Lab 7– 4 Questions under Lab Report

• Pre Lab 8– 2 Hour group design lab – Each student should

read through and do design calculations individually and perform simulations

• Lab Report 2: Due 11/13 by 5:00 PM, electronic submission– Pick from Labs 4-7


LABORATORY 8 – BJT COMMON EMITTER DESIGN I


Equivalent Circuit

• RO ignored

• Mesh analysisprovides Av

• Design Calculations:– hib + RE = 235 Ω

– Rac = 2.585k Ω

– Rdc = 4.935k Ω

– ICQ = 1.33 mA

– VCEQ = 3.438 V

– VBB = 1.014 V

– β = 200

– IBQ = 6.649 µA

– hie = 3.91k Ω

– hib = 19.55 Ω

– RE = 215 Ω

– R2 = 4.785k Ω

– R1 = 42.386k Ω



• Post Lab 8: 2 Questions under Lab Report– Do not do a full report for question 1. Simply

provide me the design calculations, results, and comparison.

• Pre Lab 9: Individual Design Lab – Bring calculations with you to next lab– Print Lab Summary to turn in as Post Lab 9


LABORATORY 9 – BJT COMMON EMITTER DESIGN II


Equivalent Circuit

• Ro ignored

• Mesh analysis

• Vπ = Vs

• Vo = -(RC//RL)gmVπ

• Av = -(RC//RL)gm

• gm = ICQ/VT

• When RC = RL, Av = -RCICQ/2VT


Design Calculations

• Rac = 2.35k Ω

• ICQ = 1.277 mA

• VCEQ = 3V

• VBB = 1.014 V

• β = 200

• IBQ = 6.649 A

• hie = 4.073k Ω

• hib = 20.37 Ω

• Rdc = 5.797k Ω

• RE = 1.097k Ω

• R2 = 28.26k Ω

• R1 = 97.92k Ω



• Post Lab 9 is to be turned in before you leave today• Pre Lab 10

– Read through the lab and be familiar with FET operation


LABORATORY 10 – FIELD EFFECT TRANSISTORS


JFET Operation

• N-Channel JFET– P-type gates – N-type channel with ohmic contacts at both ends– P-Channel switches doping type positions

• Current flow is controlled by gate bias– VGS = 0 – Depletion regions exist between

reverse biased p-n junctions, but a channel of n-type material allows current flow from drain to source

– VGS << 0 – Depletion region extends completely across n-type region cutting off current flow

gate


JFET Equations

• Linear Region

– IDS = Kn [2(VGS – VP) VDS – VDS2]

– Where Kn = IDSS/VP2

– IDSS – 0 Voltage current VP – pinchoff voltage

• Saturation Region

– IDS = Kn(VGS(Sat))2




• Pre Lab 11 – Simulate Figure 11.6


LABORATORY 11 – FET BIAS AND AMPLIFICATION


JFET Amplifier

• Similar circuit layout to BJT amplifier circuits– Common-drain analogous to Common-emitter– Common-source analogous to Common-collector

• Voltage controlled device with negligible current draw into gate– Only reverse saturation current of p-n junctions

will flow

Common-drain

Common-source


JFET Small Signal AC Model

• gm = ΔID/ΔVGS

• rd = dVDS/dID

• Amplification

– μ = gmrd

• When applied to common-drain circuit:

• If RS = 0 or bypassed

– Av = gm(rd||RD)




• Pre Lab 12– Be familiar with logic gate operation– Simulate both CMOS inverter and NAND gate


LABORATORY 12 – BASIC LOGIC CIRCUITS


CMOS Logic

• Complementary Metal Oxide Semiconductor (CMOS)– Utilizes both pMOS and nMOS transistors

• Currently the most widely used technology for logic gates

• CMOS has helped push speeds faster and sizes smaller due to the ever improving transistor technology that allows lower voltage operation and smaller gate sizes


CMOS Inverter

• pMOS transistor source tied to VCC

• nMOS transistor sourcetied to GND

• Both gates tied together and used as input

• Both drains tied together and used as output

• When In = 5 V: pMOS off, nMOS on, Out grounded• When In = 0 V: pMOS on, nMOS off, Out tied to +5


Slew Rate

• Slew rate refers to the rate at which signalsrise and fall

• Rise and fall timesdetermine how fast a circuit can operate (maximum operating frequency)

• Real signals do not instantaneously switch from high to low

• Transition times can lead to circuit glitches or missed data


The End!

• Enjoy the rest of your semester

1 clemson ece laboratories ece 311 – electronics lab i pre-labs for ece 311 created by steven...

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