1 ece 556 design automation of digital systems by prof. charlie chung-ping chen ece department...
TRANSCRIPT
![Page 1: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/1.jpg)
11
ECE 556 Design Automation of Digital Systems
ECE 556 Design Automation of Digital Systems
ByBy
Prof. Charlie Chung-Ping ChenProf. Charlie Chung-Ping Chen
ECE Department ECE Department
UW-MadisonUW-Madison
![Page 2: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/2.jpg)
22
Outline
Microprocessor Technology Trends and Design Microprocessor Technology Trends and Design IssuesIssues
Interconnect delay trendsInterconnect delay trends Circuit type trendsCircuit type trends Research summaryResearch summary
![Page 3: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/3.jpg)
33
Microprocessor Design Challenges
High performance ( > 500 Mhz)High performance ( > 500 Mhz) Low cost (< $100)Low cost (< $100) Low power consumption (< 10W mobile)Low power consumption (< 10W mobile) More functionality (KNI MMX)More functionality (KNI MMX) Shorter time to market (< 18 months)Shorter time to market (< 18 months) Satisfies different market segments (server, sub-$1000)Satisfies different market segments (server, sub-$1000) CompetitionCompetition ……..
Mission Impossible!
Mission Impossible!
![Page 4: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/4.jpg)
44
Tentative Class Schedule
Technology Trends (1 class)Technology Trends (1 class) Interconnect Modeling and Optimization: (1 week)Interconnect Modeling and Optimization: (1 week)
basic routing: maze-routingbasic routing: maze-routing wire-sizing, buffer-sizing, buffer-insertionwire-sizing, buffer-sizing, buffer-insertion
Introduction to Verilog (1 week)Introduction to Verilog (1 week) Linear programming and Introduction to C and C++ language (1 week)Linear programming and Introduction to C and C++ language (1 week) Routing: (2 week)Routing: (2 week)
Clock routing (0.6 week)Clock routing (0.6 week) Global and channel routing, Tree routing (1.4 week)Global and channel routing, Tree routing (1.4 week)
Timing Analysis (1 week)Timing Analysis (1 week) Delay Characterization, Power CharacterizationDelay Characterization, Power Characterization PERL and Latch based timing analysis PERL and Latch based timing analysis
Partitioning and Placement (1.5 week)Partitioning and Placement (1.5 week) Floorplanning (1 week)Floorplanning (1 week)
![Page 5: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/5.jpg)
55
Deal With It!
Higher clock frequencies Higher clock frequencies New processes: 0.18 micron, copperNew processes: 0.18 micron, copper Architecture levelArchitecture level
Superscalar, super-pipeline, out-of-order execution, speculative execution, Superscalar, super-pipeline, out-of-order execution, speculative execution, EPIC, VLIW, ILP, multi-threadEPIC, VLIW, ILP, multi-thread
Circuit levelCircuit level Aggressive dynamic circuits synthesisAggressive dynamic circuits synthesis Sizing, parallel re-powering, logic minimizationSizing, parallel re-powering, logic minimization
Physical DesignPhysical Design Performance-driven place and route, floorplaningPerformance-driven place and route, floorplaning Wire-sizing, buffer-sizing, buffer-insertionWire-sizing, buffer-sizing, buffer-insertion
![Page 6: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/6.jpg)
66
![Page 7: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/7.jpg)
77
![Page 8: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/8.jpg)
88
![Page 9: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/9.jpg)
99
![Page 10: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/10.jpg)
1010
![Page 11: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/11.jpg)
1111
![Page 12: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/12.jpg)
1212
Size of Team ExplodesSize of Team Explodes
![Page 13: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/13.jpg)
1313
![Page 14: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/14.jpg)
1414
Process Overview
New process (0.18 um)New process (0.18 um) High aspect ratioHigh aspect ratio Low sheet rho (resistance)Low sheet rho (resistance) Low-Low- dielectric (capacitance) (3.55 vs. 4.10) dielectric (capacitance) (3.55 vs. 4.10) Good Electromigration propertyGood Electromigration property 6 metal layers 6 metal layers
M1 tight pitch for density (X-cap)M1 tight pitch for density (X-cap) M2-M3 middle pitch for density & performance (X-cap)M2-M3 middle pitch for density & performance (X-cap) M4-M6 high pitch (low resistance) for performance (Inductance)M4-M6 high pitch (low resistance) for performance (Inductance)
FutureFuture Copper - Less resistance more inductance effectCopper - Less resistance more inductance effect SOI - the M1 coupling strangeSOI - the M1 coupling strange
![Page 15: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/15.jpg)
1515
0.25 Micron, 5 Layer Technology0.25 Micron, 5 Layer Technology
IEDM 96IEDM 96
![Page 16: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/16.jpg)
1616
M6
M5
M4
M3
M2
M1
0.18 Micron, 6 Layer Technology0.18 Micron, 6 Layer Technology
IEDM 99IEDM 99
![Page 17: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/17.jpg)
1717
5
10
15
20
25
120 130 140 150 160 170 180 190 200LGATE (nm)
Ga
te D
ela
y (
pse
c)
Vdd = 1.5V
Vdd = 1.3V
Gate Delay .v.s. ScalingGate Delay .v.s. Scaling
IEDM 99IEDM 99
![Page 18: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/18.jpg)
1818
0
20
40
60
80
100
120
0.0 0.5 1.0 1.5 2.0 2.5 3.0Pitch (m)
Sheet R
ho (
mohm
/sq) Al, 0.25um, ref [6]
Al, 0.18um, this workCu, 0.22um, ref [7]
Interconnect Resistance Grows Super LinearlyInterconnect Resistance Grows Super Linearly
IEDM 99IEDM 99
![Page 19: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/19.jpg)
1919
Interconnect Delay Trend
IEDM 99IEDM 99
![Page 20: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/20.jpg)
2020
![Page 21: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/21.jpg)
2121
![Page 22: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/22.jpg)
2222
![Page 23: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/23.jpg)
2323
Interconnect Complicated Design Flow
ArchitectureArchitecture
RTLRTL
LogicLogic
GateGate
LayoutLayout
Over tens of Over tens of iterations!iterations!
![Page 24: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/24.jpg)
2424
Signal Integrity A new design challenge
CrossCapCrossCap
1
2
CrosstalkCrosstalk
![Page 25: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/25.jpg)
2525
Inductance effect emerging
An old clock treeAn old clock tree Freq domain up to 1GhzFreq domain up to 1Ghz PVL and PRIMA with order PVL and PRIMA with order
16 find the exact16 find the exact
A newer ckt, a section of A newer ckt, a section of power gridpower grid Has L’sHas L’s PVL and PRIMA with 60th PVL and PRIMA with 60th
orderorder Frequencies more than 0.6 Frequencies more than 0.6
Ghz are not coveredGhz are not covered
Frequency (Ghz)
0 0.5 1 1.5 2-3
PRIMA
PVL|H(jw)|
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
|H(jw)|
PRIMA=PVL=EXACT
EXACT
![Page 26: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/26.jpg)
2626
70 72 74 76 78 80-550
-500
-450
-400
Multi-Point PRIMA-34
PRIMA-80
TIM
PVL-80
Some MOR result
![Page 27: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/27.jpg)
2727
![Page 28: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/28.jpg)
2828
![Page 29: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/29.jpg)
2929
Model order reduction
We need We need efficient toolsefficient tools to analyze the interconnect to analyze the interconnect dominant circuits (power grids, packages etc.) accurately dominant circuits (power grids, packages etc.) accurately in a reasonable amount of timein a reasonable amount of time
Promising Promising Model Order ReductionModel Order Reduction (MOR) techniques (MOR) techniques
Nonlinear Elements
Linear Elements
Nonlinear Elements
Reduced Model
![Page 30: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/30.jpg)
3030
Power ConsumptionPower Consumption
P P C V C V22 f, where f, whereC = Capacitance ~ AreaC = Capacitance ~ AreaV = Supply VoltageV = Supply Voltagef = Operation Frequencyf = Operation Frequency
![Page 31: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/31.jpg)
3131
Power TrendPower Trend
![Page 32: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/32.jpg)
3232
Supply Voltage TrendsSupply Voltage Trends
![Page 33: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/33.jpg)
3333
Deal With It!
InterconnectInterconnect Wire- and Repeater- SizingWire- and Repeater- Sizing Repeater InsertionRepeater Insertion Performance-driven noise-aware routingPerformance-driven noise-aware routing New material: Low resistance (Cooper), Low k material (SiN2) New material: Low resistance (Cooper), Low k material (SiN2)
GatesGates Gate SizingGate Sizing New Circuit Exploration - Dynamic Circuit, Dual VtNew Circuit Exploration - Dynamic Circuit, Dual Vt
……..
![Page 34: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/34.jpg)
3434
Standby Power TrendStandby Power Trend
![Page 35: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/35.jpg)
3535
Threshold Voltage v.s. Supply VoltageThreshold Voltage v.s. Supply Voltage
![Page 36: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/36.jpg)
3636
Vt v.s. Delay
![Page 37: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/37.jpg)
3737
Dual Vt circuitDual Vt circuit
High VtHigh Vt
Low VtLow Vt
![Page 38: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/38.jpg)
3838
Aggressive circuit styles Aggressive circuit styles
![Page 39: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/39.jpg)
3939
Clock delayed and Self-resetting dynamic circuitsClock delayed and Self-resetting dynamic circuits
![Page 40: 1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison](https://reader035.vdocument.in/reader035/viewer/2022081515/56649ee15503460f94bf1175/html5/thumbnails/40.jpg)
4040
Process limitations