1 elec 516 vlsi system design and design automation spring 2010 lecture 2 hardware modeling note:...
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ELEC 516 VLSI System Design and Design Automation
Spring 2010Lecture 2 Hardware Modeling
Note: some of the figures in this slide set are adapted from the slide setof “ Modern VLSI Design” by Wolf, Copyright Pentice Hall 2002
ELEC516/10 Lecture 22
Why do we need HDLs?
A specification is an engineering contract that includes not only functionality but also performance.
Top-down design: Partition the project into modules with well-defined specifications and interfaces, so that partition of tasks can be performed effectively.
A Behavioral model serves as a description of all the specifications of the project and document the function of all individual blocks and their interfaces.
In large digital designs: We need to talk about what hardware is required without actually designing the hardware itself: We need a Hardware Description Language HDL.
If we are able to Synthesize the hardware from the behavioral model, the target will be met.
ELEC516/10 Lecture 23
Hardware description languages
Textual languages for describing hardware: Behavior
the functional interpretation of a particular system. structure;
Most people today use textual languages rather than schematics for most digital design. Schematics make poor use of screen space.
Two major HDLs designed for simulation: VHDL; Verilog. Similar capabilities but somewhat different
language philosophies. EDIF - a standard netlist format
ELEC516/10 Lecture 24
HDL - Simulation Oriented
Difference between HDL and conventional software programming language: Notion of simulation Simulation tags computations with times.
Must know when signals change to properly simulate hardware.
Simulation is parallel.Many statements can execute at the same
(simulation) time.Just like hardware.
ELEC516/10 Lecture 25
Advantages for Digital Design
Portability Modeling capability (several levels) Technology and foundry independence Reusability Early verification/simulation of functionality
ELEC516/10 Lecture 26
Behavioral modeling
Combinational logic circuits can be described by a set of ports (inputs/outputs) and a set of equations that relate variables to logic expressions
describes the functional relationship between inputs and outputs. Similar to programming but values are
events. The circuit can be seen as an interconnection of
operators, each operator evaluates a logic function. These models differ from structural models in that
there is not a one-to-one correspondence between expressions and logic gates, because for some expressions there may not exist a single gate implementing it.
Behavioral Hardware Modeling
ELEC516/10 Lecture 27
A half-adder circuit example
architecture BEHAVIOR of HALF_ADDER is
process
begin
carry <= (a and b);
sum <= (a xor b);
end process;
end BEHAVIOR;
Behavioral Hardware Modeling
ELEC516/10 Lecture 28
Simple Example
ELEC516/10 Lecture 29
Structural Hardware Languages
Describe an interconnection of components.
Expressive power is similar to that of circuit schematics.
Hierarchy is often used to make the description modular and compact.
The basic features of structural languages place them close to the declarative class, even though some structural languages have also procedural features.
ELEC516/10 Lecture 210
Example1: half-adder in VHDLarchitecture STRUCTURE of
HALF_ADDER is component AND2
port (x, y: in bit; o: out bit); component EXOR2
port (x, y: in bit; o: out bit);begin G1: AND2b
port map (a, b, carry); G2: EXOR2
port map (a, b, sum);end STRUCTURE;
x
y
o x
y
o
ab
sum
carry
ELEC516/10 Lecture 211
Example2: A Language for Describing netlists
describe a digital system by its netlist; specifies primitive gate types and their rise and fall
delay
g2
g3
g4
g1g5
g6
abc
s
co
w1
w2
w3
w4
CCT full_adder(a,b,c,s,co)XOR(Rise=16,Fall=12) g1(w1,a,b), g5(s,w1,c);AND(Rise=12,Fall=10) g2(w2,c,b), g3(w3,c,a), g4(w4,b,a);OR(Rise=12, Fall=10) g6(co,w2,w3,w4);INPUT a,b,c;WIRE w1,w2,w3,w4;OUTPUT s,coENDCIRCUIT full_adder
ELEC516/10 Lecture 212
3rd Example: SPICE netlist
* net 1 = vdd! * net 0 = gnd! * net 2 = /p6 * net 3 = /g4 * net 4 = /Y<0> * net 5 = /A<10> * net 6 = /p7 * net 7 = /g5 * net 8 =
/Sum<1> * net 9 = /X<4> * net 10 = /g6 * net 11 = /p8 * net 12 = /A<7> * net 13 = /p9
.model model4 nmos level=3 vto=0.7459+nsub=4.547e+16 kp=0.00011169 lambda=+vmax=190000 xj=1.7e-07 ld=4.157e-08 +cgbo=3.8876e-10 cgdo=3.9e-10 cgso=3.+cj=0.00026613 cjsw=5.3766e-10 mj=1.0+rsh=14.19 delta=0.8197 kappa=0.07784* nmos_hp08(0) = /I81/N3m0 82 103 0 0 model4 w=11.2u l=0.8u* nmos_hp08(1) = /I81/N2m1 103 21 0 0 model4 w=8.4u l=0.8u.model model5 pmos level=3 vto=-0.874+nsub=2.659e+16 kp=3.0474e-05 lambda=+vmax=212900 xj=2e-07 ld=9.903e-10 th+cgdo=3.9e-10 cgso=3.9e-10 tox=1.77e-+cjsw=1.7481e-10 mj=0.5159 mjsw=0.258+delta=0.8062 kappa=0.01 eta=0.02551* pmos_hp08(2) = /I81/P1m2 1 103 82 1 model5 w=20.4u l=0.8u* pmos_hp08(3) = /I81/P0m3 1 21 103 1 model5 w=8.4u l=0.8u
ELEC516/10 Lecture 213
Testbench
A testbench is a model used to exercise a simulation. Provides stimulus. Checks outputs.
Testbenches help automate design verification. Rerun edited module against testbench. Run models at behavioral, RTL levels
against the same testbench.
ELEC516/10 Lecture 214
Example of using test bench Test bench - top level entity to test the other entity. The test bench must contain the circuit under test and
should have sources for providing data to its input
Entity TEST_BENCH is end TEST_BENCH;use WORK.all;architecture ONES_CNT1 of TEST_BENCH is signal A: BIT_VECTOR(2 downto
0); signal C: BIT_VECTOR(1
downto 0); component ONES_CNTA port(A: in BIT_VECTOR(2
downto 0);C: out NIT_VECTOR(1 downto 0));
end component; for L1: ONES_CNTA use entity
ONES_CNT(ALG)
begin L1: ONES_CNTA
port map(A,C); process begin
A<= “000” after 1 ns,“001” after 1 ns,“010” after 1 ns,“011” after 1 ns,“100” after 1 ns,“101” after 1 ns,“110” after 1 ns,“111” after 1 ns;
wait;end process;end ONES_CNT1;
ELEC516/10 Lecture 215
Synthesizable code vs. simulatable code
VHDL and Verilog were designed for simulation. A synthesis subset is:
synthesizable; produces consistent simulation results.
Different tools may use different synthesis subsets.
Register-Transfer synthesis Most common type of synthesis. Synthesizes gates from abstract RT model.
Registers are explicit.Some tools will infer storage elements---be
careful. Optimized for performance, area, power.
ELEC516/10 Lecture 216
Abstract Models
represent different circuit views at the logic and architectural levels so that it can be manipulated inside the computer.
Structural Models Model as a netlist: A netlist enumerates all nets of a
given module (module-oriented netlist) or all modules of a given net (net-oriented netlist)
m1: n1, n2, n3m2: n1, n2m3: n2, n3
m2
m1m3
n1
n2
n3
p1
p2
p4
p6
p3
p5p7
ELEC516/10 Lecture 217
State Diagrams
Sequential circuits at the logic level can be described by a finite-state machine transition diagrams which has A set of primary input patterns X A set of primary output patterns Y, A set of states S, A state transition function d: X*S->S, An output function l: X*S->Y for Mealy models or l: X-
>S for Moore models An initial state.
The state transition diagram is a labeled directed multi-graph Gt(V,E) where the vertex set V is in one-to-one correspondence with the state set S and the directed edge set E is in one-to-one correspondence with the transitions specified by d.
ELEC516/10 Lecture 218
An example of a state transition diagram
S0
S1 S2
S3
r/0
a’b’+r/0
r/0
a’b’r/0
b’r’/0
br’/1
r’/1
ar’/1
a’r’/0abr’/1 r/0
a’br’/0
ELEC516/10 Lecture 219
Data Flow Graph Abstract models of behavior at the architectural level
are in terms of operations and their dependencies. Several different Dependencies
data dependency serialization constraints in the specification. A task
may have to follow a second one. Example: loading data on a bus and then raising a flag.
dependency due to resource conflict: two tasks share the same resource (operator)
Data flow graphs represent operations and data dependencies. Let the number of operations be nops. A data flow graph Gd(V,E) is a directed graph whose vertex set V = {vi; i = 1,2,...,nops} is a one-to-one correspondence with the set of tasks.
ELEC516/10 Lecture 220
Examples of a dataflow graph
xl = x + dx;
ul = u - (3*x *u *dx) - (3 * y * dx);
yl = y + u * dx;
c = xl < a;
ELEC516/10 Lecture 221
VHDL register transfer level modeling
VHDL - usable for design documentation, high-level design, simulation, synthesis and testing of hardware, as well as a driver for a physical design tool
Combines a general-purpose programming language and an HDL. Modeled on Ada programming language.
VHDL is a rich language: concurrent language hierarchical modules; abstract data types.
ELEC516/10 Lecture 222
System Level Modeling
Modern SoC well contains Multiple processor cores, MCUs or DSPs or
specialized media processors On-chip memory Accelerating hardware units for dedicated
functions Peripheral control devices Complex on-chip communication networks and
protocol Software components on the processor core and
protocol, hardware components for accelerator. Need modeling language beyond RT level abstraction used
with the old HDLs. To specify, design, and implement complex
system , incorporating functionality implemented in both hardware and software forms.
ELEC516/10 Lecture 223
Requirement of system modeling language
Specification and design at various levels of abstraction
Incorporation of embedded software portion of a complex system, both models and implementation-level code
Creation of executable specification of design intent
Creation of executable platform models Fast simulation speed Constructs allowing separation of system function
from system communications, in order to allow flexible adaptation and reuse of both model and implementation
ELEC516/10 Lecture 224
SystemC – a system modeling and design language
Object-oriented language base allow for modeling flexibility and facilitate reuse
To facilitate reuse, the following are incorporated in SystemC Functionality and interface definition are
separated Abstract and concrete data-types and ports Interface attributes A transaction/messaging concept
ELEC516/10 Lecture 225
SystemC language architecture