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Engineering issues for FPCCD VTX Detector

Y. Sugimoto

KEK

July 24, 2007

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FPCCD 5m pixel size, 15m epi-l

ayer Accumulate signal during a

train and read out between trains Moderate readout speed ~

10Mpix/s No power cycling

Two wafers make a doublet, and three doublets make the detector

Operate at low temperature ~220K ladders are put inside a cryostat

5m

p- epitaxial layer

p++ substrate

n channel

5065

100

15

80

CCD

R-Z ViewLayer R (mm)

1 20

2 22

3 32

4 34

5 48

6 50

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Readout channels

One readout channel covers 128x13000(L1-L2)/128x20000(L3-L6) pixels

For outer layers, larger pixel size may be acceptable and could be 128x13000

Wafer size (mm2) r.o. ch/wafer # of wafers # of r.o. channels

L1 10x65 16 15()x2(z) 480

L2 10x65 16 15()x2(z) 480

L3 20x100 32 16()x2(z) 1024

L4 20x100 32 16()x2(z) 1024

L5 20x100 32 24()x2(z) 1536

L6 20x100 32 24()x2(z) 1536

Total 220 6080

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Engineering challenge

Power consumption and cooling method Wafer thinning and the ladder design Installation method …. …. ….

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Power consumption Heat source

Ohmic loss in gate electrode (probably negligible)

CCD source follower and load resister

Readout ASIC Clock driver

CCD and ASIC must be inside the cryostat

Clock driver may be put outside the cryostat

Most of power is consumed by “drivers”

No heat source in the image area

Our R&D goal: Electronics: < 100 W in the cryostatMechanics: Compatible with 100W

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Power consumption

R&D status Sensor R&D

First custom CCD in FY2007 4ch/chip, 4 different source follower designs Smallest power consuming channel: ~10mW/ch

Readout ASIC Amp, CDS, and charge-sharing SAR ADC Design completed, submission in September 4ch/chip < 10mW/ch if output is not connected (driving 100

load with 1V pulse consumes ~10mW!)

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Wafer thinning Two methods are considered

Partial thinning by etching (like DEPFET collab) Easy to handle More material (thick frame)

Total thinning by etching or mechanical method Less material Hard to handle (wire bonding OK?) Flatness ?

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Partial thinning Sample CCDs; Front side processed 300m thick frame and 20m thick image area Flatness is poor 20m looks too thin

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FEA of Ladders

Si (CCD wafer) RVC (Reticulated Vitreous Carbon)

10 cm

Epoxy

Deformation by self-weight is calculated byFEA program COMSOL

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FEA of Ladders Parameters (assumption)

Geometry

Density (g/cm3) X0 (g/cm2) E (GPa)

Si 2.33 21.8 110

Epoxy 1.15 40.9 3

RVC 0.05 42.7 0.031

Thickness Weight Radiation length

Si 50 m 0.01165 g/cm2 0.0534%X0

Epoxy 50 m 0.00573 g/cm2 0.014%X0

RVC 2 mm 0.0084 g/cm2 0.0234%X0

Epoxy 50 m 0.00573 g/cm2 0.014%X0

Si 50 m 0.01165 g/cm2 0.0534%X0

Sum 0.04316 g/cm2 0.1582%X0

0.08%X0/layer

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FEA of Ladders

Results Maximum deformation:

Without gap : vmax=0.536 m

With 0.2mm gap : vmax

=0.723 m For longer ladders

vmax ~ l4 ~8.6 m for 20cm ladder without gap

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Summary and future prospect

Among many engineering issues to be studied for FPCCD vertex detector, we have started study for Power consumption (sensor/ASIC R&D) Wafer thinning and ladder design

Due to lack of resources, these studies are at very primitive stage

As a long term goal (~2012?), construction of full size engineering model (dummy detector) would be necessary