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Introduction to Computer Organization

KR ChowdharyProfessor & Head

Email: [email protected]

Department of Computer Science and EngineeringMBM Engineering College, Jodhpur

January 13, 2011

kr chowdhary Intro CO 1/ 21

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The course

Introduction: Overview of basic digital building blocks; truthtables; basic structure of a digital computer.Number representation: Integer - unsigned, signed (signmagnitude, 1’s complement, 2’s complement, r’scomplement); Characters - ASCII coding, other coding

schemes; Real numbers - xed and oating point, IEEE754representation.Assembly language programming for some processor.Basic building blocks for the ALU: Adder, Subtractor, Shifter,Multiplication and division circuits.CPU Subblock: Datapath - ALU, Registers, CPU buses;Control path - microprogramming (only the idea), hardwiredlogic; External interface.


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Memory Subblock: Memory organization; Technology - ROM,RAM, EPROM, Flash, etc. Cache; Cache coherence protocolfor uniprocessor (simple).I/O Subblock: I/O techniques - interrupts, polling, DMA;Synchronous vs. Asynchronous I/O; Controllers.Peripherals: Disk drives; Printers - impact, dot matrix, ink jet,laser; Plotters; Keyboards; Monitors.Advanced Concepts: Pipelining; Introduction to AdvancedProcessors.


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Books and References:

Computer Architecture and Organization: J.P. Hayes,McGrawHill

Computer Architecture and organization: William StallingsComputer Architecture: H. Patterson, ElsevierNet, Wikipedia, OCW MIT


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Class test, attendance, Midsem, endsem evaluation:

20% Quizes, Assignments, attendance (attendance 5%)20% rst midsem, 20% II midsem,40% endsem

Evaluation method for nal grades: Clustering of scores. e.g.descending scores are 69, 68, 67, 67, 66 62, 61, 60, 60, 55,54, 33, 52, 48, 47, 46, 45, 44, 38, 36 thenA = {69, 68, 67, 67, 66}, B = {62, 61, 60, 60}, C =

{55, 54, 53, 52}, D = {48, 47, 46, 45, 44}, F = {38, 36}


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Computer Functional Diagram

Figure: Functional block diagram of computer


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Computer Functional Diagram2

Blocks:

Figure: Functional block diagram of computer with IO

connections are busses, size of busses: 8, 16, 32, 64. (oldersystems: 8, 12, 24, 40, etc.)Von Neumann Model (Arithmetic and Boolean logic, memory-R/W, Execution Control-branches and Jumps.


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Instructions and data

Instructions and data are in binary (1, 0) formatBinary levels in logics: TTL (0-0.8) = logic 0, (2.0-5.0v)=

logic 1(true), ECL, DTL, RTL, etc.how the CPU identies a binary string as data or instructions?What is minimum ckt to store bit (0, 1)?


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Single memory cell

Flip-op as single memory cell.

Figure: Single cell to store 1 or 0


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Logic Gates

basic gates and universal gates

XY

Z Truth table

X Y Z----------------0 0 00 1 01 0 0

1 1 1------------------

X Y

Z

AND GATE

truth Table OR GATE

X Y Z-------------0 0 0

0 1 11 0 11 1 1-------------

X

Z = X

TT not gate

X Z-------0 11 0

---------

==

==


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Simple Boolean logic circuits

Building circuits from basic gates

X YZ

W

X.YZ.W

X.Y+Z.W

X Y

XY’ X’Y

XY’+X’Y

X Y

XY’+X’Y

==

Expressions:S=X’Y+XY’ ?C=XY?

Half adder ckt

These circuits’ output is directly dependent on I/P?

More complexexpressions?

ExclusiveOR gate

These are called combinational circuits (they have nomemory element)Sequential circuits: O/P is function of current I/P andprevious I/P.


b l

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Combinational circuits

Adders, subtractors, multipliers, dividers, multiplexers,demultiplexers (O/P depends on current input)

A B

A XOR B AB

truth table

A B Sum= A’B+AB’ = A XOR B Carry=AB0 0 0 00 1 1 01 0 1 01 1 0 1

-----------------------------------------------------------

A

B

s=A XOR B

C =ABHA

ABCi

S=?Co=?FA

Full Adder (FA) TT:A B Ci S CO0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

S=A XOR B XOR CiCo=AB OR ACi OR BCi

A full adder adds two bits and carry of previous addition. Howmany FAs are required to add two 4-bit binary nos.? Why FAis FA?


A TTL NAND

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A TTL NAND gate


D i L l

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Design Levels

Design level Components IC type unit of InfoProcessor CPU, IOPs, LSI, VLSI Blocks of

memories, IO devices wordsRegister Register, combinational, MSI Words

ckts simple sequential ckstGate logic gates, SSI Bitsip-ops

Computer centre manager’s view: Processor level; Assemblylanguage programmer’s view: Register level, gate level: classical

switching theory


hi hi l D i

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hierarchical Design

Low or high levels. Should we proceed L to H or reverse?One component at level Li is equal to a network of components at level Li − 1

Specify the processor level components, then register levelcomponents, then gate levelcomponents at each level should be as independent aspossible, standard interfaces.


Gate Le el Design

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Gate Level Design

Switching theory deals with binary variables{x i }∈ {0, 1}A combinational switching function:

z = B k → B , B ∈ {0, 1}, B k is 2n binary tuplescombinational circuit can be designed by truth tables, I/P =(x 1 , . . . , x n ), O/P z (x 1 , . . . , x n )


boolean Algebra

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boolean Algebra

f (x 1 , . . . , x n ) = ∑ i ˙x i 1 . . . ˙x in , where x ij = x ij |x ij (SOP)f (x 1 , . . . , x n ) = ∏ i ( ˙x i 1 + · · · + x in ). (POS)The above is called Quinne-McClusky Method .S = ABC i + AB C i + AB C i + ABC i , from truth tableC o = ABC i + ABC i + AB C i + ABC i , from truth table(Or, function C o (A, B , C i ) = ( m3 , m5 , m6 , m7). The mintermm i assumes a value 1 for unique value of variables.Maxtermdenes the 0s in the truth table).Alternatively, sum S is: (A⊕B )⊕C i

= ( AB + AB )⊕C i = ABC i + ABC i + AB C i + AB C i C o , the carry out of full adder, is AB + AC i + BC i


Karaugh Map or K map for minimization of gate circuits

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Karaugh Map or K-map for minimization of gate circuits

After Maurice Kaurnaugh (Bell Labs, 1950)

The function Co (A, B , Ci ) Can be implemented by three AND gates plus one OR gate. Alternatively by: four gates each havingfan-in 2.


K map for minimization using maxterms

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K-map for minimization using maxterms

C o (A, b , C i ) = ( A + B )(A + C i )(B + C i )= ( A + AC i + AB + BC i )(B + C i )

= . . .

= AB + BC i + AC i kr chowdhary Intro CO 19/ 21

Sequential circuits

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Sequential circuits

z (t + ∆) = y (t ) = x 1(t ) . x 2. y is internal state variable.

SR = 00 ⇒ y 1 = y 2 = 0, or y 1 = y 2 = 0SR = 10 ⇒ y 1 = y 2 = 1 , SR = 01 ⇒ y 1 = y 2 = 0Race Condition? (if SR =11) Let SR =11, ∴ , y 1 = y 2 = 0 after ∆time.Now let SR=00, y 1 = y 2 = 0 ⇒ y 1 = y 2 = 1 ⇒ . . . (Oscillatesbetween 0 and 1). this happens if ∆ 1 = ∆ 2. Solution: SR = 11 is

kept forbidden state. kr chowdhary Intro CO 20/ 21

Sequential circuits-2

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Sequential circuits-2

Race conditions are eliminated by timing signals (clock)

Sequential circuits + clock = Synchronous circuits circuits not timed by clock are asynchronous circuits (pronetoo race conditions)Triggering takes place on rising or trailing edge of clock pulse.


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