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1 Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction Qiang Xu The Chinese University of Hong Kong Dianwei Hu and Dong Xiang Tsinghua University Beijing, China Slide 2 2 Outline Background Pattern-Directed Virtual Partitioning Routing-Aware Virtual Partitioning Experimental Results Conclusion Slide 3 3 Test Power Toggle rate in test mode may be significantly higher than that in functional mode Excessive accumulated power -> permanent damage Excessive instantaneous power -> test yield loss Excessive test power is a major concern! Slide 4 4 Prior Work on Test Power Reduction Scan chain manipulation: Scan chain partitioning (e.g., Whetsel ITC02) Scan chain reordering (e.g., Bonhomme ITC02) Test vector manipulation: Power-aware ATPG (e.g., Wang TCAD 98) Low-power X-filling (e.g., Butler ITC04, Wen ITC 05) Test vector reordering (e.g., Dabholkar TCAD98 ) Test scheduling Circuit modification Slide 5 5 Circuit Partitioning for Test Power Reduction Tester Data SE TCK Glue Logic Circuit under Test wrapper Scan chain P1 wrapper Scan chain P2 Slide 6 6 Observations and Motivation Test patterns power consumptions vary significantly Only a few care-bits necessary for a test pattern to detect all the faults covered by it Applying high-power patterns at a partitioned subcircuit containing all their care-bits reduces test power without fault coverage loss Slide 7 7 Virtual Circuit Partitioning High-power Patterns Glue Logic Circuit under Test Scan chain P1 Scan chain P2 Low-power Patterns Slide 8 8 Problem Definition How to partition the circuit such that the care-bits of as many as possible high-power patterns belong to a single partition? Slide 9 9 Design Flow Start (with given specified patterns ) Rank test patterns based on capture power Fault simulation Identify care-bits for the high-power patterns Iteratively partition the circuit Meet constraints End Yes No Slide 10 10 Care-Bits Identification Let low-power patterns detect as many faults as possible Response care-bits: fault simulation Stimulus care-bits: limited implication Cost function, depends on: Care-bits selected by previous patterns Comparison between different response care- bits Slide 11 11 Care-Bits Identification sa-0 1 1 0 1 0 1(0 ) 0(1 ) Response Carebits Slide 12 12 Care-Bits Identification sa-0 1 1 0 1 0 1(0) 0(1) Stimuli Carebits Slide 13 13 Care-Bits Identification sa-0 1 1 0 1 0 1(0) 0(1) Stimuli Carebits Slide 14 14 Iterative Partitioning P1 F1 P2 F2 P3 F3F4 High power Low power Patterns Faults Fault simulation Slide 15 15 Iterative Partitioning P2 F2 P3 F3F4 I1I1, I2 R1R2 I1 R1 Patterns Faults High power Low power P1 F1 Slide 16 16 Iterative Partitioning R4 I3, I4 I1, R1 I3, I4, R4 Patterns Faults P2 F2 P3 F3F4 P1 F1 High power Low power Slide 17 17 Iterative Partitioning R1 I2 Patterns Faults P2 F2 P3 F3F4 P1 F1 High power Low power I1, R1 I3, I4, R4 I1, R1, I2 Slide 18 18 Iterative Partitioning R1 R3 I3, I4 I2 I1, I2 Patterns Faults P2 F2 P3 F3F4 P1 F1 High power Low power I3, I4, R4 I1, R1, I2 Slide 19 19 Routing-Aware Partitioning Partitioning significantly affects scan chain routing cost Solution: constraint-driven partitioning Model the spreadness of the scan FFs Divide the circuit layout into sub-regions Routing either horizontally or vertically in a snake-like way Slide 20 20 RA-Partitioning Design Flow Start (with given specified patterns) Rank test patterns based on capture power Fault simulation Identify care-bits for the high-power patterns Iteratively partition the circuit Meet constraints End Yes No Iteratively partition the circuit with routing consideration Slide 21 21 Routing-Aware Partitioning Cont. (150,180) (130,100) (80,100) (40,40) ( 0,220 ) ( 250,220 ) (0,0) (250,0) H V d b c a 5 25 +=30 45 85 +=130 CUT Slide 22 22 Routing-Aware Partitioning Cont. (150,180) (130,100) (80,100) (40,40) (0,220) (250,220) (0,0) (250,0) H V d b c a 70 +=90 10 70 CUT 10 Slide 23 23 Iterative Partitioning Routing-Aware Partitioning Experimental Result s38417 (stuck-at) Slide 24 24 Experimental Result s38584 (broadside) Iterative Partitioning Routing-Aware Partitioning Slide 25 25 Power comparison for stuck-at Average power with VP: 49.13% Average power with RA-VP: 57.67% Slide 26 26 Wire length comparison for stuck-at Average wire length with VP: 142.52% Average wire length with RA-VP: 109.62% Slide 27 27 Power comparison for broad-side Average power with VP: 63.59% Average power with RA-VP: 68.28% Slide 28 28 Wire length comparison for broad-side Average wire length with VP: 141.68% Average wire length with RA-VP: 112.57% Slide 29 29 Conclusion Excessive test power is a major concern today We propose routing-aware circuit virtual partitioning technique for test power reduction without adding test wrappers without fault coverage loss with small scan chain routing cost