1094 ieee journal of solid-state circuits, … ieee journal of solid-state circuits, vol. 40, no. 5,...

1094 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

A 0.25-�m CMOS Quad-Band GSM RF TransceiverUsing an Efficient LO Frequency Plan

Eunseok Song, Yido Koo, Member, IEEE, Yeon-Jae Jung, Deok-Hee Lee, Sangyoung Chu, andSoo-Ik Chae, Member, IEEE

Abstract—This paper describes a single-chip CMOS quad-band(850/900/1800/1900 MHz) RF transceiver for GSM/GPRS appli-cations. It is the most important design issue to maximize resourcesharing and reuse in designing the multiband transceivers. Inparticular, reducing the number of voltage-controlled oscillators(VCOs) required for local oscillator (LO) frequency generation isvery important because the VCO and phase-locked loop (PLL) cir-cuits occupy a relatively large area. We propose a quad-band GSMtransceiver architecture that employs a direct conversion receiverand an offset PLL transmitter, which requires only one VCO/PLLto generate LO signals by using an efficient LO frequency plan.In the receive path, four separate LNAs are used for each band,and two down-conversion mixers are used, one for the low bands(850/900 MHz) and the other for the high bands (1800/1900 MHz).A receiver baseband circuit is shared for all four bands becauseall of their channel spaces are the same. In the transmit path,most of the building blocks of the offset PLL, including a TX VCOand IF filters, are integrated. The quad-band GSM transceiverthat was implemented in 0.25- m CMOS technology has a sizeof 3.3 3.2 mm2, including its pad area. From the experimentalresults, we found that the receiver provides a maximum noisefigure of 2.9 dB and a minimum IIP3 of 13.2 dBm for the EGSM900 band. The transmitter shows an rms phase error of 1.4and meets the GSM spectral mask specification. The prototypechip consumes 56 and 58 mA at 2.8 V in the RX and TX modes,respectively.

Index Terms—CMOS, dc offset, direct conversion, frequency di-vider, GSM, LO frequency, offset phase-locked loop (PLL), quad-band, transceiver.

I. INTRODUCTION

THE wide use of portable communication systems has cre-ated a great demand for low-cost, low-power, small form-

factor transceivers. In the past, radio frequency (RF) front-endcircuits have been implemented with GaAs or bipolar junctiontransistor (BJT) technologies while the low-frequency basebandcircuits have used CMOS technologies. Such implementationsusing the technologies of different kinds, however, are not suit-able as a low-cost solution for RF transceivers. In modern-dayimplementations, high-frequency CMOS circuits are becomingmore feasible due to the aggressive scale-down in CMOS tech-nologies. Thus, the recent research trends have been to develop

Manuscript received June 25, 2004; revised October 22, 2004.E. Song and S.-I. Chae are with the ISRC, School of Electrical Engineering,

Seoul National University, Seoul 151-742, Korea (e-mail: [email protected]).

Y. Koo, Y.-J. Jung, D.-H. Lee, and S. Chu are with GCT Semiconductor, Inc.,San Jose, CA 95131 USA.

Digital Object Identifier 10.1109/JSSC.2005.845990

a monolithic transceiver with low-cost CMOS technologies [1],[2].

The Global Systems for Mobile communication (GSM)network spanning over 200 countries is a rapidly growing andevolving mobile standard [3]. It is the first cellular system thatspecifies digital modulation and network-level architecturesand services [4]. There are several frequency bands where GSMterminals are or will shortly be operated. Therefore, a GSMterminal that can support all of the GSM frequency bands listedin Table I will be more useful for its global roaming [3], [5].

Previously, there have been several works related to GSMtransceivers [6]–[11]. Early GSM transceivers [6]–[8] employedthe super-heterodyne architecture to integrate the receiver andtransmitter in a single chip. However, they were implementedwith BJT technology and did not integrate all of the functions,requiring several external components, such as an IF filter. Al-though the GSM transceivers [9], [10] developed later wereimplemented with low-cost CMOS technology, they still re-quired several off-chip filters for image rejection and channelselection [9] or deferred these tasks to their baseband digitalsignal processing (DSP) chip [10]. Moreover, they supportedonly single-band communication, that is, the GSM900 band in[9] and the DCS1800 band in [10]. A GSM transceiver that sup-ports the quad bands (850/900/1800/1900 MHz) [11] was im-plemented with BiCMOS technology. It employed a direct con-version receiver (DCR) and achieved a considerably high inte-gration level. However, the TX IF filters and loop filters were notintegrated. Moreover, its frequency doubler and subharmonicmixers (SHMs), which consume a large bias current, are dif-ficult to be implemented in CMOS technology due to the rela-tively small transconductance of the MOS transistors.

In order to overcome these problems, we have proposed asingle-chip CMOS RF transceiver architecture for the four GSMbands (850/900/1800/1900 MHz). The proposed transceiverarchitecture employs a direct-conversion receiver and an offsetPLL transmitter. The rest of this paper is organized as follows.In Section II, we explain the proposed architecture of the GSMquad-band transceivers in CMOS technology. Moreover, wealso describe how we obtained an efficient LO frequency planthat is suitable for area reduction, low-power consumption, andprecise generation in the proposed architecture. The majorcircuit blocks of the transceiver are described in Section III.The experimental results of the prototype GSM transceiverare presented in Section IV. Finally, the conclusion is given inSection V.

0018-9200/$20.00 © 2005 IEEE

SONG et al.: 0.25- m CMOS QUAD-BAND GSM RF TRANSCEIVER USING AN EFFICIENT LO FREQUENCY PLAN 1095

TABLE IGSM FREQUENCY BANDS

II. QUAD-BAND TRANSCEIVER ARCHITECTURE AND ITS LOFREQUENCY PLAN

In this section, we propose the architecture for the GSM quad-band transceiver that employs a direct-conversion receiver andan offset PLL transmitter. Therefore, we can share the basebandfilters among the four frequency bands and image rejection fil-ters are not required in the receiver, which reduces the area ofthe transceiver. We employ an offset PLL transmitter in the pro-posed transceiver architecture because it has lower noise andless spurious emission.

The LO frequency planning is the key to designing the multi-band GSM transceivers because it strongly influences the per-formance of the transceiver as well as its area and power con-sumption [12]. What we must consider in the LO frequencyplanning includes the number of VCOs/PLLs required, the VCOtuning range, precise generation, and RF-LO interference.To reduce the die size of a GSM quad-band transceiver, min-imizing the number of VCOs and PLLs is the most importantfactor because they occupy relatively large areas in the trans-ceiver ICs. In this section, we will also describe how we ob-tained an efficient frequency plan using direct down conversionfor the receiver and offset PLL for the transmitter. Then, we willexplain the detailed architecture of the quad-band transceiverbased on the proposed frequency plan.

Most RF communication systems today employ accuratesignals for the complex domain signal processing. Thus, gener-ating the precise signals is a key to making a successfulfrequency plan, in order to meet the phase error specificationfor the GSM transceivers.

A. Precise Generation

In integrated circuits, there are two common methods for gen-erating signals: using an RC–CR phase shifter or using adivider circuit. The RC–CR phase shifters are more suitable tothe frequency planning of the transceivers because they do nottranslate the frequency at all. However, it is difficult to achievegood matching performance in the RC–CR phase shifters be-cause the absolute values of R and C depend on the processvariations. Although the higher order phase shifters can reducethese mismatches substantially [10], they have larger signal at-tenuation and consume more power.

Fig. 1 shows the other method of generating I/Q signals withthe divider circuits. In the frequency-divide-by-2 method shownin Fig. 1(a), is rising-edge triggered and is falling-edge triggered. Therefore, the phase accuracy of the quadrature

Fig. 1. Waveforms of input and I=Q signals generated with frequencydividers. (a) With a divide-by-2 circuit. (b) With a divide-by-4 circuit.

signal depends on the duty cycle of the input signal. On the otherhand, in the frequency-divide-by-4 method shown in Fig. 1(b),both and are rising-edge triggered. Therefore, thephase accuracy is not affected by the duty cycle of the inputsignal. Although the divide-by- methods require a higher fre-quency signal, which can be a disadvantage in a frequency plan,they consume a relatively small current and provide good phaseaccuracy against the process and frequency variations. We de-cided to use the divide-by-4 or divide-by-8 circuits to generatethe precise signals in the frequency plan in order to meetthe phase-error specification for the GSM transceivers.

B. How to Obtain an Efficient Frequency Plan

In finding an efficient LO frequency plan, we put some con-straints that are required to develop a low-power low-cost smallform-factor GSM transceiver based on the proposed architec-ture, as shown in Table II. First, it is very important to minimizethe number of VCOs/PLLs required in the transceiver. Note thatthe number of VCOs required depends on the tuning range ofeach VCO and that the typical tuning range of an on-chip L–CVCO is less than 20% due to their design margin against theL and C variations. Although the VCOs using a ring oscillatorhave a wider tuning range, they are rarely used in the transceiverIC due to their large phase noise.

The constraint for is intended to loosen the VCOpulling and pushing effect by separating away from


TABLE IICONSTRAINTS FOR THE LO FREQUENCY PLAN FOR THE GSM QUAD-BAND TRANSCEIVER ARCHITECTURE THAT EMPLOYS A DIRECT-CONVERSION

RECEIVER AND AN OFFSET PLL TRANSMITTER

Fig. 2. LO frequency plans for the transceiver architecture that employs adirect conversion receiver and an offset PLL transmitter. (a) A general frequencyplan. (b) Proposed frequency plan.

the RF frequency [6], [13], [14]. The constraint for thegeneration with the divide-by-4 or divide-by-8 circuits is addedto meet the tight phase error in the GSM specification becausethey are more precise and insensitive than the phase shifters, asexplained before.

Now we explain how we obtained the efficient LO frequencyplans that satisfy the constraints in Table II. Fig. 2(a) shows ageneral frequency plan that employs only one LO VCO/PLL and

is suitable to the offset PLL transmitter for the quad-band trans-ceiver, which can satisfy the requirement of separatingaway from in the direct conversion receiver. Note that wedo not permit low-side mixing for high bands, to prevent the LOVCO frequency from being too high. For the frequency plan inFig. 2(a), we can write the following equations:

(1)

(2)

(3)

where is the low-band frequency and is thehigh-band frequency. Equation (3) is the necessary condition tosupport the quad-band GSM. From (1)–(3), we write

(4)

To solve (4), , and are assumed as follows:

or (5)

(6)

(7)

Equations (5)–(7) are the constraints for generationwith the divide-by-4 or divide-by-8 circuits, thus limiting theVCO frequencies and making the task of implementing thedividers easier. By solving (4)–(7) together, we obtained sixfeasible solutions for , and , as shown in Table III.If , and are all fixed, we can calculate the VCOrange and the TX IF range from the frequency band definedin the GSM specification. Among the six solutions, Plan3, inwhich the VCO and TX IF frequencies are the lowest, is themost suitable to be implemented in integrated circuits becausethe on-chip L–C VCO has smaller phase noise if its oscillationfrequency is low. In addition, its prescaler is easier to be de-signed and consumes less current for the lower LO frequencies.The TX IF range should not be too high so that the TX IFfilters can be easily implemented in the integrated circuits. Weadopted the frequency Plan3 shown in Fig. 2(b), which satisfiesall the constraints in Table II.

C. Quad-Band Frequency Plan

Based on the frequency Plan3 in Table III, we describethe detailed frequency plan suitable to the GSM quad-band


TABLE IIILO FREQUENCY PLANS THAT SATISFIES THE CONSTRAINTS IN TABLE II

Fig. 3. RX block diagram based on the proposed frequency plan.(a) GSM850/EGSM900 bands. (b) DCS1800/PCS1900 bands.

transceiver. In the low-band RX (GSM850/EGSM900) fre-quency plan shown in Fig. 3(a), the LO VCO runs at of theRF frequency, and the LO signal for direct down conversionis generated by the high-sided mixing of the signals fromthe divide-by-2 with the divide-by-8 signals of the LO VCOfrequency. Note that the signals are generated throughthe divide-by-8. For the high-band RX (DCS1800/PCS1900)frequency plan in Fig. 3(b), the LO VCO runs at 4/5 of theRF frequency and the signals are generated through thedivide-by-4 of the LO VCO frequency. Note that a single LOVCO in the receiver supports the quad bands by being sharedbetween the low-band and high-band receivers. Consequently,

the required range of the LO VCO that supports the quad bandis from 1390 to 1592 MHz for the receiver.

In the TX frequency plan shown in Fig. 4, we used theoffset PLL architecture including a TX VCO to reduce thenoise in the transmit signal. The TX VCO directly coversthe high-band RF and its divide-by-2 signal covers for thelow-band RF. Similar to the RX frequency plan, the LO VCOin the TX frequency plan runs at 8/5 of the transmit RF for thelow-band RX (GSM850/EGSM900) and of the transmit RFfor the high-band RX (DCS1800/PCS1900), as shown in Fig. 4.The quadrature LO2 signals that are generated by divide-by-4or divide-by-8 circuits are applied to the offset UP mixers.Similarly, an LO VCO can be shared between the low andhigh bands. Thus, the required tuning range of an LO VCOthat supports the quad-band TX is from 1318 to 1528 MHz,which is mostly overlapped with the tuning range of the LOVCO in the receiver. Therefore, we can share an LO VCObetween the receiver and the transmitter. Table IV summarizesthe tuning ranges of the TX and LO VCOs in the proposed GSMtransceiver. Each VCO can be implemented with an on-chipL–C VCO because its tuning range is less than 20%.

This frequency plan relaxes the VCO pulling/pushing prob-lems because the LO VCO frequency is either 4/5 of the high-band frequency or 8/5 of the low-band frequency. However, itrequires four different divider circuits. Because it uses the twodifferent IF frequencies in the transmitter, the IF filters of the TXoffset PLL should be designed to select their cut-off frequencyaccording to the target frequency band.

D. Quad-Band Transceiver Architecture

We propose an efficient architecture for the single-chipGSM quad-band transceiver based on the detailed frequencyplans, which can be implemented with CMOS technology. Asshown in Fig. 5, the proposed architecture integrates most ofthe building blocks for the quad-band transceiver. The requiredexternal components are the RX band-select SAW filters, thematching circuits of the LNAs, and the TX power amplifiers.

In the receiver, four separate LNAs are employed to im-prove the blocking performance for each band. In addition,two separate down-conversion mixers are used: one for thelow bands (850/900 MHz) and the other for the high bands(1800/1900 MHz). The baseband circuits are shared for all four


Fig. 4. TX block diagram based on the proposed frequency plan. (a) GSM850/EGSM900 bands. (b) DCS1800/PCS1900 bands.

TABLE IVVCO TUNING RANGES REQUIRED FOR THE GSM QUAD-BAND TRANSCEIVER BASED ON THE PROPOSED FREQUENCY PLAN

bands because their channel spaces are equal to 200 kHz. Inthe transmitter, the offset PLL is employed to meet the tightGSM spectral mask specifications. The offset PLL transmitterincludes the offset UP/DN mixers, IF filters, TX VCO, loopfilter, and preamplifiers. Because it employs a single TX VCO,

it transmits the VCO signal directly for the high bands andthrough the divide-by-2 circuit for the low bands. We usedthe - fractional- synthesizer for the LO PLL, and all theoperating modes and options of the transceiver can be set by a3-wire serial peripheral interface (SPI).


Fig. 5. Block diagram of the quad-band GSM transceiver based on the proposed frequency plan.

III. CIRCUIT DESCRIPTIONS

A. LNA

For each LNA, we used a single-stage differential LNA, asshown in Fig. 6(a), to improve its linearity. The differential LNAwas employed to achieve a good IIP2 characteristic, althoughit requires a large area and consumes more current. We useddown-bond wires as series feedback inductors to lower both thenoise figure and the input voltage standing wave ratio (VSWR).The load of the LNA is composed of a resonant circuit usingspiral inductors, which attenuates the out-of-band blockers. Theimpedance of the half circuit of its load, shown in Fig. 6(b), canbe written as follows:

(8)

From (8), we can write and as follows:

At the frequency of , the load impedance has its min-imum value, and, at the frequency of , it is at its max-imum value. should be designed to be , the receive

band frequency, to achieve maximum LNA gain. We designedto be to prevent out-of-band blockers from being

mixed-down with the third harmonics of the LO signal.Fig. 7 shows the simulation result for the PCS1900 LNA. Its

power gain is 21 dB at 1960 MHz and its rejection at the thirdharmonic band (5880 MHz) is about 56 dB. Although this LNAhas a better blocking performance, it occupies an area of about0.3 0.3 mm due to the additional on-chip spiral inductor .

B. RX Down-Conversion Mixer

The down-conversion mixer, which is a key building blockof the RF receiver, has a large influence on the noise figure andlinearity of the receiver. The down-conversion mixer we used isshown in Fig. 8, where the NMOS current, , is 3 mA. EachPMOS current source, , reduces the bias current of its corre-sponding LO switch, which is the main source of the noisein Gilbert-type mixers [15]. However, reducing the current ofthe switches too much will result in a severe degradation of con-version gain and linearity. In the mixers with a switch currentless than the bias current, a small variation in the bias current canresult in a large change in the output voltage. Thus, the outputcommon-mode voltage is very sensitive to device mismatchesand process variations. Instead of using the ac couplers, whichhave a long settling time and occupy a large area, we employeda common-mode feedback circuit with an operational amplifierto overcome these problems [16], as shown in Fig. 8.

The simulation results for the down-conversion mixer areshown in Fig. 9. The rms output noise voltage in Fig. 9(b) is


Fig. 6. LNA. (a) Schematic. (b) Equivalent circuit for a half circuit of the load.

Fig. 7. Simulation result for the PCS1900 LNA.

calculated over the frequency range 1–100 kHz. If the of thePMOS load is sufficiently large, the output load impedance is R

. Thus, the load impedance is almost indepen-dent of the switch and load current. As a result, the conversiongain of the mixer can be maintained even though the switchcurrent is reduced to a certain level.

Fig. 8. Down-conversion mixer with common-mode feedback (CMFB).

Fig. 9. Simulation results for the down-conversion mixer. (a) Gain and IIP3versus I . (b) RMS output noise versus I .


Fig. 10. RX baseband block diagram.

However, the conversion gain and IIP3 in Fig. 9(a) are se-verely degraded as the PMOS current increases more than2 mA. There is a tradeoff between noise and linearity, and, there-fore, the PMOS current is selected to be 2 mA, which isnear the point where reducing the output noise by increasingthe PMOS current more has no further advantage.

C. RX Baseband Circuits

The block diagram of the RX baseband is shown in Fig. 10.It consists of a PreAGC, four PostAGCs, and three low-pass fil-ters. The overall dynamic range of the RX baseband circuit is 75dB. In order to loosen the linearity requirement of the basebandcircuits, the LNA is designed to have about a 27-dB gain con-trol range. Thus, the total dynamic range of the receiver is about102 dB. The output of the RX down-conversion mixer is appliedto the input of the PreAGC, as in Fig. 10. We allocated a largerarea and more current to the PreAGC than the other basebandcircuits, in order to allow both high linearity and low noise per-formance. Three low-pass filters reject the in-band interferers,which are implemented by third-order active-RC Butterworthfilters.

In the direct-conversion receivers, the dc-offset cancellationis very important. Although the ac couplers are a simple solu-tion, they require a large area and a long settling time. We usedthe active dc-offset cancellation circuits (DCCs), which are con-nected to each AGC, as shown in Fig. 10. An AGC cell with theDCC is shown in Fig. 11, where we used MOS capacitors to re-duce the area. A dc extractor integrates the offset voltage of theAGC output and the integrated offset voltage is subtracted fromthe AGC input through a feedback connection. For the AGC cir-cuit in Fig. 11(a), the AGC output can be written as follows:

(9)

From (9), the transfer function of the AGC can be written asfollows:

(10)

Fig. 11. VGA with DCC. (a) Schematic. (b) Its frequency response.

The transfer function of (10) is drawn in Fig. 11(b). The cornerfrequency of the high-pass filter can be adjusted by changing theresistance in the dc extractor.

D. TX Offset UP/DN Mixers

The nonlinear terms of the offset UP mixer will cause spu-rious emission in the transmit signal. Among them, the spurioustones from the baseband third harmonics are hard to remove be-cause they appear very close to the transmit frequency. Fig. 12shows the offset UP mixer used in this work, which improveslinearity substantially using a gain-boosting operational ampli-fier. is a degeneration resistor and the transistors, M1 andM2, operate as source followers. If the gain-boosting circuits arenot added to M1 and M2, harmonic terms can appear when thecurrent of varies due to the insufficient transconductanceof M1 and M2.

If the gain of the operational amplifier is sufficiently large,the differential current of M1 and M2 can be written as follows:

Because the signal bandwidth of the IN/INB is less than100 kHz, it is not difficult to design an operational amplifierwith a bandwidth wider than 100 kHz. From the simulation


Fig. 12. Offset UP mixer with improved linearity.

Fig. 13. Offset DN mixer with cascode stage.

result, the offset UP mixer provides an IIP3 of 12 dBV, whichshows an improvement of about 10 dB compared with the UPmixer without the gain boosting circuits.

The offset DN mixer translates the VCO frequency into theIF frequency, which is applied to the phase frequency detector(PFD), as shown in Fig. 5. Because it is a relatively high fre-quency circuit, the signal couplings should be taken into ac-count. Fig. 13 shows the offset DN mixer used in this work.The cascode transistors, M3 and M4, prevent the LO signalsfrom directly coupling to the VCO/VCOB. If the LO signalsare coupled to the VCO/VCOB, it will add spurious tones tothe transmit signal. According to the simulation results, the cas-code stack reduces the coupling from the LO to the VCO bymore than 20 dB.

Fig. 14. Simulation result for TX offset PLL: rms phase error and phase noiseat 20-MHz offset versus loop bandwidth.

Fig. 15. Microphotograph of the quad-band GSM transceiver.

E. Offset PLL Loop Filter

The frequency of the Gaussian-filtered minimum shift keying(GMSK) modulated signal is deviated within the range from

kHz to kHz according to the conveyed digital data.Thus, the output of the offset UP mixer, which corresponds tothe reference input of the PFD, will also be deviated from thecenter IF frequency. If the bandwidth of the offset PLL is toonarrow, the output of the offset PLL cannot track the referencedeviation, which can result in a large rms phase error of thetransmit signal. Fig. 14 shows the simulation result for the rmsphase error along with the phase noise at 20-MHz offset versusthe loop bandwidth of the offset PLL. There exists a tradeoffbetween the rms phase error and the 20-MHz wideband noise[8], [17]. In order to achieve an rms phase error of less than0.6 and to minimize the wideband noise, we designed the loopbandwidth of the offset PLL to be 933 kHz. In designing theloop parameters of the offset PLL, the division factor shouldbe calculated as 1. Because the VCO frequency is translated tothe IF frequency by the offset DN mixer, the frequency deviationof the VCO output is not scaled down at all [18].


Fig. 16. RX noise figure versus frequency. (a) EGSM900 band. (b) PCS1900band.

Fig. 17. RX IIP3 versus frequency. (a) EGSM900 band. (b) PCS1900 band.

IV. EXPERIMENTAL RESULTS

The quad-band GSM transceiver described in the previoussection was implemented in 0.25- m 1-poly 5-metal CMOStechnology, and its microphotograph is shown in Fig. 15. The

Fig. 18. Constellations of the GMSK demodulated signal at the RX output.(a) For the RX input power of �86 dBm. (b) For the RX input power of �102dBm.

prototype chip occupies an area of 3.3 3.2 mm including itspads, which was assembled in a 40-pin quad flat no-lead (QFN)package. The RX RF circuits, such as LNAs and down-conver-sion mixers, are placed in the upper left corner and the RX base-band circuits, such as PGAs and LPFs, in the lower left corner.We allotted a large area to the RX baseband blocks to reduce the

noise. The TX offset PLL including the TX VCO is locatedin the upper right corner and the LO VCO with a - frac-tional- synthesizer is located in the lower right corner. Theirloop filters are integrated using the MOS capacitors. The type ofeach VCO is an LC oscillator with an external inductor, and itssize is about 0.7 0.7 mm . Each VCO consumes about 5 mA.

Fig. 16 shows a graph of noise figure versus frequency forthe receiver. The measured chip noise figures (NFs) for theEGSM900 and PCS1900 bands are less than 2.9 and 3.4 dB,respectively. The NF variations in a band are related with theSAW filter ripple, impedance matching, and so on. We mea-sured the NF with the inclusion of the external band-select SAWfilter. From this, we compensated for the insertion loss of the


Fig. 19. Measured rms phase error at the TX output for the GMSK modulatedsignal.

SAW filter in order to calculate the chip NF. Although the inser-tion loss of the SAW filter at each channel (or frequency) mustbe strictly compensated for, we used a typical loss in a bandfor simplicity. Thus, the insertion loss variation of the SAW isincluded in the NF plot of Fig. 16. The SAW filters used in thiswork are the EPCOS B7701/B7706/B7716/B7717 componentsfor GSM/EGSM/DCS/PCS, and their typical insertion lossesare 2.3/2.6/3.0/2.6 dB, respectively. Fig. 17 shows a graph ofIIP3 versus frequency for the receiver. The IIP3 values weremeasured by the two-tone test. The minimum receiver IIP3 isabout dBm for the EGSM900 band and dBm forthe PCS1900 band, which satisfies the specifications requiredfor the GSM transceiver. The specifications shown in Fig. 17were also calculated by assuming that the front-end loss is4 dB. Fig. 18 shows the constellations of a GMSK demodulatedsignal at the RX output for the input of (a) dBm and (b)

dBm. The measured rms phase errors are 2.9 and4.6 , respectively, which are sufficiently less than the required

rms error of 5 in the GSM specifications [5].Fig. 19 shows the rms phase error at the TX output for

the GMSK modulated signal. According to the experimentalresults, the rms phase errors for the PCS1900 and EGSM900bands are 1.7 and 1.4 , respectively, which are also sufficientlysmaller than the required RMS phase error of 5 in the GSMspecification [5]. The GMSK modulated spectrums at the TXoutput are shown in Fig. 20, which also meet the GSM spectralmask specifications [5]. The prototype chip consumes about56 mA in the RX mode and 58 mA in the TX mode at 2.8 V.Specifically, the LO generation circuitry with the exception ofthe synthesizer consumes about 10 mA.

Table V summarizes the performance of the quad-band GSMtransceiver. The overall receiver dynamic range is 102 dB. Themaximum receiver gain is 107 dB and the minimum gain is 5 dB.For the high bands, the IIP2 performance is not sufficient topass the AM suppression test. In order to improve the IIP2 at1800/1900 MHz, we should reduce the mismatches between thedifferential signal paths, for example, the asymmetry of the PCBlines, the chip layout, and the pin assignment. The TX spectralmask performance at 400 kHz, as shown in Table V, is marginal.

Fig. 20. GMSK modulated spectrums at the TX output. (a) EGSM900 band.(b) PCS1900 band.

which is due to the nonlinearity of circuits, especially the thirdharmonics of the offset UP mixer. Thus, the IIP3 of the offsetUP mixer should be improved in order to achieve better TXmask performance. We used a - fractional- synthesizerto meet the settling time requirement for the GPRS class 12.The measured RX and TX settling times are less than 200 and220 s, respectively.

Although the frequency plan used in this study has the ad-vantage of reduced area and smaller power consumption, theundesirable mixing products from the LO generator affect theout-of-band blocking performance of the receiver. The front-endSAW filter on the receiver side should have enough selectivity tosuppress the input frequency bands corresponding to the mixingterms. In order to improve the blocking characteristics, an L–Ctuned amp for the LO buffer or a bandpass filter following theLO generation mixers should be added, which might increasethe power consumption. Therefore, there is a tradeoff betweenperformance and power consumption.

V. CONCLUSION

In this paper, we proposed an efficient frequency plan that issuitable for the GSM quad-band transceiver. We also presented a


TABLE VPERFORMANCE SUMMARY OF THE QUAD-BAND GSM TRANSCEIVER CHIP

single-chip 0.25- m CMOS RF transceiver using the proposedfrequency plan. The GSM quad-band transceiver includes onlyone LO VCO with a tuning range from 1318 to 1592 MHz. Weused divide-by-4 and divide-by-8 circuits to generate all of the

signals, which consume less power and are less sensitive tothe process and frequency variations, compared with the phaseshifters. Moreover, we selected the LO VCO frequencies to re-duce the VCO pulling and pushing effects by separating themaway from the RF frequency. According to the measured re-sults, the receiver provides the maximum noise figure of 2.9 dBand the minimum IIP3 of 13.2 dBm for the EGSM band. Thetransmitter presents an rms phase error of 1.4 , which meetsthe GSM spectral mask specification. The prototype chip con-sumes 56 mA in the RX mode and 58 mA in the TX mode at2.8 V. Thus, we conclude that the proposed GSM transceiver issuitable for low-cost low-power small-form factor solutions.

ACKNOWLEDGMENT

The authors would like to thank S.-W. Lee and J. Park fortheir discussion on the transceiver architecture, S. Hong for hishelpful comments on the GSM standard, and Y. Ahn for his testequipment setup.

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Eunseok Song was born in Korea in 1971. Hereceived the B.S. and M.S. degrees in electricalengineering from Seoul National University, Seoul,Korea, in 1996 and 1999, respectively, where he iscurrently working toward the Ph.D. degree.

He has been working on CMOS analog circuit de-sign, and his research interests include CMOS RF cir-cuits and CMOS image sensors.

Yido Koo (S’96–M’03) was born in Seoul, Korea. Hereceived the B.S., M.S., and Ph.D. degrees in elec-trical engineering and computer science from SeoulNational University, Seoul, Korea, in 1996, 1998, and2003, respectively. His doctoral dissertation includesthe design of a fully integrated CMOS frequency syn-thesizer for CDMA applications.

From 2000 to 2002, he developed the frequencysynthesizer for CDMA and PHS wireless systemsworking with GCT Semiconductor, Inc., San Jose,CA, as a part-time Design Engineer. In 2003, after

graduation, he joined the same company as a Manager of Analog Division,where he is now involved in the design and implementation of RF transceiverand building blocks for GSM and W-CDMA systems. He is the inventor of twoand co-inventor of several U.S. patents.

Dr. Koo was the recipient of the 2003 IEEE Best Student Award of the IEEESolid-State Circuits Society Seoul Chapter.

Yeon-Jae Jung was born in Korea in 1974. He re-ceived the B.S., M.S., and Ph.D. degrees in electricalengineering and computer science from Seoul Na-tional University, Seoul, Korea, in 1997, 1999, and2003, respectively.

Currently, he is a Design Engineer with GCTSemiconductor, San Jose, CA. His main researchinterests are in RF and baseband CMOS circuits andsystem planning for wireless communications.

Deok-Hee Lee was born in Korea on May 6, 1977.He received the B.S. and M.S. degrees in electricalengineering from Seoul National University, Seoul,Korea, in 2000 and 2002, respectively.

He is currently with GCT Semiconductor, Inc., SanJose, CA, where he works on the design and develop-ment of integrated CMOS transceivers for GSM andwireless LAN.

Sangyoung Chu was born in Korea on August 11,1973. He received the B.S. and M.S. degrees in elec-trical engineering from Seoul National University,Seoul, Korea, in 1998 and 2000, respectively.

In 2000, he joined GCT Semiconductor, Inc., SanJose, CA, where he is currently a Principal Engineerleading the development of wireless communicationsystems.

Soo-Ik Chae (M’87) received the B.S. and M.S. de-grees in electrical engineering from Seoul NationalUniversity, Seoul, Korea, in 1976 and 1978, respec-tively, and the Ph.D. degree in electrical engineeringfrom Stanford University, Stanford, CA, in 1987.

He was an Instructor with the Electronics Depart-ment, Air Force Academy of Korea, Seoul, from 1978to 1982. He also worked as a Manager of an ASICDesign Group, ZyMOS Corporation, Sunnyvale, CA,from 1987 to 1988 and a General Manager at DaewooTelecom Company from 1988 to 1990. Since 1990,

he has been with Seoul National University, where he is currently a Professorin the School of Electrical Engineering and the Director of the Center of SoCDesign Technology. He was the Director of the Inter-University SemiconductorResearch Center (ISRC) from 2001 to 2003. His research interests include dig-ital system design, especially programmable DSP design for H.264 and three-di-mensional graphics and ultralow-power circuits.

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