11

22

Class Presentation for VLSI Course

Major Reference is:

Circuit Design Issues in Multi-Gate FET CMOS Technologies

Christian Pacha, Klaus VonArnim, Thomas Schulz, Wade Xiong, Michael

Gostkowski, Gerhard Knoblinger, Andrew Marshal, Thomas Nirschl, Joerg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin,

Klaus Schruefer

Instructor: S. M. Fakhraee

Presented by: Behzad Ebrahimi

December 2006

In ISSCC2006/ SESSION 23/ TECHNOLOGY AND ARCHITECTURE DIRECTIONS/ 23.2

33

Outline

Introduction Comparison speed in different structures Low power design Opamp with FinFET I/O and ESD protection

4

Introduction

4

Multiple-Gate FET Transistors are promising device structures for

sub-45nm technology.

• Superior Control of the Channel

• Reduced Short Channel Effect

• Lower Leakage Current

• Better Cicuit Performance

• Novel Gate-Stack materials

• Reduced parasitic capacitances

• Hole mobility improvement

5

Multi-Gate FET

TriGateDouble Gate/ FinFET

WFINL

HF

IN

FINEFF 2HW FINFINEFF W2HW

66

Multi-Gate FET

Fabrication of tall Triple-Gate FETs with 10nm fin with demonstrates the long-term scalability.

Relaxed FinFET and Triple-Gate device dimensions were chosen to increase yield and homogeneity.

Triple-Gate Control allows for higher device currents and relaxed process

requirements.

From [1]

77

Multi-Fin MuGFET

FinFET:

1npW

npW

)Wn(2HW

nH2W

FIN

EFF

FINFP

FINFINEFF

FINEFF

Triple-Gate FET:

Footprint:

Area gain over bulk CMOS:

Three-dimensional device topology in combination with a small fin pitch

improves the circuit density.

N+

Wgeo

DRAIN

SOURCE

GA

TEWfin

50nm200nm

Lg

500n

m pitch

Lg

DRAIN

SOURCE

GA

TE

SCGS

Lg

MD

R

Wgeo

DRAIN

SOURCE

LgPOLY POLY

N+

500n

m

From [1]

8

Multi-Fin MuGFET

The discrete transistor widths of multi-fin MUGFETs are a circuit design limitation compared to bulk CMOS.

This design limitation is not critical for nFET/pFET sizing in CMOS logic circuits, especially for a <110> channel surface orientation [1]

Discrete transistor widths are a concern for SRAM cells which are composed of single-fin devices.

In SRAM the drive currents of single-fin MUGFETs can be modified only by different gate lengths.

99

Speed in Different Structure

• Performance, active and leakage current of these structures are measured using 24 ring oscillator (RO) modules.

• The ROs are composed of various gates up to NAND3/NOR3 complexity with a fan out two (FO2) .

Triple-Gate circuits using TiN metal gate electrodes are 65% faster than FinFET circuits with poly-Si gate electrodes at

VDD=1.2V.

From [1]

10

Low Power Design

10

• Low power circuits require additional high-VT devices to implement non-critical paths to switch-off non-active circuit blocks.

• Fast circuit are based on devices with minimum gate length while leakage sensetive circuits are made of devices with longer gate lengths but smaller off-currents.

From [1]

1111

Operational Amplifier

-10

-5

0

5

10

15

20

25

1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07

Frequenz [Hz]

A

[d

B]

R

10*R

Vout

VcmVcm

Vin

VDD=1.5V

• Due to the large multi-fin transistors with non-minimum gate lengths, the effect of discrete device widths on circuit design is negligible.• Bode plot ( gain vs. frequency) configured as a 20dB inverting amplifier.• The low-frequency open loop gain is A0=45dB . This is comparable with typical open loop gains achievable in deep sub-micron planar CMOS technologies.

From [3]

1212

I/O & ESD

MuGFETs show a low ESD current capability and high ESD sensitivity.

This motivates the co-integration of more robust PD-SOI devices for ESD clamps and multi-fin MuGFETs to provide large currents for fast I/O drivers.

From [1]

13

Conclusion

• Three-dimensional device topology in combination with a small fin pitch in multifin MuGFET improves the circuit density

• Novel Gate-Stack materials can improve performance.

• The use of FinFET in low power applications is considered.

• The successful design and realization of the most important analog circuits (Miler op-amp) in a MuGFET technology is presented for the first time.

• We see a solution to the electrostatic discharge (ESD) sensitivity of MuGFETs.

1414

THANKS FOR YOUR ATTENTION

ANY QUESTION?

1515

References:

1. C. Pacha et al., “Circuit Design Issues in Multi-Gate FET CMOS Technologies,” ISSCC Dig. Tech Papers, pp. 420-421, February ., 2006

2. N. Collaert et-al, “A Functional 41-Stage Ring Oscillator Using Scaled FinFET Devuces WIth 25-nm Gate Lengths and 10-nm Fin Widths Applicable for the 45-nm CMOS Node”, IEEE Electron Device Letters, Vol 25, No 8, August 2004, p568-570

3. G. Knoblinger et.al., “Design and Evaluation of Basic Analog Circuit in an Emerging MuGFET Technology”, IEEE SOI Conference, Oct 4-6, 2005

4. C.Russ et al., “ ESD Evaluation of the Emerging MuGFET Technology,” EOS/ESD Symp., pp, 280-289, Sept., 2005