1128 ieee transactions on components, packaging and ... · abstract—silicon platforms with...

1128 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 7, JULY 2012

Silicon Platform With Vertically Aligned CarbonNanotubes for Enhancing Thermal Conduction

in Hybrid Optoelectronic IntegrationSzu-Chieh Chen, San-Liang Lee, Senior Member, IEEE, Hsinyi Lo, Yung-Jr Hung, Member, IEEE,

Kuei-Yi Lee, Charng-Gan Tu, Yen-Ting Pan, and Rajeev J. Ram, Senior Member, IEEE

Abstract— Silicon platforms with high-number-densityvertically aligned carbon nanotubes (VACNTs) on patternedsubstrates are designed and fabricated to provide efficientthermal conduction for hybrid optoelectronic integration anddevice packaging. The simulation shows that the platform canreduce the thermal resistance by >40%, resulting from the helpof the high-thermal-conductivity VACNTs and the increase inthe heat spreading area of the patterned platform geometry. Theplatform can also provide the flexibility in device attachmentand alignment. Applications of this platform to packagedlight-emitting diodes (LEDs) are used to demonstrate thefeasibility of this approach. The experimental results verify thatan increase in the saturation power and optical output power ofLEDs can be obtained by packaging with the VACNT-integratedplatform. The thermal resistance measurement also indicatesthat the proposed platform has lower thermal resistance thanthe planar silicon substrate.

Index Terms— Light-emitting diode (LED), optoelectronicintegration, thermal conduction, vertically aligned carbonnanotube (VACNT).

I. INTRODUCTION

S ILICON substrates have been the platforms foroptoelectronic device packaging due to their thermal

and electrical properties [1]–[3]. They are also the popularplatforms for heterogeneous photonic circuit integrationbecause of the increased microsystem functionality through

Manuscript received June 20, 2011; revised March 18, 2012; acceptedApril 10, 2012. Date of publication May 10, 2012; date of current versionJune 28, 2012. This work was supported in part by the National ScienceCouncil, Taiwan, under Grant NSC97-2221-E-011-077-MY3, and the Ministryof Education, Taiwan, under the Top University Program. Recommended forpublication by Associate Editor C.-P. Chiu upon evaluation of reviewers’comments.

S.-C. Chen is with AU Optronics Corp., Hsinchu 30078, Taiwan (e-mail:[email protected]).

S.-L. Lee was with the Department of Electronic Engineering, NationalTaiwan University of Science and Technology, Taipei 106, Taiwan. He isnow with the Research Laboratory of Electronics, Massachusetts Institute ofTechnology, Cambridge, MA 02139 USA (e-mail: [email protected]).

H. Lo and R. J. Ram are with the Research Laboratory of Electronics,Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail:[email protected]; [email protected]).

Y.-J. Hung, K.-Y. Lee, C.-G. Tu, and Y.-T. Pan are with the Depart-ment of Electronic Engineering, National Taiwan University of Scienceand Technology, Taipei 106, Taiwan (e-mail: [email protected];[email protected]; [email protected]; [email protected]).

C.-G. Tu is with National Taiwan University, Taipei 10617, Taiwan (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2012.2195315

integration with other electronic or photonic circuits [4], [5].Heat conduction of the platform is of critical concern whenit is applied to integrate active devices like high-powerdiode lasers and high-brightness light-emitting diodes (LEDs)[6]–[9]. Poor heat dissipation will result in lower efficiency,shorter lifetime, and wavelength drift for the active devices.Heat conduction is also important for some micro pillaror nanophotonic devices that have larger thermal resistancedue to their device geometry [3]. Taking the packaging ofhigh-brightness LEDs as a specific example, silicon substratesare frequently used to replace the original substrates ofLEDs due to their good thermal conductivity and relativelylow thermal expansion [2]. However, further reduction inthe thermal resistance is still strongly desired due to theeverlasting efforts of obtaining increasing output power andluminous efficacy for LEDs.

Carbon nanotubes (CNTs) are well-known excellent heatspreaders for their high thermal conductivity and goodmechanical strength [10], [11]. They were used as thermalinterface material between a LED module and heat sink[12], [13]. They were also used for flip-chip packaging LEDchips directly on the CNT-metal electrodes over a siliconcarrier [14]. However, the existing ways of using CNTs asheat spreaders usually have poor adhesion between CNTsand adjacent materials, which may impact device yield andreliability. Moreover, heat transfer can be more efficient byplacing CNTs closer to heating sources.

In this paper, we designed and fabricated a platformfor optoelectronic device packaging by integrating verticallyaligned CNTs (VACNTs) onto patterned silicon U-grooves forachieving enhanced thermal conduction and stable mechanicalproperties. The VACNT structure was demonstrated to havehigher thermal conductivity than random CNTs [15], [16]. Weapplied the platform for packaging LED devices to demon-strate the feasibility of the proposed approach. The enhancedthermal conduction from the use of the platform can be verifiedfrom the increased saturation current and output power of theLEDs as well as from the thermal resistance measurement.

II. DESIGN OF VACNT-ON-SILICON (VOS) PLATFORM

Fig. 1(a) shows the schematic of the platform. VACNTsare grown on a silicon trench to provide heat spreadingfor the bonded device chip. A thin dielectric layer betweenVACNTs and silicon substrate is usually needed to eliminate

2156–3950/$31.00 © 2012 IEEE

CHEN et al.: SILICON PLATFORM WITH VACNTs FOR ENHANCING THERMAL CONDUCTION 1129

(a) (b)

Fig. 1. Cross-sectional view of LED packaging on (a) VoS platform and (b) reference silicon platform.

TABLE I

PARAMETERS FOR NUMERICAL THERMAL MODELING

Component Thermal conductivity (W/mK)Dimensions

(L × W × T )(mm3)

LEDsubstrate

Si 148 0.3 × 0.3 × 0.2

Submount

Silicon 148

1.6 × 0.9 × 0.2SiO 1.5

Silver epoxy 0.68

AuSn 60

CNTs 150–600

Heat source has a heat flux of 0.8 W.Bottom boundary: perfect heat conductor with a heat transfer coefficientof 150 000 W/m2K.Surrounding boundary: static air with a heat transfer coefficient of220 W/m2K.

current leakage to the substrate. The device chip is bondedto the platform by the bonding pads on the platform surface,which provides firm adhesion for the chip to the platform.Since CNTs were known to have larger thermal conductivitythan silicon [10], a larger volume of CNTs embedded in theplatform leads to a lower thermal resistance for the platform.For comparison, a reference silicon platform with the samethin dielectric layer on top is shown in Fig. 1(b).

The platform can provide not only the enhancement onthermal conduction but also the flexibility in device attachmentand alignment. Owing to their mechanical flexibility, the CNTsdo not need to have precise length as long as they can touchthe bottom of the device chip. This platform can accommo-date devices with nonplanar surface, which occurs often inheterogeneous photonic circuit integration. For example, fordevices with p-type and n-type contacts on the same side butwith different heights, it would be difficult to flip-chip bondthe device on planar silicon substrate to obtain good thermaland electric conduction to both contact areas. The bendabilityalso provides flexibility for vertical alignment of the devicechip. For example, when the platform is used in combinationwith the silicon optical bench for packaging a ridge waveguidelaser with a fiber [1], the laser can be flip-chip bonded to retaingood vertical alignment to the fiber, in addition to the goodthermal conduction provided by the CNTs.

The temperature distributions and thermal resistance of theVoS platform were simulated by using the finite elementanalysis. A silicon monoxide (SiO) film of 500-nm thicknessis used as the dielectric layer. The thermal conductivity of

CNTs is varied from 150 to 600 W/mK. For the thermal mod-eling assumption, the boundary environment on the bottomof submount is a perfect heat conductor with a heat transfercoefficient of 150 000 W/m2K and an area of 1.44 mm2 (sameas the size of submount) for heat dissipation. The boundarysurrounding the chip/submount is static air with no forced airflow. The volume heat source is on the surface of device chipwith a heat flux of 0.8 W. Thermal resistance is defined asthe ratio of the temperature difference between LED junctionand surface mounted device (SMD) leadframe over the heatflux. The temperature for the LED junction is extracted fromthe average value of the top surface while the temperaturefor SMD leadframe is from the average value of the bottomsubstrate. The thermal conductivities and device dimensionsused in the simulation are listed in Table I. Although the heattransfer coefficient changes with the temperature, the calcu-lated thermal resistance through convection (>3000 K/W) ismuch larger than that of LED and submount (<15 K/W). Itreveals that the dominant heat transfer is through the substrateand the temperature dependence of the natural convective heattransfer only results in minor perturbations to the simulation.

The simulated thermal resistance for the platform is depictedin Fig. 2. The depth ratio for the VoS platform is defined asthe ratio of the depth of the U-groove where CNTs reside overthe thickness of the substrate. The reference silicon platformwith the same thickness of SiO, as shown in Fig. 1(b), isalso simulated for comparisons. The heat source has an areaof 300 µm2 × 300 µm2. The VoS platform and the referencesilicon platform have the same dimensions of 1.6 mm (length),0.9 mm (width), and 200 µm (thickness). Fig. 2(a) showsthe variation of the thermal resistance with the CNT arearatio, which is the ratio of the top area of the U-groove,W2

t , over the area of the heat source. The slope of theU-groove was determined by the wet chemical etching(54.75°). The simulated thermal resistance is normalized tothat of the reference platform (12.9 K/W). The results indicatethat >40% reduction in thermal resistance can be achievedwith an area ratio of 0.8 and a CNT thermal conductivityof 300 W/mK, which is obtainable for single- and multiwallCNTs [10], [11]. The enhancement on the thermal conductionby the VoS platform results not only from the replacement ofa portion of silicon substrate with high-thermal-conductivityVACNTs but also from the increased heat spreading due tothe platform geometry. The VoS platform increases the surfacearea of the SiO layer, thereby reducing the thermal resistance.Fig. 2(b) shows that the reduction in thermal resistance can


(b)

(a)

Fig. 2. Simulated thermal resistance versus (a) CNT area ratio and (b) depthratio for the VoS platform.

(a)

(b)

Fig. 3. Simulated temperature distribution for devices packaged on (a) VoSand (b) planar silicon platforms.

be enhanced by increasing the depth of the U-groove andthe height of VACNTs, especially for using high-thermal-conductivity CNTs.

Fig. 3 compares the temperature distribution for the devicepackaging with and without using the VoS platform. In thesimulation, the LED chip size is 300 µm3 × 300 µm3×200 µm3 with a thin layer of heat source on the top surface.

Fig. 4. Fig. 4. Process flow of the proposed LED packaging configuration:(a) deposition of silicon dioxide mask, (b) etching of silicon U-groove,(c) deposition of SiO, Al/Fe, and patterning Ti/Au, and (d) growth of VACNTs.

The substrate of the LED chip is assumed to be silicon.Two-micrometer-thick Au–Sn solder is applied between theLED and CNTs for chip bonding. The thermal conductivityof Au–Sn is assumed to be 60.0 W/mK in the simulation. Theheat source dissipates 0.8 W, and the ambient temperatureis assumed to be 25 °C. It can be clearly seen from thetemperature distribution that the VoS platform can provideexcellent heat conduction with the help of heat spreading bythe CNT. The heat is effectively conducted by VACNTs to theU-groove sidewalls, which have a larger surface area than theplanar silicon surface.

III. FABRICATION OF VOS PLATFORM

The VoS platform can be easily fabricated with the pro-cedures shown in Fig. 4. Silicon dioxide is first depositedon the 200-µm-thick silicon substrate. After transferringU-groove patterns into silicon dioxide by photolithography andCF4 plasma etching, the sample is immersed into potassiumhydroxide solution with a temperature of 80 °C for 50 minto etch silicon. The opening area and the depth of U-grooveare around 210 µm2 × 215 µm2 and 60 µm, respectively.The wet etching condition is optimized for obtaining smoothU-groove surface. A 500-nm-thick SiO film is then depositedover the entire submount for isolating the current from flowingthrough the substrate.

The VACNT growth is carried out by using the ther-mal chemical vapor deposition (TCVD) with an Al (5 nm)/Fe (3 nm) thin film as the buffer layer and catalyst, which isdeposited over the entire submount. Patterned Ti (50 nm)/Au(500 nm) metal pads are then deposited as the mask forblocking the growth of VACNTs outside the U-groove areaand also serving as the ground electrodes. The TCVD growthis performed by first annealing the sample at an elevatedtemperature of 750 °C and a pressure of 4 × 10−2 torr for60 min and then pouring in C2H2 for 7 min. The SEM photo


(a)

(b)

Fig. 5. (a) SEM photo for the grown CNTs on the U-groove. (b) TEM photoof a single CNT.

shown in Fig. 5(a) indicates that VACNTs with high wiredensity (around 109 wires per square millimeter) can be grownon the U-groove. The CNTs are multiwalled with a diameterof around 16 nm from the TEM photos, as shown in Fig. 5(b).

IV. APPLICATIONS TO LED PACKAGING

To demonstrate the enhanced heat conduction with the VoSplatform, red-emitting LED chips of 300 µm2 × 300 µm2

size are bonded onto the VoS platforms by using Au–Snsolder. The LED chips are top-emitting with a substratethickness of 200 µm. The assembly is then bonded onto analuminum heat slug and a SMD leadframe, as illustrated inFig. 6(a). The Al heat slug has a surface area of 12.56 mm2

and a thickness of 1 mm. For reference, LED chips werealso directly bonded to planar silicon substrates (with thinSiO layer) and then attached to the heat slugs and leadframes. Two types of bonding materials, Au–Sn solder orsilver epoxy, are used for the reference samples. There existfluctuations in the light output characteristics of the LEDchips before packaging. In order to make fair comparisons ofthe LED performance after packaging, tens of samples werepackaged on each type of platform. The statistical analysisof the LED characteristics is shown in Fig. 7.

Since the VACNT arrays are grown only inside theU-groove, the LED chips can be firmly bonded to the sub-mount to overcome the adhesion issue between VACNTs andsilicon substrate [9]. The bonding quality between LED chipsand submounts can be maintained as long as an appropriateplanar surface area on the VoS platform is allocated forbonding. In our experiments, the VACNT area is only 54%of that of the LED chip for achieving high packaging yield.The area ratio of the VACNTs can be further optimized toobtain both good thermal conduction and bonding strength.

The light–current–voltage (L–I–V ) characteristics aremeasured by applying a pulse current of 4 s on-time and3 s off-time on a stage without heat sink. The optical powerwas measured with a photodetector attached to an integrat-ing sphere. Fig. 7(a) compares the results of the packagedLEDs on different submounts, including the VoS platform,Si substrate with Au–Sn solder, and Si substrate with silverepoxy. The optical spectra shown in the inlet indicate thatthe light emission has a peak wavelength of 626 nm. Thevariation of the packaged LED characteristics is partiallydue to the performance variation of original LED chips. Theaverage saturation current and maximum output power forthe silver epoxy packaged LEDs are around 120 mA and26 mW, respectively. For Au–Sn packaged LEDs, the averagesaturation current and maximum output power are around160 mA and 28 mW, respectively. The LEDs packaged withthe VoS platform can provide an average maximum outputpower of around 29 mW and an average saturation currentof 170 mA. It can be clearly seen that the LEDs packagedwith epoxy bonding have lower output power. Though theperformance of the other two packaging types is close, theLEDs packaged on the VoS Platform have better performancethan the LEDs packaged with planar silicon substrate, in termsof the average output power. It will be shown later that thethermal resistance difference is small between the LEDs pack-aged on the VoS platforms and planar substrates with Au–Snbonding. The resultant temperature difference is thus smallsince the power consumption of the LEDs is only 0.8 W.

Since the optical output power is only a small portion ofthe injected electric power, the thermal heating effect can beobserved from the analysis of the saturation current. For theLED packaging on planar silicon substrate with silver epoxy,all samples have lower than 120 mA of saturation current.This can be attributed to the low thermal conductivity ofsilver epoxy. The enhanced thermal conduction by using CNTscan be verified by comparing the saturation current betweenthe packaged LEDs on the VoS platform and planar siliconsubstrate with Au–Sn solder. Fig. 7(b) shows the histogram ofthe saturation current for both type of packages. The saturationcurrent values are extracted at the roll-off points of light–current curves of all the devices shown in Fig. 7(a). 55% ofthe VoS-packaged LEDs have a saturation current equal to orlarger than 160 mA, compared to 26% for the LEDs packagedon planar silicon substrate.

To verify the improvement on thermal conduction by VAC-NTs, the LED junction temperature and leadframe temperaturewere measured by using microthermocouples, as indicated inFig. 6(a), which have a temperature resolution of 0.01 Kand a data deviation of around 0.1 K [17]. The LEDs arebiased at 250 mA to enhance the thermal heating effects.Current/voltage source has a voltage fluctuation of <10 µVand a current fluctuation of <1 µA. Device dimensions areobtained from the Hitachi scanning electron microscope whichhas a resolution of 10 nm at 3 kV. During measurements,the sample is attached to a large heat sink. The sampleis covered to block the airflow so that the heat transferthrough convection is reduced. Besides, thermal resistanceto air (by assuming natural convection) is much larger than


(a) (b)

Fig. 6. (a) Schematic diagram and (b) photograph of the packaged LED module.

TABLE II

MEASURED TEMPERATURES AND THERMAL RESISTANCES

Packageplatform

Heatrate(W)

T j (°C) TSMD (°C)Rth(Meas.)(K/W)

Rth(Cal.)(K/W)

VoS 0.765 55.5 30.8 32.3 24.5Silicon+Au-Sn 0.785 58.5 30.7 35.4 28.1Silicon+silver

epoxy 0.75 66.7 30.7 48.0 38.8

that through the substrate. The measured temperatures and thecorresponding thermal resistances are summarized in Table II.The thermal resistance of the whole LED module is measuredto be 48.0 and 35.4 K/W for the packaging on planar siliconsubmounts with silver epoxy and Au–Sn solder, respectively.In contrast, the thermal resistance of the LED module pack-aged on the VoS platform has a thermal resistance of 32.3 K/W.The reduced thermal resistance for the VoS platform indicatesthat the VACNTs provide both good thermal contact andenhanced thermal conduction.

For comparison, the thermal resistance of the packagedLED module, including the LED chip, submount, and thebonding material between the LED and submount, is sim-ulated to be 38.8 and 28.1 K/W for the reference modulesbonded with silver epoxy and Au–Sn solder, respectively.The calculated thermal resistance for the LED bonded onthe VoS platform is 24.5 K/W, providing that the thermalconductivity of the VACNT is 300 W/mK. The U-grooves usedin the experiments have the dimension of 0.54 area ratio and0.3 depth ratio. The simulated thermal resistance of the LEDchip is 14.8 K/W. Therefore, the theoretical value of thethermal resistance for the planar silicon platform and VoSplatform is 13.3 (12.9 without Au–Sn) and 9.4 (9.0 with-out Au–Sn) K/W, respectively. There exists about the same(7–9 K/W) difference between the measured and simulatedthermal resistance of the whole module for the three types ofpackaged modules. We attribute the difference to the thermalresistance of the bonding materials (silver epoxy) between thesubmount and the SMD leadframe, which is not included in thesimulation due to its uncertain thickness. We also accountedthe orthotropic property of bulk thermal conductivity forVACNTs in our simulation model but only found slightlyincreased overall thermal resistance (∼0.07 K/W) of packagedLEDs. This indicates that the thermal resistance of the VoS

(a)

(b)

Fig. 7. (a) L–I–V characteristics of the final packaged LED device and(b) histogram of the saturation current for the LEDs packaged on the VoSplatform (Au–Sn+CNT) and on planar silicon substrate with Au–Sn solder.

platform is dominated by the axial heat dissipation of theCNTs. Thus, the effect of the orthotropic property of CNTs isnegligible for the overall thermal resistance.

The reduction in the thermal resistance can have significanteffects when the VoS platform is applied to package high-brightness LEDs, which have relatively large device areas andconsume a large power (>10 W). The large device area allowsthe use of a larger area ratio to incorporate VACNTs, whichwill result in a larger reduction in thermal resistance, as canbe seen from Fig. 2(a). The reduction in thermal resistance iscritical for ensuring long lifetime for the high power operation.


V. CONCLUSION

The packaging with the VoS platform can benefit the deviceperformance more when the heat source is placed closer to theCNTs. This can usually be performed by using the flip-chipbonding technique. For example, the platform can be used forflip-chip bonding of a high-power edge-emitting laser or laserarray such that the heat generated in the active layers canbe effectively removed by the CNTs. Another example is theflip-chip packaging of high-power blue LEDs with transparentsubstrates. The ratio of thermal resistance reduction will belarger than the case demonstrated here since the heat willbe conducted directly to the VoS platform without passingthrough the LED substrate.

In conclusion, we have demonstrated both by simulationand experiments that the VoS platform can provide excellentheat spreading for packaged photonic devices. The simulationindicates that greater than 45% of reduction in the thermalresistance can be achieved by using the VoS platform, bycomparing to the use of planar silicon substrate. The applica-tion of this platform to packaged LEDs verifies that the VoSplatform can provide excellent heat conduction for the LEDchips, leading to an increased saturation current and enhancedoutput power. Thermal resistance of VACNT packaged LEDsis measured to be 32.3 K/W, lower than the values for themodules packaged with the planar silicon substrates. Thethermal resistance of the VoS platform can be further reducedby optimizing the platform geometry to increase the volumeratio of VACNTs and improve the thermal conductivity ofVACNT.

ACKNOWLEDGMENT

The authors would like to thank M.-J. Wu and J.-C. Chen ofNational Central University, Jhongli, Taiwan, and J.-C. Su ofNational Taiwan University of Science and Technology, Taipei,Taiwan, for their help in part of the packaging process andmeasurement.

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Szu-Chieh Chen received the B.S. degree fromChung Yuan Christian University, Taoyuan, Taiwan,and the M.S. degree from the National Taiwan Uni-versity of Science and Technology, Taipei, Taiwan,in 2007 and 2009, respectively, both in electricalengineering.

She is currently a Senior Engineer devoted to TFT-LCD and touch panel design with AU OptronicsCorp., Hsinchu, Taiwan. Her current research inter-ests include thermal conduction in optoelectroniccomponents.

San-Liang Lee (SM’07) received the B.S. degree inelectronics engineering from National Chiao TungUniversity, Hsinchu, Taiwan, the M.S. degree inelectrical engineering from National Taiwan Univer-sity, Taipei, Taiwan, and the Ph.D. degree in electri-cal and computer engineering from the University ofCalifornia at Santa Barbara, Santa Barbara, in 1984,1986, and 1995, respectively.

He joined the faculty of the Department of Elec-tronic Engineering, National Taiwan University ofScience and Technology (NTUST), Taipei, in 1988,

and became a Full Professor in 2002. He was the Chairman with theDepartment of Electronic Engineering, NTUST. He served as the Dean ofAcademic Affairs Office, NTUST, from 2008 to 2010. He was the Director ofthe Program Office for the National Innovative Education Program on ImageDisplay Technology, sponsored by the Ministry of Education, Taipei, from2005 to 2009. He is currently a Visiting Scientist with the Research Laboratoryof Electronics, Massachusetts Institute of Technology, Cambridge, taking asabbatical leave from NTUST. He has published more than 180 refereed papersin international journals and conferences and holds 30 patents. His currentresearch interests include semiconductor optoelectronic components, photonicintegrated circuits, nanophotonics, and optical networking technologies.

Dr. Lee has been serving as the Electronic Section Editor of the SCI indexedjournal, the Journal of the Chinese Institute of Engineers, since 2007.


Hsinyi Lo received the B.S. degree from NationalTaiwan University, Taipei, Taiwan, in 2004, and theM.S. and Ph.D. degrees from Carnegie Mellon Uni-versity (CMU), Pittsburgh, PA, in 2005 and 2009,respectively, all in mechanical engineering.

She was an Intern with IBM Zurich Research Lab-oratory, Zurich, Switzerland, in 2008. Her researchfocus was probe-based study on phase change mater-ial films. While at CMU, her focus was phase changematerials and conductive atomic force microscopyfor reconfigurable RF circuits. Her current research

interests include the study of material uniformity thermoelectric materials,using thermoreflectance technique and material property extraction fromthermal images.

Yung-Jr Hung (S’07–M’10) received the B.S. andPh.D. degrees in electrical engineering from theNational Taiwan University of Science and Technol-ogy (NTUST), Taipei, Taiwan, in 2005 and 2010,respectively.

He was a Visiting Scholar with the Department ofElectrical and Computer Engineering, University ofCalifornia at Santa Barbara, Santa Barbara, in 2009,partly supported by the National Science Council,Taiwan. He is currently a Post-Doctoral Fellow withthe Department of Electronic Engineering, NTUST.

He has authored or co-authored 47 refereed papers in international journalsand conferences. His current research interests include semiconductor opto-electronic devices, nanostructure-based solar cells, and photonic integratedcircuits.

Kuei-Yi Lee received the B.S. degree in physics andthe M.S. degree in optical sciences from NationalCentral University, Jhongli, Taiwan, in 1994 and1996, respectively, and the Ph.D. degree in electronicengineering from Osaka University, Osaka, Japan, in2002.

He is currently an Associate Professor with theDepartment of Electronic Engineering, National Tai-wan University of Science and Technology, Taipei,Taiwan. His current research interests include thinfilms and nanotechnology, working on the synthesis,

analysis, and design of nanomaterials.

Charng-Gan Tu received the B.S. degree in elec-tronic engineering from the National ChanghuaUniversity of Education, Changhua, Taiwan, andthe M.S. degree in electrical engineering from theNational Taiwan University of Science and Technol-ogy, Taipei, Taiwan, in 2008 and 2010, respectively.

He is currently a Doctoral Student with NationalTaiwan University, Taipei. His current research inter-est includes metal organic chemical vapor depositiongrowth and fabrication of nitride based light-emittingdiodes.

Yen-Ting Pan received the B.S. degree in electricalengineering from National Taiwan Ocean Univer-sity, Keelung, Taiwan, in 2001, and the M.S. andPh.D. degrees in electronic engineering from theNational Taiwan University of Science and Technol-ogy (NTUST), Taipei, Taiwan, in 2003 and 2008,respectively.

He is currently a Post-Doctoral Fellow withthe Department of Electronic Engineering, NTUST.His current research interests include the designand fabrication of semiconductor optoelectronic

components.

Rajeev J. Ram (SM’07) received the B.S. degreein applied physics from the California Institute ofTechnology, Pasadena, and the Ph.D. degree in elec-trical engineering from the University of Californiaat Santa Barbara, Santa Barbara, in 1991 and 1997,respectively.

He joined the Faculty with the Department of Elec-trical Engineering and Computer Science, Massa-chusetts Institute of Technology (MIT), Cambridge,in 1997, and was promoted to Associate Professorin 2000. He is currently an Associate Director with

the Research Laboratory of Electronics (RLE), MIT, and the Director ofRLE’s affiliated Center for Integrated Photonic Systems. His current researchinterests include physical optics and electronics, including the developmentof novel components and systems for communications and sensing, novelsemiconductor lasers for advanced fiber optic communications, and studies offundamental interactions between electronic materials and light.

1128 ieee transactions on components, packaging and ... · abstract—silicon platforms with...

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