13 nyquist ad_johns & martin slides
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Nyquist-Rate A/D Converters
David Johns and Ken MartinUniversity of Toronto
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Analog to Digital ConvertersLow-to-Medium
Speed,High Accuracy
Medium Speed,Medium Accuracy
High Speed,Low-to-Medium
Accuracy
Integrating Successiveapproximation
Flash
Oversampling
(not Nyquist-rate)
Algorithmic Two-step
Interpolating
Folding
Pipelined
Time-interleaved
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Integrating Converters
• Low offset and gain errors for low-speed applications
• Small amount of circuitry
• Conversion speed is 2 N+1 times 1/T clk
(Vin is held constant during conversion.)
Control
logicCounter
b1 b2 b3
b N
Clock
f clk 1
Tclk -----------=
S2
S1Vin –
Vref
S1S2
R 1
C1
Vx
Bout
Comparator
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Integrating Converters
• Count at end of T 2 is digital output
• Does not depend on RC time-constant
Time
Vx
T1
Phase (I) Phase (II)
Vin1 –
Vin2 –
Vin3 –
T2 (Three values for three inputs)
(Constant slope)
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Integrating Converters
• Notches the input frequencies which are multiples of 1/T 1
10 100
0
–10
–20
–30
60 120 180 240 300
–20 dB/decade slopeH f ( )
(dB)
Frequency (Hz)
(Log scale)
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Successive-Approximation Converters
Sample
Start
Stop
No
Yes
No
Yes
b i 1= b i 0=
Signed input
V in V D/A>
V in V D/A, 0 i, 1= =
V D/A V D/A V re f 2 i 1+ ⁄ +→ V D/A V D/A V re f 2 i 1+ ⁄ ( ) – →
i i 1+→
i N≥
• Makes use of binary search algorithm
• /Requires N steps for N-bit converter
• Successively “tunes” a signal untilwithin 1 LSB of input
• Medium speed
• Moderate accuracy
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DAC Based Successive-Approximation
• Adjust until within 1 LSB of
• Start with MSB and continue until LSB found • D/A mainly determines overall accuracy • Input S/H required
S/H
D/A converter
Successive-approximation register (SAR) and control logic
b1 b2 b N
Bout
V D/A
Vin
Vref
V D/A V in
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Charge Redistribution A/D
CC2C4C8C16C
1. Sample mode
CC2C4C8C16C
2. Hold mode
CC2C4C8C16C
3. Bit cycling
SAR
SAR
SAR
b1 b2 b3 b4 b5 s 3
s1
s2
b1 b2 b3 b4 b5 s 3
s1
s2
b1 b2 b3 b4 b5 s 3
s1
s2
Vx 0≅
Vx Vin – =
Vx Vin – Vref
2-----------+=
Vin Vre f
Vin Vref
Vin Vref
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Charge Redistribution A/D • McCreary, 75 • Combines S/H, D/A converter, and difference circuit
• Sample mode: Caps charged to , compar reset.
• Hold mode: Caps switched to gnd so
• Bit cycling: Cap switched to . If cap left
connected to and bit=1. Otherwise, cap back to gndand bit=0. Repeat times
• Cap bottom plates connected to side to minimize parasitic capacitance at . Parasitic cap does not causeconversion errors but it attenuates .
V in
V x V in – =
V ref V x 0<
V ref
V ref
V x V x
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Algorithmic (or Cyclic) A/D Converter
Sample V = V in, i = 1
Start
V > 0
V → 2(V – V ref /4) V → 2(V + V ref /4)
i → i + 1
i > N
Stop
No
Yes
No
Yes
b i 1= b i 0=
Signed input• Operates similar to successive-
approx converter
• Successive-approx halves ref voltageeach cycle
• Algorithmic doubles error each cycle(leaving ref voltage unchanged)
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Ratio-Independent Algorithmic Converter
• McCharles, 77; Li, 84 • Small amount of circuitry — reuse cyclically in time
• Requires a high-precision multiply by 2 gain stage
S/H
S/HX2
Cmp
Vref /4
–Vref /4
VinShift register
Out
Gain amp
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Ratio-Independent Algorithmic Converter
• Does not rely on cap matching• Sample input twice using C 1; hold first charge in C 2 and
re-combine with first charge on C 1
CmpVerr
C1
Q1
C2
1. Sample remainder and cancel input-offset voltage.
CmpVerr
C1
Q1
C2
2. Transfer charge Q 1 from C 1 to C 2.
Q1
CmpVerr
C1
Q2
C2
3. Sample input signal with C 1 again
Q1
CmpVerr
C1
Q1+Q2
C2
4. Combine Q 1 and Q 2 on C 1, and connect C 1 to output.
Vout = 2 Verr
after storing charge Q 1 on C 2.
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Flash (or Parallel) Converters • Peetz, 86; Yoshii, 87; Hotta, 87; and Gendai, 91
Vref
Vin
(2 N –1) to N
encoder
N digitaloutputs
Over range
Comparators
R
R
R
R
R
R
R
V r1
V r2
V r3
V r4
V r5
V r6
V r7
R 2----
R 2 ⁄
• High-speed
• Large size and power hungry
• 2 N comparators
• Speed bottleneck usually large capload at input
• Thermometer code out of comps• Nands used for simpler decoding
and/or bubble error correction
• Use comp offset cancellation
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Issues in Designing Flash A/D Converters • Input Capacitive Loading — use interpolating arch. • Resistor-String Bowing — Due to I in of bipolar comps —
force center tap (or more) to be correct.
• Signal and/or Clock Delay — Small arrival diff in clockor input cause errors. (250MHz 8-bit A/D needs 5psmatching for 1LSB) — route clock and V in together withthe delays matched [Gendai, 1991]. Match capacitive
loads • Substrate and Power-Supply Noise — and 8-
bit, 7.8 mV of noise causes 1 LSB error — shield clocksand use on-chip supply cap bypass
• Flashback — Glitch at input due to going from track tolatch mode — use preamps in comparators and matchinput impedances
V ref 2 V=
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Flash Converters — Bubble Errors • Thermometer code should be 1111110000 • Bubble error (noise, metastability)— 1111110100 • Usually occurs near transition point but can cause gross
errors depending on encoder
• Can allow errors in lower 2 LSB but have MSBs encoderlook at every 4th comp [Gendai, 91]
(2N–1) to Nencoder
N digitaloutputs
Vin
Vri
… …
…
… …
[Steyaert, 93]
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Reduced Auto-Zeroing • Tsukamoto et al, ISSCC/96 • Spalding et al, ISSCC/96 • Reduce the auto-zero portion of conversion
— auto zero when not performing conversion — add one more comparator and ripple up auto-zero
Advantages
• Lower power — less current drawn from ref string • More speed — more time for conversion
Disadvantage
• 1/f noise not rejected as much
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Two-Step A/D Converters
• High-speed, medium accuracy (but 1 sample latency) • Less area and power than flash • Only 32 comparators in above 8-bit two-step
• Gain amp likely sets speed limit • Without digital error correction, many blocks need at least
8-bit accuracy
4-bit
A/D4-bitD/A 16
First 4 bits
Vin
Gain amp
V1
Vin
VqMSB
4-bit
A/DLSB
Lower 4 bits b1 b2 b3 b4, , ,( ) b5 b6 b7 b8, , ,( )
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Digital Error Correction
• Relaxes requirements on input A/D• Requires a 5-bit 2nd stage since V q increased• Example, see [Petschacher, 1990].
S/H1
4-bit
A/D
S/H2
4-bit
D/A 8 S/H3
Error correctionD
8 bits
Digital delay
4 bits
5 bits
Vin
Gain amp
(4-bit accurate)(8-bit accurate)
(5-bit accurate)
(5-bit accurate)
(8-bit accurate)
(8-bit accurate)
V1
Vin
VqMSB
5-bit
A/DLSB
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Interpolating A/D ConvertersVref 1 V=
Vin
R
R
R
R
0.75 V
0.5 V
0.25 V
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
Digitallogic
b1 b2 b3 b4
(Overflow)
Inputamplifiers
Latchcomparators
V1
V2
V3
V4
V2a
V2b
R R R R
R R R R
V2c
R
R
R
R
R R
R
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
• Goodenough, 1989
• Steyaert, 1993
• Kusumoto, 1993
• Use input amps toamplify input aroundreference voltages
• Latch thresholds lesscritical
• Less cap on input (faster than flash)
• Match delays to latches
• Often combined withfolding architecture
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Interpolating Converters
Vin1.0
(Volts)
(Volts)
0.750.50.2500
5.0
Latch thresholdV1
V2
V2a
V2b V2c
9
I1 I2a I2b I2
9
33
33
33
(Relative width sizing shown)(All lengths same)
current interpolation
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Folding A/D Converters
Folding block
Folding block
2-bitMSB A/Dconverter
Latch
Latch
Latch
Latch
Digitallogic
Vin
b1
b2
b3
b4
V1
V2
V3
V4
Vin
V 1
Vin
V 2
Vin
V3
Vin
V 4
Threshold
Threshold
Threshold
Threshold
Folding block responses
1(Volts)
(Volts)V r
416------ 8
16------ 12
16------ 16
16------, , ,
=
V r 3
16------ 7
16------ 11
16------ 15
16------, , ,
=
V re f 1 V=
Vr 2
16------ 6
16------ 10
16------ 14
16------, , ,
=
V r 1
16------ 5
16------ 9
16------ 13
16------, , ,
=
416------ 8
16------ 12
16------ 10
0
316------
716------
1116------
1516------
216------ 6
16------ 10
16------ 14
16------
116------ 5
16------ 9
16------ 13
16------
1
Folding block
Folding block
• Reduce number of latches using folding
• Save power and area
• Similar concept to 2-step
• Folding rate of 4 shownfor 4 bit converter
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Folding Circuit
I b I b I bI b
Vin
V out
R 1 R 1
Vr1Vr2 Vr3 Vr4
V in
V out
VCC
VEE
VCC VBE –
VCC VBE – I b R 1 –
V r1 V r2 V r3 V r4
(b)
(a )
Q1 Q 2VaV b
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Folding with Interpolation
Folding block
Folding block
2-bitMSB A/Dconverter
Latch
Latch
Latch
Latch
Digitallogic
Vin
b1
b2
b 3
b 4
V1
V2
V3
V4
Vin
V1
Vin
V2
Vin
V3
VinV 4
Threshold
Threshold
Threshold
Threshold
Folding-block responses
1(Volts)
(Volts)
Vr
316------ 7
16------ 11
16------ 15
16------, , ,
=
Vref 1 V=
Vr 1
16------ 5
16------ 9
16------ 13
16------, , ,
=
416------ 8
16------ 12
16------
100
316------ 7
16------ 11
16------ 15
16------
216------ 6
16------ 10
16------ 14
16------
116------ 5
16------ 9
16------ 13
16------
R
R
V4
V4
V4
R R
• Folding usually used
with interpolation• Reduces input cap (
• Without interp, sameinput cap as flash
• [van Valburg, 1992]
• [van de Grift, 1987]
• [Colleran, 1993]
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Pipelined A/D Converters
D1
Q1
D N-2
Q N-1
D N
Q N
D1
Q1D1
Q1
D N-2
Q N-1
1-bitDAPRX
1-bitDAPRX
1-bitDAPRX
1-bitDAPRX
Vin
N –
1 - b
i t s h i f t r e g
i s t e r
Analog pipeline (DAPRX - digital approximator)
b 1
b 2
b N
b N 1 –
S/H
2
Cmp
–V ref/4
Vref/4
Vi–1
Vi
b i
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Time-Interleaved A/D Converters [Black, 80]
• Use parallel A/Ds and multiplex them• Tone occurs at fs/N for N converters if mismatched• Input S/H critical, others not — perhaps different tech for input S/H
S/H
S/H
S/H
S/H
S/H
N-bit A/D
N-bit A/D
N-bit A/D
N-bit A/D
Dig.mux
Digitaloutput
f 2
f 3
f 4
f 1
f 0
Vin