13716_2 metastability

8/7/2019 13716_2 metastability

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Advanced Digital DesignAdvanced Digital DesignMetastabilityMetastability

by A. Steininger and M. DelvaiVienna University of Technology


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Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 2

OutlineOutline

What is metastabilityWhat is metastability

Effects and ThreatsEffects and Threats

The unavoidabilityThe unavoidability

MTBU estimationMTBU estimation

CountermeasuresCountermeasures TrendsTrends


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Digital LogicDigital Logic

The output of a digital logic gateThe output of a digital logic gatealways assumes a defined logic levelalways assumes a defined logic level

The undefined (forbidden) voltageThe undefined (forbidden) voltage

range in between is assumed onlyrange in between is assumed only during transition (very shortly)during transition (very shortly)

for undefined input levels (!)for undefined input levels (!)

1

0


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Important RemarksImportant Remarks

Specified behavior of a component canSpecified behavior of a component canbe expected only on condition of itsbe expected only on condition of its

environmentenvironment behaving as specified.behaving as specified.

Digital levels are represented byDigital levels are represented by

analoganalog

voltages. Also the transistorsvoltages. Also the transistors

inside the gates are inherentlyinside the gates are inherently analoganalog

elements. We just use a digitalelements. We just use a digital

abstractionabstraction, since the gates are, since the gates arespecified for a digital environment.specified for a digital environment.

Once generated, undefined logic levelsOnce generated, undefined logic levels

have the potential tohave the potential to propagatepropagate


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Inverter ExampleInverter Example

analog transferanalog transfer

characteristicscharacteristics

undefined inputundefined input

level may lead tolevel may lead toundefined outputundefined output

levellevel

propagation ofpropagation of

undefined levelundefined level

uin

uoutInverter-

characteristics

BUT: No generation of undefined levelsBUT: No generation of undefined levels

(for defined inputs)(for defined inputs)


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Observation:Observation: An input transition during theAn input transition during the

decision window leads to an (unbounded)decision window leads to an (unbounded)

increase of clock-to-output delayincrease of clock-to-output delay

tclk2out

tclk2out,nom

tclk2datatsetup thold0

CLK

D

Response Time of a FFResponse Time of a FF

off-spec


7/41Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 7

Behavior during DelayBehavior during Delay

A data transition during the setup/holdA data transition during the setup/holdwindow violates the environment speci-window violates the environment speci-

fications. Consequently the output doesfications. Consequently the output does

not behave as specified. Possibilitiesnot behave as specified. Possibilities

delayed but proper transitiondelayed but proper transition may cause timing problemsmay cause timing problems

creeping through undefined rangecreeping through undefined range

generates long undefined levelgenerates long undefined level oscillationoscillation

generates erroneous transitionsgenerates erroneous transitions


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Metastability: CreepingMetastability: Creeping

1

2

3

4

5

1 2 3 4 5

1

1

Inv 1

Inv 2

ue,2 =ua,1

ue,1 = ua,2

stable (HI)

stable (LO)

metastablemetastable

A


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Physical EquivalentPhysical Equivalent

Ball may remain on top (metastable) forBall may remain on top (metastable) forunbounded timeunbounded time

A small disturbance causes the ball to fall inA small disturbance causes the ball to fall in

either directioneither direction

normaloperation:sufficient

impulserolls ballover hill

problemcase:insufficient

impulse


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CLK

D

Q

D Q1

1

1

Why a Setup/Hold Time?Why a Setup/Hold Time?

When swiching aWhen swiching alatch fromlatch from

transparent totransparent to

hold the feedbackhold the feedback

path must bepath must bestable.stable.

Otherwise weOtherwise we

capture acapture a

transition, thustransition, thusgenerating agenerating a

lasting undefinedlasting undefined

levellevel


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Why voilate Setup/Hold?Why voilate Setup/Hold?

in a closed synchronous system noin a closed synchronous system noviolations will occurviolations will occur

BUT: no system is really closedBUT: no system is really closed

non-synchronous interfacesnon-synchronous interfaces clock domain boundariesclock domain boundaries

fault effectsfault effects (single-event upsets)(single-event upsets)

off-spec operationoff-spec operation (temp, VCC, frequency)(temp, VCC, frequency)


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asynchronous event

setup/hold

clock period Tclk

dec. win. T0

probability ofsetup/hold violation

Asynchronous InputsAsynchronous Inputs

00

>=

c lk

v io la t e

T

TP


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CLK 1(Ref)

CLK 2

A

Multiple Clock DomainsMultiple Clock Domains

arbitrary phase relation setup/hold violation inevitable

(fundamentally!)


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Metastability: ThreadMetastability: Thread

propagationpropagation undefined logic level at input mayundefined logic level at input may

produce undefined outputproduce undefined output

Byzantine InterpretationByzantine Interpretation thresholds of different inputs arethresholds of different inputs are

different (type variations)different (type variations)

marginal input level may bemarginal input level may beinterpreted differentlyinterpreted differently


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D

CLK

X

Metastab.

Xdata

clkuin

uout

Combinational gates as well as theCombinational gates as well as the

inverters inside the FF map metastableinverters inside the FF map metastable

inputs to metastable outputsinputs to metastable outputs

Inverter-characteristics

A

Metastability PropagationMetastability Propagation

D

CLK


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Inconsistent PerceptionInconsistent Perception

D

CLK

D

CLK

X

0

1

Metastab.

The metastable state may be regarded asThe metastable state may be regarded as

1 by one FF and as 0 by another1 by one FF and as 0 by another

CMOS 3V

0.8V

2.0V

0.0V

0.4V

2.4V

3.3V

D

CLKX

threshold A

A

Btreshold B

A


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Why use the D-Flipflop?Why use the D-Flipflop?

Metastability is not restriced toMetastability is not restriced toD-FFs, it is encountered withD-FFs, it is encountered with

SR-latch, JK-Flipflop, Muller C-Gate,SR-latch, JK-Flipflop, Muller C-Gate,

basic issue:basic issue: Even with perfect input level runts mayEven with perfect input level runts may

emerge from looped-back outputs underemerge from looped-back outputs under

unfavorable timing conditionsunfavorable timing conditions Basically all biststableBasically all biststable

elements can becomeelements can become

metastablemetastable min min

max


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Metastability ProofsMetastability Proofs

Formal proofs exist thatFormal proofs exist that no upper bound on the duration ofno upper bound on the duration of

metastable state can be givenmetastable state can be given

metastability can in principle not bemetastability can in principle not be

avoided (Buridans Principle)avoided (Buridans Principle)

Fundamental issueFundamental issue Mapping from a continuous space to aMapping from a continuous space to a

discrete space involves a decision thatdiscrete space involves a decision thatmay take unbounded time (namely inmay take unbounded time (namely in

borderline cases)borderline cases)

RuntsRunts create such borderline casescreate such borderline cases


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Mitigating MetastabilityMitigating Metastability

Metastability cannot be eliminatedMetastability cannot be eliminated in practice systems still work becausein practice systems still work because

metastability is very improbablemetastability is very improbable

it can be madeit can be mademore or lessmore or less

probable byprobable by

design techniquesdesign techniques


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=

c

res

clkdat

tfTf

MTBU

exp1

0

Quantifying the Risk of MSQuantifying the Risk of MS

UpsetUpset metastable output is captured bymetastable output is captured by

subsequent FF aftersubsequent FF after ttrr

Mean Time Between Upset (MTBU)Mean Time Between Upset (MTBU) expected value (statistics!) for intervalexpected value (statistics!) for interval

between two subsequent upsetsbetween two subsequent upsets


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Resolution TimeResolution Time

clk

asyn

syn

tclk2outtcomb tSUtres

SUcombclkresttTt =

D

CLK

D

CLK

asyn

clk

syncomb.logic

normal operation:

tclk2out < tr

upset:

tclk2out > tr


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ParametersParameters

Resolution timeResolution time ttresres interval available for output to settle afterinterval available for output to settle after

active clock edgeactive clock edge

Flip-Flop parametersFlip-Flop parameters cc,,TT00 experimentally determinedexperimentally determined

time constanttime constant cc dep. on transit frequ.dep. on transit frequ.

TT00 from effective width of decision windowfrom effective width of decision window

Clock period of FFClock period of FF TTclkclk = 1/= 1/ffclkclk

Average rate of changeAverage rate of change ffdatdat

average data rate at FF data inputaverage data rate at FF data input


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Simple Metastability ModelSimple Metastability Model

model bistablemodel bistable

element byelement by

inverter pairinverter pair

useuse linear modellinear modelfor inverter,for inverter,

around midpoint ofaround midpoint of

transfer functiontransfer function

(balance point)(balance point)

consider homo-consider homo-genuous case, i.e.genuous case, i.e.

closed loopclosed loopuin

uoutInverter-characteristics

uout = -A*uin

u1 u2


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Introducing DynamicsIntroducing Dynamics

1st order1st order

approximation ofapproximation of

dynamic behavior:dynamic behavior:

RC elementRC element

assume symmetryassume symmetry

(same A, RC for(same A, RC for

both inverters) forboth inverters) for

simplicitysimplicity

assume symmetricassume symmetricsupplysupply (+VCC/-VCC)(+VCC/-VCC)

against GNDagainst GND

-A

-A

RC =

RC =u1 u2


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Differential EquationsDifferential Equations

Basics:Basics:

forward path:forward path:

backward path:backward path:

Laplace:Laplace:

time-domain solution:time-domain solution:

RR iRu = dtduCiCC =

dt

duCRuAu 212 =

dtduCRuAu 121 =

0)()(

usUs

dt

tduL =

( )

0

2212 uUsUAU =

( )0

1121 uUsUAU =

+++

= tAuutAuutu

1exp

2

1exp

2)(

0

1

0

2

0

1

0

22


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The SolutionThe Solution

uu2200-u-u

1100 difference of initial voltages difference of initial voltages

(charges on Cs); zero at balance point(charges on Cs); zero at balance point RC constant,RC constant, bandwidth = 1/RCbandwidth = 1/RC

A inverter gain at balance pointA inverter gain at balance point

A/A/

gain bandwidth product of inverter gain bandwidth product of inverterstarting from the initial difference ustarting from the initial difference u

22risesrises

exponentially with timeexponentially with time towards thetowards the

positive or negative supply voltagepositive or negative supply voltage

tAuutu

1exp2

)(01

02

2


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Plot of uPlot of u22 over Timeover Time

-500

-250

0

250

500

0 1 2 3

-25

-20

-15

-10

-5

0

5

10

15

20

25

For a givenFor a given ttwe can project forbidden input range backwe can project forbidden input range back

to a forbidden range of the initial voltage differenceto a forbidden range of the initial voltage difference


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Forbidden Initial RangeForbidden Initial Range

tAuutu

1exp2

)(01

02

2

uu00

= resborderoutrborder tAUtu

1exp)( ,,0

The forbidden output voltage range relates to aThe forbidden output voltage range relates to a

forbidden range of initial difference voltage (i.e. justforbidden range of initial difference voltage (i.e. just

after sampling). This range becomes exponentiallyafter sampling). This range becomes exponentially

smaller forsmaller for high resolution timehigh resolution time ttresres andand high gain-high gain-

bandwidth productbandwidth product AA// ..


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Aperture WindowAperture Window TTAWAW

How long does it take for the inputHow long does it take for the inputvoltage difference to cross thevoltage difference to cross the

forbidden range?forbidden range?

Depends on feedback voltage slopeDepends on feedback voltage slope

(and probably on input voltage!)(and probably on input voltage!)

+u0, border

u0, borderT

AW

udiff (t), slope S

S

uT borderAW ,0

2

=


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CalibratingCalibrating TTAWAW

TTAWAW depends ondepends on uu0,0,borderborder,,which in turn depends onwhich in turn depends on tt

resres

for immediate use of the output:for immediate use of the output:

thusthus

== resborderborder

AW tA

S

U

S

uT

1exp

22 ,0,0

0

,02)0( W

border

resAW T

S

UtT ===

= resWAW t

ATT

1exp0

technologyparameter


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Hitting the ApertureHitting the Aperture

with exponentially distributed inter-arrivalwith exponentially distributed inter-arrivaltime of input events (ratetime of input events (rate

datdat) and) and

sampling with periodsampling with period TTclkclk

(i.e. window(i.e. window TTAWAW

isis

repeated) the upset rate can be calculatedrepeated) the upset rate can be calculated

asas

Hence the MTBU becomesHence the MTBU becomes

clk

AWdatupset

T

T=

AW

clk

datupset T

TMTBU ==

11


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Putting it all togetherPutting it all together

AW

clk

datupset T

TMTBU ==

11

= resWAW t

ATT

1exp0

= resWclk

dat

tATTMTBU

1exp1

0

T0

1/


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The widely used equationThe widely used equation

=

c

r

clkdat

tTff

MTBU

exp1

0

rate (!) ofinput events

sampling frequency

technologyparameters

expected timebetween upsets(statistical!)

availableresolution time


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Provoking MetastabilityProvoking Metastability

asynchronous inputsasynchronous inputs multiple clock domainsmultiple clock domains

clock divider (uncontrolled delay)clock divider (uncontrolled delay)

low timing marginslow timing margins

slow technology (gain/BW prod)slow technology (gain/BW prod)

supply drop (excessive delay)supply drop (excessive delay) heatingheating


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Determination ofDetermination ofTT00,, CC

experimental:experimental:

varyvary ttresres

observe MTBUobserve MTBU log graphlog graph

=> straight=> straight

slope ->slope -> CC

offset ->offset -> TT00

typical valuestypical values

T0

C

1

tr-tCO (ns)

fdat

= 1MHz

fclk = 10MHz


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Claim: Metastability is a non-issueClaim: Metastability is a non-issuein modern technologiesin modern technologies

log MTBU[s]

tres

6

12

5

1996(XC4005)

2002(XC2VP4)

BUT: clock rates haveincreased by a factor of16 during that period

and timing marginshave shrunk in thesame way!

Metastability TrendsMetastability Trends


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Mitigating MetastabilityMitigating Metastability

avoid/minimize non synchronous IFsavoid/minimize non synchronous IFs leave sufficient timing marginsleave sufficient timing margins

use fast technology (gain/BW prod)use fast technology (gain/BW prod)

ensure proper operating conditionsensure proper operating conditions(stable power supply, cooling,)(stable power supply, cooling,)

basic principle of synchronizers:basic principle of synchronizers:

trade performance for increasedtrade performance for increased

timing margins (ttiming margins (tresres))


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SynchronizerSynchronizer

Example: Cascade ofExample: Cascade ofnn Input-FFsInput-FFs

D

CLK

asyn

clk

syn

D

CLK

MTBU calculation: same equation as before,MTBU calculation: same equation as before,but now individual resolution times sum up:but now individual resolution times sum up:

= iresres tt ,


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MTBF of n-Stage Synchr.MTBF of n-Stage Synchr.

Recall the projection of allowed output range to anRecall the projection of allowed output range to aninput range considering the exponen-tial increaseinput range considering the exponen-tial increase

during the resolution time:during the resolution time:

uu00for FFfor FF

kkis provided by the output of a precedingis provided by the output of a preceding

stage FFstage FFk-1k-1

=> we make the same projection again:=> we make the same projection again:

=

c

resoutres

tUtu

exp)(0

1

,

1

,01,1,0

expexp

exp)(

=

=

kc

res

kc

reskout

kc

reskkresk

ttU

tutu


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Assumptions made so farAssumptions made so far

linear inverter slopelinear inverter slope (1st order model)(1st order model) load independent gainload independent gain

dominating RC const.dominating RC const. (1st order model)(1st order model)

full symmetryfull symmetry (RCs, inverter properties,(RCs, inverter properties,rising/falling slopes,)rising/falling slopes,)

decreasing exp term neglecteddecreasing exp term neglected

homogenuous casehomogenuous case (MUX switching and(MUX switching and

input signal shape neglected)input signal shape neglected)

equally distributed voltage levelsequally distributed voltage levels

exponentially distributed input eventsexponentially distributed input events


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A More general MS ModelA More general MS Model

ideal amplifier

gain -A

pure delay

delay

slope limiter

time constantRC slope S

GBWP = A/RC determines dynamics(decay of metastable state)

oscillation for > RC/A

creeping otherwise

13716_2 metastability

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