14 cascading counters: build a 6-bit counter by cascading two 3...
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![Page 1: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/1.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 7 / 8C Copyright 2006 Gandhi Puvvada
14 Cascading Counters: Build a 6-bit counter by cascading two 3-bit counters
Try completing this alternative design and also criticize the same.
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
EN_CLK
![Page 2: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/2.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 7 / 8C Copyright 2006 Gandhi Puvvada
14 Cascading Counters: Build a 6-bit counter by cascading two 3-bit counters
Try completing this alternative design and also criticize the same.
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
EN_CLK
![Page 3: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/3.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 7 / 8C Copyright 2006 Gandhi Puvvada
14 Cascading Counters: Build a 6-bit counter by cascading two 3-bit counters
Try completing this alternative design and also criticize the same.
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
EN_CLK
![Page 4: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/4.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 7 / 8C Copyright 2006 Gandhi Puvvada
14 Cascading Counters: Build a 6-bit counter by cascading two 3-bit counters
Try completing this alternative design and also criticize the same.
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
EN_CLK
![Page 5: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/5.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 7 / 8C Copyright 2006 Gandhi Puvvada
14 Cascading Counters: Build a 6-bit counter by cascading two 3-bit counters
Try completing this alternative design and also criticize the same.
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
EN
CLK
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
Least SignificantRegister
Q3
Q4
Q5
D Q
D Q
Q3*
Q4*
Q5*
EN_CLK
![Page 6: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/6.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 8 / 8C Copyright 2006 Gandhi Puvvada
15 Fix Mr. Bruin, I mean, Mr. Bruin’s design of a stop watch. This stop watch goes from 0:00 to 1:59 (1 Min. 59 Sec.) and rolls back to 0:00. It has a CLEAR and START/STOP controls.
16 Timing analysis of a counter
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQS0
QS1
QS2
D Q
D Q
QS0*
QS1*
QS2*
CLK
D QQS3* QS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
START/STOP
Least Significant
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQTS0
QTS1
QTS2
D Q
D Q
QTS0*
QTS1*
QTS2*
CLK
D QQTS3* QTS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
Least Significant
CLEAR
CLEAR
D QCLKCLK
QM
![Page 7: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/7.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 8 / 8C Copyright 2006 Gandhi Puvvada
15 Fix Mr. Bruin, I mean, Mr. Bruin’s design of a stop watch. This stop watch goes from 0:00 to 1:59 (1 Min. 59 Sec.) and rolls back to 0:00. It has a CLEAR and START/STOP controls.
16 Timing analysis of a counter
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQS0
QS1
QS2
D Q
D Q
QS0*
QS1*
QS2*
CLK
D QQS3* QS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
START/STOP
Least Significant
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQTS0
QTS1
QTS2
D Q
D Q
QTS0*
QTS1*
QTS2*
CLK
D QQTS3* QTS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
Least Significant
CLEAR
CLEAR
D QCLKCLK
QM
![Page 8: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/8.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 8 / 8C Copyright 2006 Gandhi Puvvada
15 Fix Mr. Bruin, I mean, Mr. Bruin’s design of a stop watch. This stop watch goes from 0:00 to 1:59 (1 Min. 59 Sec.) and rolls back to 0:00. It has a CLEAR and START/STOP controls.
16 Timing analysis of a counter
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQS0
QS1
QS2
D Q
D Q
QS0*
QS1*
QS2*
CLK
D QQS3* QS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
START/STOP
Least Significant
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQTS0
QTS1
QTS2
D Q
D Q
QTS0*
QTS1*
QTS2*
CLK
D QQTS3* QTS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
Least Significant
CLEAR
CLEAR
D QCLKCLK
QM
![Page 9: 14 Cascading Counters: Build a 6-bit counter by cascading two 3 …ee-classes.usc.edu/ee457/ee457_lab_manual_Fl2010/ee457... · 2011. 4. 16. · B1 B2 S0 S1 S2 Adder 0 0 1 Most Significant](https://reader036.vdocument.in/reader036/viewer/2022071513/6134b6b2dfd10f4dd73be81b/html5/thumbnails/9.jpg)
EE201L_ClassNotes_Ch10_Counters_transparencies.fm
4/24/06 EE201L Class Notes - Chapter #10 Counters Page 8 / 8C Copyright 2006 Gandhi Puvvada
15 Fix Mr. Bruin, I mean, Mr. Bruin’s design of a stop watch. This stop watch goes from 0:00 to 1:59 (1 Min. 59 Sec.) and rolls back to 0:00. It has a CLEAR and START/STOP controls.
16 Timing analysis of a counter
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQS0
QS1
QS2
D Q
D Q
QS0*
QS1*
QS2*
CLK
D QQS3* QS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
START/STOP
Least Significant
D Q
A0A1A2
B0B1B2 S0
S1S2
Adder
001
Most Significant
RegisterQTS0
QTS1
QTS2
D Q
D Q
QTS0*
QTS1*
QTS2*
CLK
D QQTS3* QTS3
B3
A3
S3
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
000
Y3
I130
I03
0
I00I01I02
I10I11I12
Y0Y1Y2
S
Mux
Y3
I13
I03
EN CLR
Least Significant
CLEAR
CLEAR
D QCLKCLK
QM