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CSE 141 Discussion

Final Review

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Branch Prediction

What is the accuracy of always taken and

always-not-taken predictors for this

sequence? Always taken: 3/5 = 60%

Always not taken: 2/5 = 40%

Branch Pattern: T, T, T, NT, NT

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Branch Prediction

What is the accuracy of the two-bit predictor

for the first four branches in the pattern,

assuming the predictor starts off at stronglynot taken?

Outcomes: T, T, T, NT

Predictor Values at prediction time: 00, 01, 10, 11 Accuracy: 25%


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Branch Prediction

What is the accuracy of the two-bit predictor

if this pattern is repeated forever?

Values at 1stPass: 00, 01, 10, 11, 10 (20%)

Values at 2ndPass: 01, 10, 11, 11, 10 (40%)

Values at nth Pass: 01, 10, 11, 11, 10 (40%)

Accuracy: 40%


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Branch Prediction

Design a predictor that would achieve a perfect

accuracy if the pattern was repeated forever.

Requires a working knowledge of the branch Create an N-bit Shift Register

Every time the register is accessed, it shifts one bit to the

right

Initialize the target branch pattern into the register

What are the problems of doing something like this?


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Direct Mapped Caching

What does the cache look like if you have a

direct-mapped cache with 2-word blocks and

8 blocks? Show Hit/Miss rates as well. Need a couple tables

Show a table that shows the index calculation and

whether it hits or misses the cache Show a table of the cache to show what is in the

cache at that moment.

Memory Access Pattern: 1, 134, 212, 1, 135, 213, 162, 161, 2, 44, 41, 221

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Tag Index Offset H/M

0000 000 1 M


Index Tag

000 0000

001

010

011

100

101

110

111

First address to go into cache

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0000 000 1 M

1000 011 0 M

1101 010 0 M


Index Tag

000 0000

001

010 1101

011 1000

100

101

110

111

Nothing interesting to see here

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0000 000 1 M

1000 011 0 M

1101 010 0 M

0000 000 0 H


Index Tag

000 0000

001

010 1101

011 1000

100

101

110

111

First cache hit for Mem Address = 1!

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0000 000 1 M

1000 011 0 M

1101 010 0 M

0000 000 0 H

1000 011 1 H

1101 010 1 H

1010 001 0 M

1010 000 1 M


Index Tag

000 0000 1010

001 1010

010 1101

011 1000

100

101

110

111

First Conflict and Replacement

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0000 000 1 M

1000 011 0 M

1101 010 0 M

0000 000 0 H

1000 011 1 H

1101 010 1 H

1010 001 0 M

1010 000 1 M

0000 001 0 M


Index Tag

000 1010

001 1010 0000

010 1101

011 1000

100

101

110

111

More Conflicts

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0000 000 1 M

1000 011 0 M

1101 010 0 M

0000 000 0 H

1000 011 1 H

1101 010 1 H

1010 001 0 M

1010 000 1 M

0000 001 0 M

0010 110 0 M

0010 100 1 M

1101 110 1 M


Index Tag

000 1010

001 0000

010 1101

011 1000

100 0010

101

110 0010 1101

111

Filling up the rest of cache

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What about associative caches?

Lets use the same instruction stream, but

have a 3-way set associative cache with two-

word blocks and a total size of 24 words.

Waithow many possible indices will we have

then?

We will use LRU replacement to evict old data

from the cache.

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Set-Associative Caching


00000 00 1 M

10000 11 0 M

11010 10 0 M


Index Tag[0] Tag[1] Tag[2]

00 00000

01

10 11010

11 10000

Filling up Cache

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00000 00 1 M

10000 11 0 M

11010 10 0 M

00000 00 0 H

10000 11 1 H

11010 10 1 H



00 00000

01

10 11010

11 10000

Bunch of hits!

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00000 00 1 M

10000 11 0 M

11010 10 0 M

00000 00 0 H

10000 11 1 H

11010 10 1 H

10100 01 0 M

10100 00 1 M

00000 01 0 M

00101 10 0 M

00101 00 1 M

11011 10 1 M



00 00000 10100 00101

01 10100 00000

10 11010 00101 11011

11 10000

Filling up more Cache

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00000 00 1 M

10000 11 0 M

11010 10 0 M

00000 00 0 H

10000 11 1 H

11010 10 1 H

10100 01 0 M

10100 00 1 M

00000 01 0 M

00101 10 0 M

00101 00 1 M

11011 10 1 M



00 00001 10100 00101

00000

01 10100 00000

10 11010 00101 11011

11 10000

Example of LRU Step 2

NEW STREAM ADDRESSES: 8, 161, 1


00001 00 0 M

10100 00 1 H

00000 00 0 M

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TLB

Think of it as a cache for virtual memory

Operates in pretty much the same way as a

cache does

They tend to be fully associative

Will have some form of LRU (since true LRU is

difficult to implement in hardware)

Question: Show the TLB after a set of memory

addresses go through it.

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TLB

Valid Phys Page or Disk

1 5

0 Disk

0 Disk

1 6

1 9

1 11

0 Disk

1 4

0 Disk

0 Disk

1 3

1 12

Memory Access Pattern: 9452, 30964, 19136, 46502, 38110, 16653, 48480

Valid Tag Page Num

1 11 12

1 7 4

1 3 6

0 4 9

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TLB


1 5

0 Disk

1 13

1 6

1 9

1 11

0 Disk

1 4

0 Disk

0 Disk

1 3

1 12


Valid Tag Page Num

1 11 12

1 7 4

1 3 6

1 2 13

Address: 9452, TLB Miss AND Page Fault!

(Tag is 2)

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TLB


1 5

0 Disk

1 13

1 6

1 9

1 11

0 Disk

1 4

0 Disk

0 Disk

1 3

1 12


Valid Tag Page Num

1 11 12

1 7 4

1 3 6

1 2 13

Address: 30964, TLB Hit (Tag is 7)

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TLB


1 5

0 Disk

1 13

1 6

1 9

1 11

0 Disk

1 4

0 Disk

0 Disk

1 3

1 12


Valid Tag Page Num

1 4 9

1 7 4

1 3 6

1 2 13

Address: 19136, TLB Miss (Tag is 4Replace 11)

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TLB


1 5

0 Disk

1 13

1 6

1 9

1 11

0 Disk

1 4

0 Disk

0 Disk

1 3

1 12


Valid Tag Page Num

1 4 9

1 7 4

1 11 12

1 2 13

Address: 46502, TLB Miss (Tag is 11Replace 3)

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TLB


1 5

0 Disk

1 13

1 6

1 9

1 11

0 Disk

1 4

0 Disk

1 14

1 3

1 12


Valid Tag Page Num

1 4 9

1 7 4

1 11 12

1 9 14

Address: 38110, Page Fault! (Tag is 9Replace 2)

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TLB


1 5

0 Disk

1 13

1 6

1 9

1 11

0 Disk

1 40 Disk

1 14

1 3

1 12


Valid Tag Page Num

1 4 9

1 7 4

1 11 12

1 9 14

Address: 16553 (Tag = 4) Hit

Address: 48480 (Tag = 11) Hit

What do we replace next?

141 review

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