15-447 computer architecturefall 2007 © november 21, 2007 karem a. sakallah lecture 23 virtual...
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15-447 Computer Architecture Fall 2007 ©
November 21, 2007
Karem A. Sakallah
Lecture 23Virtual Memory (2)
CS 15-447: Computer Architecture
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15-447 Computer Architecture Fall 2007 ©
Last Lecture
• Virtual memory lets the programmer “see” a memory array larger than the DRAM available on a particular computer system.
• Virtual memory enables multiple programs to share the physical memory without:– Knowing other programs exist (transparency).– Worrying about one program modifying the data
contents of another (protection).
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15-447 Computer Architecture Fall 2007 ©
Other VM Functions
• Page data location – Physical memory, disk, uninitialized data
• Access permissions– Read only pages for instructions
• Gathering access information– Identifying dirty pages by tracking stores– Identifying accesses to help determine LRU
candidate
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15-447 Computer Architecture Fall 2007 ©
Page Replacement Strategies
• Page table indirection enables a fully associative mapping between virtual and physical pages.
• How do we implement LRU?– True LRU is expensive, but LRU is a heuristic
anyway, so approximating LRU is fine– Reference bit on page, cleared occasionally by
operating system. Then pick any “unreferenced” page to evict.
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15-447 Computer Architecture Fall 2007 ©
Performance of Virtual Memory
• We must access physical memory to access the page table to make the translation from a virtual address to a physical one
• Then we access physical memory again to get (or store) the data• A load instruction performs at least 2 memory
reads• A store instruction performs at least 1 read and
then a write.
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15-447 Computer Architecture Fall 2007 ©
Translation Lookaside Buffer
• We fix this performance problem by avoiding memory in the translation from virtual to physical pages.
• We buffer the common translations in a translation lookaside buffer (TLB)
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15-447 Computer Architecture Fall 2007 ©
Where is the TLB Lookup?
• We put the TLB lookup in the pipeline after the virtual address is calculated and before the memory reference is performed.– This may be before or during the data cache
access.– Without a TLB we need to perform the
translation during the memory stage of the pipeline.
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15-447 Computer Architecture Fall 2007 ©
Placing Caches in a VM System
• VM systems give us two different addresses: virtual and physical
• Which address should we use to access the data cache?– Virtual address (before VM translation)
• Faster access? More complex?
– Physical address (after VM translations)• Delayed access?
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15-447 Computer Architecture Fall 2007 ©
Physically-Addressed Caches
• Perform TLB lookup before cache tag comparison.– Use bits from physical address to index set
– Use bits from physical address to compare tag
• Slower access? – Tag lookup takes place after the TLB lookup.
• Simplifies some VM management– When switching processes, TLB must be invalidated,
but cache OK to stay as is.
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15-447 Computer Architecture Fall 2007 ©
Page offsetVirtual page
Picture of Physical Caches
Virtual address
Set1 tagSet1 tag
Set0 tagSet0 tag
Set2 tagSet2 tag
Tagcmp
Tagcmp
Cache
tag PPNtag PPNtag PPNtag PPN
Page offsetPPN
tag index Blockoffset
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15-447 Computer Architecture Fall 2007 ©
Virtually-Addressed Caches
• Perform the TLB lookup at the same time as the cache tag compare.– Uses bits from the virtual address to index the cache
set– Uses bits from the virtual address for tag match.
• Problems:– Aliasing: Two processes may refer to the same
physical location with different virtual addresses.– When switching processes, TLB must be invalidated,
and dirty cache blocks must be written back to memory.
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15-447 Computer Architecture Fall 2007 ©
Picture of Virtual Caches
tag index Block offset
Virtual address
Set1 tagSet1 tag
Set0 tagSet0 tag
Set2 tagSet2 tag
Tagcmp
Tagcmp
• TLB is accessed in parallel with cache lookup• Physical address is used to access main memory in case of a cache miss.
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15-447 Computer Architecture Fall 2007 ©
OS Support for Virtual Memory
• It must be able to modify the page table register, update page table values, etc.– To enable the OS to do this, AND not the user
program, we have different execution modes for a process – one which has executive (or supervisor or kernel level) permissions and one that has user level permissions.
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15-447 Computer Architecture Fall 2007 ©
Extended Example: Loading a Program into Memory
text2Istatic
text1
Disk Pages 2 entry TLBMemory
Page Table
0123
1000100110021003
01234567
References000000047FFC00082134
Physical Refs
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15-447 Computer Architecture Fall 2007 ©
Additional Information
• Page size = 4KB
• Page table entry size = 4B
• Page table register points to physical address 0000
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15-447 Computer Architecture Fall 2007 ©
Step 1: Read Executable Headerand Initialize Page Table
text2Istatic
text1
Disk Pages 2 entry TLB
reserved
Memory
Page TableD1000D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
01234567
References000000047FFC00082134
Physical Refsroro
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15-447 Computer Architecture Fall 2007 ©
Step 2: Load PC from Headerand Start Execution
text2Istatic
text1
Disk Pages 2 entry TLB
reserved
Memory
Page TableD1000D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
01234567
References000000047FFC00082134
Physical Refsroro
MISS!
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15-447 Computer Architecture Fall 2007 ©
Fetching instr 0000
text2Istatic
text1
Disk Pages 2 entry TLB
reserved
Memory
Page TableD1000D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
01234567
References000000047FFC00082134
Physical Refs0000
Page fault
roro
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15-447 Computer Architecture Fall 2007 ©
Fetching instr 0000
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Memory
Page TableM1
D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
ro
01234567
References000000047FFC00082134
Physical Refs0000
Page fault
roro
21
15-447 Computer Architecture Fall 2007 ©
Fetching instr 0000
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Memory
Page TableM1
D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
ro
01234567
References000000047FFC00082134
Physical Refs0000
Page fault1000
roro
22
15-447 Computer Architecture Fall 2007 ©
Fetching instr 0004
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Memory
Page TableM1
D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
ro
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
roro
HIT!
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15-447 Computer Architecture Fall 2007 ©
Reference 7FFC
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Memory
Page TableM1
D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
ro
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
roro
MISS!
24
15-447 Computer Architecture Fall 2007 ©
Reference 7FFC
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Memory
Page TableM1
D1001D1002no mapno mapno mapno mapno map
0123
1000100110021003
ro
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
No map page fault
roro
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15-447 Computer Architecture Fall 2007 ©
Reference 7FFC
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Set to 0s
Memory
M27000
Page TableM1
D1001D1002no mapno mapno mapno map
M2
0123
1000100110021003
rorw
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
No map page fault2FFC
roro
26
15-447 Computer Architecture Fall 2007 ©
Fetching instr 0008
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Set to 0s
Memory
M27000
Page TableM1
D1001D1002no mapno mapno mapno map
M2
0123
1000100110021003
rorw
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
No map page fault2FFC1008
roro
HIT!
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15-447 Computer Architecture Fall 2007 ©
Reference 2134
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Set to 0s
Memory
M27000
Page TableM1
D1001D1002no mapno mapno mapno map
M2
0123
1000100110021003
rorw
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
No map page fault2FFC1008
roro
MISS!
28
15-447 Computer Architecture Fall 2007 ©
Reference 2134
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Set to 0s
Memory
M27000
Page TableM1
D1001D1002no mapno mapno mapno map
M2
0123
1000100110021003
rorw
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
No map page fault2FFC1008
Page fault
roro
29
15-447 Computer Architecture Fall 2007 ©
Reference 2134
text2Istatic
text1
Disk Pages
M10000
2 entry TLB
reservedtext1
Set to 0sIstatic
Memory
M32000
Page TableM1
D1001M3
no mapno mapno mapno map
M2
0123
1000100110021003
rorw
01234567
References000000047FFC00082134
Physical Refs0000
Page fault10001004
No map page fault2FFC1008
Page fault3134
roro
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15-447 Computer Architecture Fall 2007 ©
Multiple Processes
• Virtual cache support for multiple processes:– Flush the cache between each context switch.– Use processID (a unique number for each
processes given by the operating system) as part of the tag
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15-447 Computer Architecture Fall 2007 ©
Multiple Processors
• Can run two programs at the same time– Each processor has its own cache. Why?
• May or may not share data– Sharing code is not a problem (read only)
• Example: shared libraries, DDLs
– Sharing data (read/write) is a problem• What if it is in one processors cache?
– Solution: Snoopy caches