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Lecture 15:Lecture 15:Register Transfer LanguageRegister Transfer Language

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RTL (Register Transfer Language)RTL (Register Transfer Language)

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RTL ToolsRTL Tools

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VerilogVerilog

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Modified ExampleModified Example

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WiresWires

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module example(b, c, d);input [3:0]b, [3:0]c;output d;wire [3:0]a; // necessary

a = b & c;

d = a[2] | a[1] | a[0];endmodule

Register Transfer Language?Register Transfer Language?

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Module D_FlipFLop(Q, D, CLK);output Q;reg Q;input D, CLK;always @(negedge CLK) // Sensitivity List

begin // Not needed for 1 statement

Q

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Misc.Misc.

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reg [31:0] register_file[0:31];

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