1581110060 k. v. suresh kumar(phase2-review2)3
TRANSCRIPT
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Implementation of High-
Performance 32-bitHigh-Valency Ling Adder
Under the guidance of Mrs. E. Chitra , Asst. Prof. (Sr.G)
By
K. V. Suresh Kumar M.Tech VLSI Design
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Outline Previous Work
Kogge stone Adder
Ladner fischer Adder
Ling adder with valency
Simulation Results
References11-06-2013
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Previous Work
A 32-bit Ling Adder is implemented by replacing H.Ling proposed equations in CLA as follows.
p i = a i b i ti = a i + b i
g i = a i . b i where t i = p i + g i s i = p i c i-1 c i = g i + t i . c i -1
c i = g i + p i . c i-1 = t i . h i
s i = p i c i -1
= p i (t i -1 . h i -1) 11-06-2013
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The delay is compared with Carry Look AheadAdder and Ripple Carry Adder.
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Adder(32-bit) Delay(ns) Power(W)
Ripple carry Adder 44.27 ns 0.168
Carry Look Ahead Adder 42.42 ns 0.215
Ling Adder(with H.Ling
Equations)
6.096 ns 0.130
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4-bit Kogge Stone AdderA0=1 B0=0A1=1 B1=0A2=0 B2=1A3=1 B3=1
Cin=0
g0=0 p 0=1
G0=C0=0
g1=0 p 1=1
G1:0 =0P1:0 =1
G1=C1=0
g2=0 p 2=1
G2:1 =0P2:1 =1
G2=C2=0
g3=1 p 3=0
G3:2 =1P3:2 =0
G3=C3=1
G3:0 =1P3:0 =0
S0=1S1=1S2=1S3=0Cout =1
A=1011B=1100S=0111
Cout =1
g = a i and b ip = a i xor b i
Black CellG i= G i+P i.G i-1 P i=P i . P i-1
Carryci= g i
Sum
S i= p i xor ci-1
p0p1p 2p3
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11-06-2013
gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0
a(0)b(0)
a(1)b(1)
a(2)b(2)
a(3)b(3)
a(4)b(4)
a(5)b(5)
a(6)b(6)
a(7)b(7)
Cin
gc0 bc0 bc1 bc2 bc4 bc8 bc6 bc10
gc1 gc2 bc3
gc3 gc4 gc5 gc6
bc5 bc9 bc7 bc11
gc7
S0 S1 S2 S3 S4 S5
P0(0)P0(1)P0(2)
S6 S7
P0(3)P0(4)P0(5)P0(6)P0(7)
Cout
g3(1)g3(2)g3(3)g3(4)g3(5)g3(6)g3(7)
g2(7)
p 2(7)
g2(6)
p 2(6)
g2(5)
p 2(5)
g2(4)
p 2(4)
g2(3)
p 2(3)
g2(2) g 2(1) g 2(0)
g1(0)g1(1)p 1(1)
g1(2)p 1(2)
g1(3)p 1(3)
g1(4)p 1(4)
g1(5)p 1(5)
g1(6)p 1(6)
g1(7)p 1(7)
g0(7)
p 0(7)
g0(6)
p 0(6)
g0(5)
p 0(5)
g0(4)
p 0(4)
g0(3)
p 0(3)
g0(2)
p 0(2)
g0(1)
p0(1)
g0(0)
p 0(0)
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gp15 gp14 gp13 gp12 gp11 gp10 gp9 gp8 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0
a(0)b(0)
a(1)b(1)
a(2)b(2)
a(3)b(3)
a(4)b(4)
a(5)b(5)
a(6)b(6)
a(7)b(7)
a(8)b(8)
a(9)b(9)
a(10)b(10)
a(11)b(11)
a(12)b(12)
a(13)b(13)
a(14)b(14)
a(15)b(15)
Cin
gc0 bc0 bc1 bc2 bc4 bc8 bc6 bc10 bc13 bc16 bc19 bc22 bc25 bc28 bc31 bc34
gc1 gc2 bc3
gc3 gc4 gc5 gc6
bc5 bc9 bc7 bc11 bc14 bc17 bc20 bc23 bc26 bc29 bc32 bc35
bc12 bc15 bc18 bc21 bc24 bc27 bc30 bc33 bc36
gc7 gc8 gc9 gc10 gc11 gc12 gc13 gc14 gc15
S0 S1 S2 S3 S4 S5
P0(0)P0(1)P0(2)
S6 S7 S8 S9 S10
P0(3)P0(4)P0(5)P0(6)P0(7)P0(8)P0(9)P0(10)
S11 S12 S13 S14 S15
Cout
P0(11)P0(12)P0(13)P0(14)P0(15)
g4(3)g4(4)g4(5)g4(6)g4(7)g4(8)g4(9)g4(10)g4(11)g4(12)g4(13)g4(14)g4(15)
g3(1)g3(2)g3(3)g3(4)g3(5)g3(6)g3(7)p 3(7)
g3(8)p 3(8)
g3(9)p3(9)
g3(10)p 3(10)
g3(11)p 3(11)
g3(12)p 3(12)
g3(13)p 3(13)
g3(14)p3(14)
g3(15)p 3(15)
g2(10)
p 2(10)
g2(11)
p 2(11)
g2(12)
p 2(12)g2(13)p 2(13)
g2(14)p 2(14)
g2(15)p 2(15)
g2(9)
p 2(9)
g2(8)
p 2(8)
g2(7)
p2(7)
g2(6)
p 2(6)
g2(5)
p 2(5)
g2(4)
p2(4)
g2(3)
p 2(3)
g2(2) g 2(1) g 2(0)
g1(0)g1(1)p 1(1)
g1(2)p 1(2)
g1(3)p1(3)
g1(4)p1(4)
g1(5)p 1(5)
g1(6)p 1(6)
g1(7)p 1(7)
g1(8)p 1(8)
g1(9)p 1(9)
g1(10)p 1(10)
g1(11)p 1(11)
g1(12)p 1(12)
g1(13)p 1(13)
g1(14)p1(14)
g1(15)p 1(15)
g0(10)
p 0(10)
g0(11)
p0(11)
g0(12)
p 0(12)
g0(13)
p 0(13)
g0(14)
p0(14)
g0(15)
p 0(15)
g0(9)
p 0(9)
g0(8)
p 0(8)
g0(7)
p0(7)
g0(6)
p 0(6)
g0(5)
p 0(5)
g0(4)
p0(4)
g0(3)
p0(3)
g0(2)
p 0(2)
g0(1)
p 0(1)
g0(0)
p 0(0)
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32 bit Kogge Stone Adder
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Ling Adder with valency
11-06-2013 32-bit Adder carry tree with valency 2x3x2(12 bit) and 2x5x2(20 bit)
012345678910111213141516171819202122232425262728293031
R(2)31:30
R(5)31:22 R(5)21:12 R(3)11:6 R(3)5:0
R(2)31:12 R(2)11:0
R(2)31:0
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Ling Adder with Valency 2x3x2 and 2x5x2
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Steps to reduce delay If the load of any gate is larger than required the reduction in load is obtained
either by reducing the wire load or by fan-out load. Wire load reduction is possible by placing the driving gate and driven gates
close to each other.
Fan-out reduction can be obtained by inserting the inverter after that gate and
driving the gates on non-critical path through that inverter and gate on critical path directly.
Techniques like shielding reduce the wire capacitance of long wires by placingthe power and ground rails parallel to that wire.
By connecting input which is available late to the faster input of the gate canalso reduce the total delay.
Some of the gates have very high input capacitance so the delay through thatgate is longer compared to others, avoiding such gates and reformulation of equations to use better gates reduces the overall delay.
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Delay comparison
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Adder(32-bit) Delay(ns) Power(W)
Ripple carry Adder 44.27 ns 0.168
Carry Look Ahead
Adder
42.42 ns 0.215
Kogge stone Adder 13.897 ns 0.167
Ling Adder(with H.Ling
Equations)
6.096 ns 0.130
Ling Adder with
Valency
6.026 ns 0.349
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Advantages
Compared with normal CLA adder:
c i = g i + c i -1 t i
= g i + g i -1 . t i + g i -2 . t i-1. t i + + t i . t i-1 . . t 0 . C -1
h i = g i + g i-1 + g i -2 . t i-1 + + t i-1 . t i-2 . . t 0 . h -1
Each product term in h i has one less AND gatecorrespondingly
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References[1] Taskin Kocak, Preeti Patil, Design and Implementation of High-Performance
High-Valency Ling Adders. 978-1-4673-1188-5/12/ 2012 IEEE
[2] Dayu Wang, Xiaoping Cui, Xiaojing Wang, Optimized design of Parallel Prefix LingAdder, International Conference on Electronics, Communications and Control(ICECC) 2011.
[3] Dimitrakopoulos. G, Nikolos. D, High -speed parallel-prefix VLSI Lingadders, IEEE Transactions on Computers , Feb. 2005.
[4] Matthew Keeter, David Money Harris, Andrew Macrae, Rebecca Glick, MadeleineOngand Justin Schauer, Implementation of 32-bit Ling and Jackson Adders, Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems andComputers (ASILOMAR), 2011
[5] Adder Designs , http://www.acsellab.com/Projects/fast_adder/adder_designs.htm
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http://www.computer.org/tc/http://www.acsellab.com/Projects/fast_adder/adder_designs.htmhttp://www.acsellab.com/Projects/fast_adder/adder_designs.htmhttp://www.acsellab.com/Projects/fast_adder/adder_designs.htmhttp://www.acsellab.com/Projects/fast_adder/adder_designs.htmhttp://www.computer.org/tc/http://www.computer.org/tc/http://www.computer.org/tc/http://www.computer.org/tc/http://www.computer.org/tc/http://www.computer.org/tc/http://www.computer.org/tc/ -
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Thank you
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