1

18-322 Lecture 19 CMOS Gates: Sizing and Delay

• Load Capacitance

• Fall and rise time analysis.

• Analytical models.

• Propagation delay analysis.

• Fall and rise time formulas

• Transistor sizing

• Multi-input gates

Text: Sections 3.3.3 and 4.2

2

CMOS Inverter’s

LoadVDD

GND

In

VDD

GND

OutC

AB B

A

B

A

C

C

VDD

GND

B

A

B

C

C

A

VDD

GND

A

B

C

B CA

VDD

GND

C

A

C

A

3

VDD

GND

In

VDD

GND

OutC

AB B

A

B

A

C

C

VDD

GND

B

A

B

C

C

A

VDD

GND

A

B

C

B CA

VDD

GND

C

A

C

A

CL VDD

GND

In

CL

4

CMOS Inverter - Switching

VDD

GND

VDD

GND

"1"

CL

VDD

GND

"0"

CL

5

Device equations (NMOS)

Non-Sat:

Saturation:

where

Ids βn Vgs Vtn–( )Vds12---Vds

2–=

Ids

βn

2----- Vgs Vtn–( )2

=

βn µ εtox------ W

L-----

n

=

6

Inverter Switching

Non-Sat Sat

Vds = Vgs - Vtn

OffOn

Vout

Ids

Vin

fall time rise time

Time

VOL

VOH

VDD

VinVout

CL

NMOS trajectory: Vout falling.

90%

10%

7

CMOS Inverter - Switching

DS

800

700

600

500

400

300

200

100

0

V = 5.0 VGS

V = 4.5 VGS

V = 4.0 VGS

V = 3.5 VGS

V = 3.0 VGS

V = 2.5 VGS

V = 2.0 VGSV = 1.5 VGS

V [V]

DSI [µA]

5.04.03.02.01.0

VDD

GND

"1"

CL

8

Output Fall Time Analysis

PMOS

NMOSCL

Vout(t)

Ic

Idsn

NMOS saturated: Vout ≥ VDD - Vtn

PMOS

NMOSCL

Vout(t)

Ic

NMOS non-saturated:0 < Vout ≤ VDD - Vtn

Rcn

tf kCL

βnVDD-----------------=

9

CMOS Inverter - Switching

800

700

600

500

400

300

200

100

0DS

GS

V [V]

DS- I [µA]

V = -5.0 V

-5.0-4.0-3.0-2.0-1.0

VDD

GND

"0"

CL

10

Output Rise Time Analysis

PMOS

NMOSCL

Vout(t)

Ic

Idsp

PMOS saturated: Vout ≤ |Vtp|

PMOS

NMOSCL

Vout(t)

Ic

PMOS non-saturated: |Vtp| < Vout < VDD

Rcp

tr kCL

βpVDD-----------------=

11

Inverter Rise/Fall Time Equalization

• Fall, Rise times:

• To equalize rise, fall times:

tf kCL

knWL-----

nVDD

-------------------------------=

tr kCL

kpWL-----

pVDD

-------------------------------=

,

µn 2µp=( ) WL-----

p

2WL-----

n

≈ ⇒

12

Propagation Delays

• .∆t ∆QIavg--------- CL

∆VIavg---------= =

Vin

tpHL tpLHTime

VOL

VOH AB C DVOL + VOH

2

13

• , .tpHL CL

12--- VOH VOL–( )

Iavg------------------------------------= Iavg

IA IB+

2-----------------=

Propagation delay - t pHL

DS

800

700

600

500

400

300

200

100

0

V = 5.0 VGS

V = 4.5 VGS

V = 4.0 VGS

V = 3.5 VGS

V = 3.0 VGS

V = 2.5 VGS

V = 2.0 VGSV = 1.5 VGS

V [V]

DSI [µA]

5.04.03.02.01.0

VDD

GND

"1"

CL

AB

DS

GS

V [V]

= -5.0 V

-5.0-4.0

"

C

H

14

• , .tpLH CL

12--- VOH VOL–( )

Iavg------------------------------------= Iavg

IC ID+

2-----------------=

800

700

600

500

400

300

200

100

0

DS- I [µA]

V

-3.0-2.0-1.0

VDD

GND

0"

CL D

Propagation delay - t pL

e time

15

Inverter Switching

Vin

fall time ris

Time

VOL

VOH

VDD

VinVout

CL 90%

10%

D-- RpCL τ r= =

CL

Vout(t)

Ic

p

16

Inverter Rise/Fall TimeSimplifications:

tf kCL

βnVDD----------------- RnCL τ f= = = tr k

CL

βpVD---------------=

PMOS

NMOS

RPMOS

NMOSCL

Vout(t)

Ic

Rn

VDD

-----------

17

Inverter Sizing• Fall, Rise times:

• To equalize rise, fall times:

tf kCL

knWL-----

nVDD

-------------------------------=

tr kCL

kpWL-----

p

--------------------=

,

µn 2µp=( ) WL-----

p

2WL-----

n

≈ ⇒

VDD

3C

4/1

2/1

C

2C

Rp = R

Rn = R

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Inverter Sizing

VDD

2/1CL = Cn + Cp = 3C

4/1

Cn =Cn = C

Cp = Cp = 2C

Rp = R

Rn = R

tf = tr = 3RC

verters

3C

tdf

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Transistor sizing: Cascaded inVDDVDD

3C2/1

3C

4/1 4/1

2/1

VDD

4/1

2/1

A B

Vin

tdr

VOL

VOH

90%

10%

A B

tdr = tf1 + tr2

tdf = tr1 + tf2

ertersVDD

3C

4/1

2/1

VDD

2C

2/1

2/1

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Transistor sizing: Cascaded inv• tdf = R3C + R3C = 6RC

tdr = R3C + R3C = 6RC

• tdf = 2R2C + R2C = 6RC

tdr = R2C + 2R2C = 6RC

VDD

2/13C

4/1

VDD

2/12C

2/1

(long buses,

2 - 5

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Stage Ratios

C L

a1 a2 a3

Problem:Driving large load capacitancesI/O pads)

Solution:Inverter chain with stage ratio a=

L

0 C

1, tdr = 208RC

2, tdr = 41RC

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Stage Ratios

tdr = R(2aC) +

C

a1 a2 a3

CL= 10

for a =

for a =

(2R/a)(2a2C) +

(R/a2)(2a3C) +

(2R/a3)(CL)

= 8RaC + 2RCL/a3

DD

Vout

Rp Rp

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Sizing multi-input gates

tf kCL

βn

3-----VDD

-----------------=

tf = 3RnCL

tr = RpCL

V

in3

in2

in1

Rn

Rn

Rn

Rp

nCL

RpCL

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Sizing multi-input gates

VDD

GND

Out

B

A

B

C

C

A

tf = R

tr = 3

RnCL

RpCL

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Sizing complex gates

VDD

GND

Out

B

C

B

CA

D

A

D

tf = 3

tr = 2