a high-performance all-enhancement nmos

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1070 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979

Shunichi Suzuki was born on August 25, 1940.

He received the B.E. degree from Kyoto Uni-

versity, Kyoto, Japan, in 1963.

He joined the Nippon Electric Company, Ltd.,

Kawasaki-shi, Japan, in 1963 and has been en-

gaged in research and development of magnetic

plated wire memory. From 1968 to the present

he has been working on semiconductor memory,

particularly silicon Schottky-gate FET, DMOS,

and short-channel MOS technologies. He is

currently a Research Manager at the Centrrd

Masaki H irata was born in Hiroshima, Japan,

on March 9, 1949. He received the B.S. and

M.S. degrees in electronic engineering from the

University of Electronics Communication,

Tokyo, Japan, in 1970 and 1972, respectively.

He joined the Nippon Electric Company,

Ltd., Kawasaki, Japan, in 1972. He has been

working in MOS circuit design. His current

research interests are in sensor devices.

Mr. Hirata is a member of the Institute o

Electronics and Communication Engineers oResearch Laboratories, managing a group in semiconductor digitaJ and Japan.

analog circui ts and systems.

Mr. Suzuki is a member of the Institute of Electronics and Com-

munication Engineers of Japan.

A High-Performance All-Enhancement NMOS

Operational Amplifier

IAN A. YOUNG, MEMBER, IEEE

Abstract –An NMOS operational amplifier has been designed and

fabricated using only enhancement mode MOSFET’S in a circuit that

employs a novel feedforward compensation scheme. Specifications

achieved include high open loop gain (2200), low-power (15 mW or less

depending on the load), fast settling time (0.1 percent setting time in

3 s for a 4 V input step and a 10 pF load), and small area. While this

amplifier uses only a small number of transistors, its performance is

comparable to that of recent depletion load amplifiers. Fewer critical

steps are needed to fabricate this amplifier, making it attractive for

large arialog/digi ta f LSI c ircui ts.

I. INTRODUCTION

THE REALIZATION of an internally compensated MOS

amplifier has made possible the complete integration of

analog and digital subsystems on a LSI chip. For example”,

A-D and D-A converters, tone generators, CODEC’S, CCD,

and switched-capaci tor filters have each been fully integrated

in a MOS technology, some in CMOS and others in NMOS. In

CMOS the operational amplifier design was found to be quite

straightforward due to the availability of complementary

devices which produce high gain per stage. In NMOS the first

internally compensated amplifier [1] used only enhancement

transistors and achieved the moderate gain of 200 which wassufficient for its design application in a CODEC. However,

CCD transversal filters [2] and the more recently developed

switched-capacitor recursive filters [3] required an amplifier

Manuscript received May 1, 1979; revised September 5, 1979. This

research was sportsored by the National Science Foundation under

Grant ENG73-01484-A01.

The author wa with the Department of Electrical Engineering and

Computer Science, University of California, Berkeley, CA 94720. He

is now with the Mostek Corporation, Carrollton, TX 75006.

with a gain between 1000 and 2000. It therefore became

attractive to realize an amplifier with this gain in single-

channel NMOS. The single-channel NMOS technologies are

the most cost-effective in terms of cost per unit digital or

analog function on the chip because of their high yield, low

fabrication cost, and the very dense digital” and analog circuit

packing density. Thus, provided the design difficulties can be

overcome, it is more’ cost-effective to realize these functions

in single-channel NMOS technology.When only enhancement transistors are used to realize an

amplifier, the gain obtained for each common source stage is

to a first-order dependent on the ratio of the (W/L) in the

common source transistor over the (lV/L) of the load tran-

sistor. The latter would have its gate connected to, the positive

supply voltage. As with the inverter design in digital circuits

it became clear that the depletion-type MOSFET, when used

as a load device in an inverter gain stage [4], would provide

more gain than an enhancement load having the same geom-

etry [5]. Here the depletion load device with its gate con-

nected to its source is ideally a constant current source.

Working against this ideal situation, however, is the fact that

the cleplet ion device is not grounded at the source. ’ Therefore,the output resistance of this current source is degraded as the

output voltage changes, varying the back gate bias and modify-

ing the threshold voltage through the body effect.

Within the category of single-channel MOS design alterna-

tives the ability to realize the high-performance general-

purpose MOS amplifier with only enhancement MOSFET’S is

attractive for a number of reasons. MOS circuits that use only

enhancement MOSFET’S are easier to design and manufacture,

especially with regard to insensitivity to variati~ns in device-

001 8-9200/79/1 200-1070 00.75 @ 1979 IEEE



YOUNG: ALL-ENHANCEMENT NMOSOP AMP 1071

M15

M13

OUT

j M14 M16

“PUT

.+BODY BIAS–

a)

SOURCE

FOLLOWER

DIFFERENTIAL SOURCE GAIN STAGE OUTPUTINPUT STAGE FOLLOWER STAGE

b)

Fig. 1. a) NMOS operational amplifier with only enhancement tran-

sistors). Cc= 11 pF. b) Block diagram description of the amplifier

circuit in a).

threshold voltages. This will help increase the yield, together

with the fact that there is one less mask required to process

this circuit. In a standard digital enhancement/depletion

NMOS process, on 10-15 Q . cm material, the depletion tran-

sistor threshold voltage VTD) is not as well defined as the

enhancement threshold voltage VTE). In addition, the body

factor for the depletion device is not low enough to allow a

depletion load inverter formidably higher gain than an en-hancement load inverter could realize in the same area. The

enhancement/depletion amplifier has to maintain dc operating

points where all devices are in the saturation region for worse

case VTD and VTE variations. Additional circuitry is often

needed to improve the insensitivity of the design to these

variations.

While the basic superiority of the depletion device might

be correct when analyzing an inverter from a small signal

point of view, it is not necessarily true that use of this device

in an overall amplifier design results in a general-purpose

operational amplifier of superior performance to one designed

using only enhancement MOSFET’S. A high-performance

internally compensated amplifier that uses solely enhance-ment MOSFET’S is described along with experimental results

in this paper. It compares favorably with a recent depletion

load amplifier desi~ [5] in all aspects including silicon area.

It is interesting to also note that some high-performance

memory circuits do not have a depletion transistor in their

design. [9]

Fig. l a) shows the basic circuit diagram of the operational

amplifier to be described in this paper. Some devices have

been left out for clarity at this point. The complete circuit

will be given later. A block diagram for this amplifier circuit,

shown in Fig. 1 b), illustrates the signal paths. The input stage

is a source-coupled pair forming a differential input with one

single-ended output as in a paraphase amplifier). This drives

a second gain stage through a source follower level shift. The

second gain stage consists of a driver and enhancement load,

whose gate is biased by the voltage present on the second out-

put of the differential input stage, rather than the VDD supply.

This connection provides a feedforward path with small phase

shift at high frequencies. The second gain stage has a feedback

capacitor to realize a dominant pole through Miller compensa-

tion. This simple two transistor gain stage drives a shunt-

shunt feedback output stage. The bias points in the circuit are

interdependent such that all devices in the circuit track one

another through proper choice of device geometry. These gain

stages remain in their high gain active region independent of

VT and mobili ty variations.

II. AMPLIFIER CIRCUIT DESCRIPTION

A. Process Description

The amplifier was fabricated as part of a fully monolithic

switched-capacitor recursive falter using n-channel Al-gate

MOS technology. No p+ isolation diffusion was employed;however a low resistivity p-type substrate 1 -2 Q . cm/5X 1015

boron atoms/cm3) was used to raise the field threshold to

more. than +20.0 V with a small substrate bias applied. The

enhancement device threshold was 0.2 V for zero substrate

bias. To simulate higher threshold voltages, more typical of

industrial processing, a substrate bias of-5 V was used so that

the effective threshold of the devices, whose source is con-

nected to - V~~, was 1.5 V. The range of threshold voltages

that can be present throughout the circuit and body effect

will, of course, be different from that if the circuit were

realized with devices having VT = 1.5 V without a substrate

bias. The use of a substrate bias is justified, however, by the

fact that the circuit operation is based on threshold voltagetracking rather than exact threshold voltages.

B. The Input Stage

The input stage is drawn in Fig. 2 with the layout W/L de-

vice sizes shown in microns. This amplifier is operated only

with its positive input grounded in the switched-capacitor

recursive falters; therefore, wide common mode range is not

necessary. During transient conditions, however, 445 and lf6

can be driven hard out of their saturation region if the quies-

cent voltage drops across IW4 and J47 are large. In this case,

iW5 and lt f6 would be operating too close to VDSAT, the drain-

to-source saturation voltage, Thus, to avoid large transient dis-

tortion arising from the input stage, the voltage drop acrossA44 and J147was limited to 6 V when the amplifier was biased

from V~~ = +10 V, V~~ = -10 V, VBB = -15 V supplies.

The single-ended gain of this input stage is given by

/n

w

15 w

dvm .1AV, =

X4

‘VINDIFF 2 1

1)

1+;dvD~ + VBB + 2@~




+VDD

‘

L (ML12/152

M7

?

J

12/152

–v:~

Fig. 2. Differential input stage. The channel width W) and length L)

is shown in microns for each transistor W/L).

where

y = body factor;OF= bulk silicon Fermi potential;

V’BB = substrate bias relative to ground;

VD ~ = drain voltage of Jf5 relative to ground.

With device sizes shown, the gain from the differential input

to the single-ended output is 12. Only one-half of the avail-

able differential gain has been exploited to enable the advan-

tageous use of feedforward for phase compensation of the

overall amplifier.

The common-mode gain of the input stage is controlled by

the output resistance

by

1

AVCm=—2r. gm84

where rfl. is the small

of M8. The common-mode gain is given

2)

signal output resistance of Jf8 and g~~ is

the sm~ signal transconductance of kf4. By increasing the

channel length of lf8 one can reduce the common mode gain.

The common mode gain of the input stage is approximately

0.04 with the device sizes as shown in Fig. 2.

C. Source Follower Level Shift

The single-ended output from the input stage is applied to

the gate of M9, a source follower which dc level shifts the

signal down in voltage to drive the gate of Ml 2, the second

gain stage’s driver device. Ml O, whose gate is controlled by

the same dc voltage as M3, provides the quiescent current to

bias the source follower. Fig. 3 shows the circuit for this

source follower and the second gain stage which it drives.

The voltage gain of this source follower is described by

A~ s)=-—gm, + scl

.gm,—+ J++-+ S C1+C2)ag rO9 010

where

3a)

+VDD?L

T 1

‘D’” *51~5 + M1O k

M12254/12

25L/12

- v:~

Fig. 3. Source follower driving the second gain stage. Cc= 11 pF.

-0

V3

+

V,N S)z vou~ s)

+ +

-Avz

Fig. 4. Small-signal block diagram of the circuit in Fig. 3. Small-signal

components at VD4 and VD7 are out of phase with each other.

Cl is total capacitance between input and output mostly Cg,,),

and C2 is the total capacitance between the source follower

output and ground.

At low frequencies, and since rO for the devices is large com-

pared to l/gm9, 3a) becomes

AV 0)=C19. 3b)

The value of this gain is 0.89. The output impedance is

given by

ROUT = -+ llrOQllrO,O. 4)~m9 “-

This impedance when multiplied with the sum of the input

capacitance to Ml O, the total junction capacitance connected

to this node, and the Miller multiplied feedback capacitance

Cc, forms the dominant pole in the amplifier.

D. Second Gain Stage

The second gain stage is a simple inverter in which the load

device has its gate biased by the voltage at VD7 the second

output of the differential input stage). The low-frequency

gain for this stage is given by

gin,,

AV, =—.1

5)gw,, ~ + 7

2dv~12 + v~~ + 2@p’

Note that the gain in this enhancement load inverter is not as

strongly dependent on ~ as the depletion load inverter [5],

and therefore is less process dependent .

The output of this stage forms the summing node for the

feedforward path that provides some phase compensation in

this three stage amplifier. Fig. 4 illustrates the principle of the

feedforward compensation. A ~, is the high-gain, low-frequency

amplifier stage with two poles and one zero, the latter arising



YOUNG: ALL-ENHANCEMENT NMOS OP AMP1073

from the source follower (3a). Av, isthelow-gain (a simple

source follower in fact) high-frequency stage with one pole

and one zero that are close to each other. This feeclforward

stage provides a low phase shift path athigh frequencies. This

path maintains the frequency stability of the amplifier. Based

upon CgS and cgd in the devices and the lumped parasitic

capacitances from nodes 1 and 2 to ground

A y2(S) =‘V2(” 3(1+3

(1+:)(1+:)

( )

A~3(o) 1 +:

A ~3(s) =

()

1+1

P3

(6)

(7)

A ~,(s) describes the signal path from V~4 to the output of

the circuit in Fig. 3, while A v, (s) describes the signal path

from V~7 to the output. The compensation capacitor Cc, in

addition to introducing a dominant pole, also introduces a

right half-plane zero corresponding to a=, = (gm,, /Cc) [6].

This right half-plane zero occurs at a low frequency because of

the low transconductance from the MOS device. This is highly

undesirable since it degrades the phase of the complete ampli-

fier by 90” at high frequencies while at the same time stops

the 20 dB/decade rolloff created by the dominant pole in the

magnitude response.

The overall transfer function for the scheme in Fig. 4 is

W =A ~ToT(s) =AV,(S)+A V,(S). (8a)

With the substitution of (6) and (7) and refactorization, thisequation takes the form

A ~ToT(S) = {A v,(”)+ A v,(”)}

The feedforward path has introduced new zero IIocations,

which can be used to compensate the whole amplifier. P1 is

the dominant pole produced by the Miller compensation

capacitance Cc. The finrd location of the zeros is determined

mainly by PI and the original zeros Z2 and Z3, the latter being

contro lled by Cg~, and Cgs,,. The design must ensure that any

zeros below the unity gain crossover frequency are placed as

close as possible to their matching pole. This is neeessary to

avoid any “doublet” contributing a large slow settling compo-

nent to the transient response [7].

E. Output Stage

The output stage is shown in Fig. 5. The use of shunt-shunt

negative feedback allows this circuit to realize a moderate

amount of gain while being broad-band in nature [1], [4].

k

m-15

16/18

M13 t-----12/51

‘T--b

Fig. 5. Output stage,

Also the output impedance, 1/gml,, of the Ml 5/ ll 6 inverter,

is reduced by the loop-gain gn, c/g~,,. This allows a lower

output impedance with less quiescent current in Ml 5 and Ml 6

than when feedback is not employed. The gain of this output

stage, assuming negligible body effect, is given by

r gin,, 1

‘“ ’=i g’sk.l()—L lb——

r)—L14X. ——

()

w

z ~’3

(9)

The device geometries were chosen such that: 1) the input

capacitance to this stage did not load the output of the second

gain stage, 2) the amplifier had a fast transient response with

10 pF connected directly I o the output (t2 V step in under

3.5 I-N), and 3) maximum output voltage swing was achieved.

F. VT Insensi tive Biasing

The complete amplifier, shown in Fig. l(a), derives its dc

biasing from the three transistor string Ml, 1142,and Jf3, each

of which is always in saturation because their gate and drain

are connected. The quiescent voltages in the circuit are de-

signed to track and maintain all devices, up to IW14, in the

saturation re@on independent of the value of VT. This is

based on the fact that the VT and mobility of the devices in

the circuit will track, even though the absolute value might

vary across the wafer.

The quiescent voltage tracking will now be explained.

(W/L)n denotes then transistor’s geometric ratio after lateral

diffusion has been taken into account. The input stage is

symmetrical, such that for z,erodifferential input, VGsq = VGsT,

independent of VT. Geometries (W/L)lO, (W/L)8, and (W/L)3




Fig. 6.

k s

Enhancement NMOS operational amplifier. CB, = CB, = 3.8 pF;

cc=7pF+14pF.

are all the same, so that 110 =18 =13 = 11. Therefore, a current

of Ii/2 flows through M4 and M7. Since W/L q = W/L 7 =

~ W/L l, therefore, VGSI = VGS4 = VGS,. This means that

~Gs, + VGS, = ~GS, + ~Ds, O= ~Gs,, ~ ~Ds,2. The choice Of

W/L , / W/L 3 = W/L 9/ W/L 10 results in VGs2= VG~, and,

therefore, VDG,O= O with V~~lo = VGs10= VGs, in epen ent

of VT. Now since V~s, ~= VGs,, and if W/L z/ W/L 3 =

W/L l ,/ W/L 12 then VGs2 = VGSII and V~Gl, = O. Thus,

V~s,2 = VGs,, = V~s10 = VGs, independent of VT. As long as

VT> O, Ml O and Ml 2 will remain in the saturation region

where their transconductance is high and II ~= II ~. The geom-

etries were chosen such that the quiescent current in M3, M8,

M1O, andikl12is 20pA when V~~ = +IOV, V~~ = -IOV, and

VBB = -15 V. This choice consumed minimum power while

also providing good frequency response from the input stage

and high slew rate when charging the compensation capacitor.

G. Complete Amplifier

The excessive area associated with a very long load device in

the second gain stage can be reduced somewhat by using asplit-load inverter consisting of two devices, with their gate

tied to their drain, connected in series. The two series devices

can produce the same small-signal resistance as the one tran-

sistor load, while requiring less total length for the transistors.

The complete circuit for the amplifier is shown in Fig. 6, with

the device geometries given in Table I.

Bypass capacitance has been introduced into the two source

follower signal paths in order to lower the dominant zero

frequency and move it closer to the second dominant pole.

This enables the unity gain bandwidth to be increased from

1.5 MHz up to 3 MHz with two bypass capacitors of 3.8 pF

and Cc = 14 pF. The phase margin was increased from 45° to

55° When CC = 7 pF the slew rate is higher; however, the

time over which damped oscillation occurs is longer.

Finally, common mode feedback was used in the input stage

as shown in Fig. 6. Ml’ and Ml sense the common mode

voltage at nodes V~4 and VD7 of the input stage, and control

the current into the lf3, M8 current mirror. Thus, if the com-

mon mode output voltage for the input stage increases, then

the current through M3 increases and is mirrored into the

current source M8< This increased current in M8 causes

the common mode output voltage to remain unchanged from

the original value. Thus, more control has been placed on the

dc operating points of VD4 and VD7 in the input stage. This

TABLE 1

M4s~ llEVICE DIMENSIONS FOR THE AMPLIFIER CIRCUIT IN FIG, 6

DEVICE W pm L pm

Ml 12.7 396.2

Ml’ 12.7 396.2

M2 12.7 203.2

M3 254 12.7

M4 12.7 152.4

M5 254 12.7

M6 254 12.7

M7 12.7 152.4

M8 254 12.7

M9 12.7 203.2

M9 ‘ 12.7 203.2

kilo 254 12.7

ml 12.7 203.2

l’ 12.7 203.2

Mlz 254 12.7

N13 12.7 50.8

M14 190.5 12.7

M15 12.7 38.1

M16 254 12.7

VOUT VOLTS

A

7 -

6 -

5 -

L -

3 -

2

1

0.

-1 -

-2 -

-3

-L -

-5-

-6 -

Fig. 7. Simulated dc amplifier characteristics of the NMOS amplifier.

VDD V,yS = 20V; VBB - V8S = -5 V.

technique increased the common mode rejection ratio for the

overall amplifier.

H. Simulated Performance

Computer simulation was done using the circuit analysis

program SPICE2. The device model parameters were deter-

mined from experimental characteristics of devices that were

fabricated with the process described in Section I. For V~D =

10 V, Vss = -10 V, VBB = -15 V, the dc transfer characteris-

tic of the amplifier is given in Fig. 7, and the frequency

response in Fig. 8 a and b .



YOUNG: ALL-ENHANCEMENT NMOS OP AMP1075

,.2 ~03 ,.4

PHASE DEG]

,@

a

,.6107 FREQUENCY

[ HERTZ

102 103 IOL 105 106 107 FREQUENCY

b[ HERTZ

Fig. 8. a Magnitude response of the NMOS~plifier from simulatioln.

b Phase response of the NMOS amplifier from simulation.

III. EXPERIMENTAL RESULTS

The all-enhancement NMOS amplifier was fabricated with

the Al-gate NMOS technology described in Section II-A. A die

photograph of the amplifier is shown in Fig. 9. The circuithad minimum dimensions of 12 ~m. The die arei~ for the

amplifier excluding bonding pads was 0.32 mm2 or 500 mils2.

Table II contains the measured performance from a sample

of eight amplifiers on two different wafers. The dc transfer

characteristic for this operational amplifier can be seen in

Fig. 10. The power supply voltages were VDD =+1 O V,

V~~ = -10 V, VBB = -12.5 V. Fig. 11 provides information

about the common mode input range and the common mode

rejection ratio. This photograph is a trace of the input offset

voltage as a function of common mode input voltage. Fig. 12

“ ‘DD

Fig. 9. Microphotograph of the amplifier.



1076 IEEE JOURNAL

TABLE H

PERFORMANCE PARAMETERSOF THE NMOS AMPLIFIER BASED UPON A

SAMPLE OFEIGHT AMPLIFIERS ON Two DIFFERENT WAFERS

Power Supplies: VDD = + 10.0 V, VSS = - 10.0 V

Substrate bias = - 2.5 (VBB = - 12.5 V)

Low Frequency Gain Mean

Low Frequency Gain Standard Deviation

Input Offset Voltage Mean

Input Offset Voltage Standard Deviation

Common Mode Input Range

Common Mode Rejection Ratio (at zero

common mode input voltage)

Positive Power Supply Rejection

Negative Power Supply Rejection

Slew Rate

Step Response Settling Time to O.1 :

fOra OVto+l Vstep:

fOra OVtO-l Vstep:

f0ra-2Vt0+2V step:

f0ra+2Vto-2V step:

Output Voltage SwinS

Total Input Referred Noise

(O to 50 kHz bandwidth)

Power Conswnpt ion

2200

200

- 20 mv

5 ml’

+ 5. Ovto-8.5V

72 dB

SO dB

74 dB

+ 5 vf~sec, - 2 Vlvsec

2.0 vsec

2.0 usec

3.5 usec

3.0 lJsec

+3.2 vto-7.4v

60 to SO UV I’lUS

15 mW

OUTPUT (VOLTS)

+6

+L

+2

o –

-2 –

-L -

-6 –

-8~I I I I I I

-20 -lo 0 10 20

DIFFERENTIAL INPUT [ mV]

Fig. 10. Measured dc transfer characteristic of the NMOS operational

amplifier. Input offset was –18 mV, but is set to zero in the above

curve: VDD – VSS = 20 V; VBB - VSS = -2.5 V.

shows some step responses of the operational amplifier when

connected as a unity gain buffer with around 10 pF directly

on the output. The measured power consumption was 15 mW,

By reducing the load drive capability of the design, this power

could be reduced to less than 5 mW.

IV. CONCLUSIONS

The results of this work have shown that an internally com-

pensated operational amplifier with good overall characteris-

tics can be realized with single-channel MOS technology and

OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979

COMMONMOOE—

‘UT

.:; 1

+4

+2

o –

-2 –

-L –

-6 –

L-L&&.&-20 -lo

INPUT OFFSET (mV)

Fig. 11. Common mode input performance of the NMOS amplifier.

OUTPUT

1 V/div

+2

+1

o -

-1

-2 –

OUTPUT

1 Vid v

r+2

+1

o

-1

-2

1

(a)

~2 pec/dlv

(b)

Fig. 12. Measured transient response of the NMOS operational ampli-

fier in the unity g~in connection with a 10 pF load.

only enhancement mode transistors. The gain achieved (2200)

was higher, the power consumption (15 mW for *1 O V supply

voltages) was lower and the silicon area was srnallei-than any

previous all-enhancement MOSFET operational amplifier

design. The unity gain settling to 0.1 percent was 3 MS for a

* 2 V input step and a 10 pF capacitive load. These character-

istics are similar to those for the general-purpose depletion

load operational amplifier described in [5]. The advantage of

the all-enhancement amplifier design techniques is that the

overall performance of the circuit is far less dependent on

processing parameters (e.g., body factor and VTD) than the

depletion load amplifier design. This leads to a lower cost,

higher yielding alternative for large-scale integration of analog

systems that require multiple operational amplifiers on the

one die.



IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC.14, NO. 6, DECEMBER 1979 1077

ACKNOWLEDGMENT

The author wishes to thank Dr. B. J. Hosticka, Prof. P. R. ,6]

Gray, and Prof. Y. P. Tsividis for their helpful comments.

[1]

[2]

[3]

[4]

[5J

REFERENCES[7]

Y. P. Tsividis and P. R. Gray, “An integrated NMOS operational

amplifier with internal compensation,” IEEE J, Soli State Cir- [8]

cuits, vol. SC-11, pp. 748-753, Dec. 1976.

C. H. Sequin and M. F. Tompsett, “Charge transfer devices,” in [9]Advances in Electronics and Electron Physics. New York: Aca-

demic. 1975.

R. W. “Brodersen, P. R. Gray, and D. A. Hodges, Proc. IEEE, vol.

65, Jan. 1979.B. J. Hosticka, “MOS sampled-data recursive fiiters using state

variable technique s,” Ph.D. dissertation, Univ. of California,

Berke ley, 1977. Ian

NMOS operational amplifier,” IEEE J. Solid-State Ctrcuits, vol.

SC-13, pp. 760-766, Dec. 1978.

Y. P. Tsividis, “Design considerations in single-channel MOS

analog integrated circuits –A tutorial,” IEEE J, Solid-State Cir-

cuits, vol. SC-13, pp. 383-391, June 1978.

R. J. Apfel and P. R. Gray, “A fast-settling monolithic operational

amplifier using doublet compression techniques,” IEEE J. Solid-

State Circtiits, vol. SC-9, Dec. 1974.

C. N. Ahlquist et al., “A 16,384 bit dynamic RAM,” IEEE J. Solid-

State Circuits, vol. SC-1 1, ]pp. 570-574, Oct. 1976.

P. R. Schroeder and Robert J. Proebsting, “A 16K X 1 bit dynamicRAM,” Digest Int. Solid-State Circuits Conf. (Philadelphia, PA,

Feb. 1, 1977), pp. 12-13.

A. Yourrz C3’73-M’78), for a photograph and biography, see this

D. Senderowicz, D. A. Hodges, and P. R. Gray, “High performance issue, p. 10331

End of Special Section

Nonlinear Signal Processing with Carrier

Domain Devices

ALBERT C. VAN DER WOERD

Abstract –A new design method for nonlinear signal processing cir-

cuits is presented. The principle is based on carrier domain moving,

occurring in a planar transistor structure of special design,, The em-

ployed geometries are variants of the geometry employed by Smith

for his carrier domain multiplier [3]. The design method involves the

calculation of the domain locus corresponding to a predetermined

arbitrary transfer function. The method has been applied to two

examples, which have been realized in practi cal devices.

I. INTRODUCTION

NONLINEAR analog signal processing circuits are widely

used in electronic systems. Some examples are signal

compressing and expanding circuits in audio systems, gamma

correctors in video systems, and triangle-sine converters in

function generators. Prevailing circuits commonly employ a

combination of several basic nonlinear network elements

Manuscript received May 25, 1978; revised July 17, 1979.

The author is with the Department of Electrical Engineering, Delft

University of Technology, Delft, The Nether lands.

such as p-n junctions. In practice this has sometimes led to

quite complicated circuits with relatively low bandwidth.

In this paper a method fo~rperforming nonlinear signal pro-

cessing based on the carrier domain principle wil l be presented.

The concept was first introduced by Gilbert [1] and is also

mentioned in [3] , When this approach is used the actual non-

linear operation is executed by only one network element: a

carrier domain device (CDD). Because the high bandwidth and

the noise properties of such devices are promising [2] , a com-

parison with common circuits is useful. In this paper, however,only the development of some new CDD geometries is described.

We start by giving a brief description of the idea of the car-

rier domain principle adapted to our special aim. Generally

speaking, a carrier domain device is an element comprising an

extended bipolar transistor structure where the carrier in-

jection is compressed into a small area (domain) by enforced

emitter crowding; in addition, this domain, and hence the

signal transfer, can be changed by an external variable. Gilbert

applied this principle to his new four-quadrant multiplier [2] ,

0018 -9200/79 /1200 -1077 00.75 01979 IEEE

a high-performance all-enhancement nmos

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