ee141 – fall 2005 lecture...

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EE141 – Fall 2005Lecture 4

The MOS TransistorThe MOS TransistorMOS Transistor ModelMOS Transistor Model

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Important!

Discussions and Labs start next week!

You must show up in one of the lab sessionsnext week• If you don’t show up you will be dropped from the

class (unless you let me know that you still want to be in the class)

Homework 2 due next Thursday, September 15

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TAmtng

* Discussion sessions will cover identical material

Mon

Tue

Wed

Thu

Fri

Lec(Dejan)

203 McLaughlin

Lec(Dejan)

203 McLaughlin

OH(Dejan)511 Cory

DISC*(Ke)203

McLaughlin

9 10 11 12 1 2 3 4 5 6 7

Lab(Louis)353 Cory

Lab(Louis)353 Cory

OH(Ke)

197 Cory

OH(Lynn)197 Cory

ProblemSets Due

Lab - NEW(Lynn)353 Cory

Lab (Ke) 353 CoryDISC*(Lynn)

293 Cory

Your EE141 Week at a Glance

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Agenda

Last Lecture• Design metrics• MOS manufacturing process• Design rules

Today’s Lecture• Basic MOS transistor operation• Large-signal MOS model for manual analysis• The CMOS inverter at a first glance

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The MOS Transistor

Polysilicon Aluminum

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Design Rules

Interface between designer and process engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width• Scalable design rules: lambda parameter• Absolute dimensions (micron rules)

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CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

RedBlue

MagentaBlack

BlackBlack

Select (p+,n+) Green

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Layers in 0.25µm CMOS Process

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Design Rules

Intra-layer: widths, spacing

Inter-layer: enclosures, overlaps• Transistor rules• Contact and via rules• Well and substrate contacts

Special rules (sub-0.25µm)• Area, antenna rules, density rules

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Intra-Layer Design Rules

Metal2 4

3

10

90

Well

Active3

3

Polysilicon2

2

Different PotentialSame Potential

Metal1 3

32

Contactor Via

Select2

or6

2Hole

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1

2

5

3

Tran

sist

or

Inter Layer: Transistor Rules

Tran

sist

or

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Inter Layer: Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

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1

3 3

2

2

2

WellSubstrate

Select3

5

Inter Layer: Well and Substrate

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Example: CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

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Layout Editor – MicroMagic

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Layout Editor –Cadence Virtuoso

In1 In2Out

vdd

gnd

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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important

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Outline

MOS TransistorMOS Transistor• Basic Operation• Modes of Operation• Deep sub-micron MOS

CMOS InverterCMOS Inverter

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What is a Transistor?

|VGS|

A MOS Transistor

|VGS| ≥ |VT|

S DRon

A Switch!

S D

G

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Switch Model of CMOS Transistor

|VGS|

S D

G

|VGS| < |VT| |VGS| > |VT|

Ron

S D S D

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NMOS and PMOS

VGS > 0

S D

G

VGS < 0

S D

G

NMOS Transistor PMOS Transistor

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S

D

G B

S

D

G

S

D

G

S

D

G

NMOS Enhancement NMOS Depletion

PMOS Enhancement NMOS withBulk Contact

MOS Transistors:Types and Symbols

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Outline



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n+

p-substrate

DSG

B

VGS

+

–

Depletionregion

n-channel

n+

Threshold Voltage: Concept

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The Threshold Voltage

( )FSBFTT VVV φφγ 220 −+⋅+=

i

ATF n

Nln⋅= φφ

Threshold

Fermi potential

2ΦF is approximately −0.6V for p-type substratesγ is the body factorVT0 is approximately 0.45V for our process

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The Body Effect

-2.5 -2 -1.5 -1 -0.5 00.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VBS

(V)

VT (V

)

VT0

reverse body bias

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The Drain Current

[ ]TGSoxi VxVVCxQ −−⋅−= )()(ox

oxox t

C ε=

Charge in the channel is controlled by the gate voltage:

Drain current is proportional to charge and velocity:

WxQxI inD ⋅⋅−= )()(υ

dxdVxx nnn ⋅=⋅−= µξµυ )()(

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The Drain Current

( ) dVVVVWCdxI TGSoxnD ⋅−−⋅⋅⋅=⋅ µCombining velocity and charge:

Integrating over the channel:

( )

−⋅−⋅⋅=

2

2DS

DSTGSnDVVVV

LWkI ’

Transconductance:ox

oxnoxnn t

Ck εµµ ⋅=⋅=’

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Outline



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n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

Transistor in Linear ModeVGS > VDS + VT

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n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Transistor in Saturation

Pinch-off

VT < VGS < VDS + VT

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Saturation

For VGD < VT, the drain current saturates:

( )22 TGSn

D VVL

WkI −⋅⋅=’

Including channel-length modulation:

( ) ( )DSTGSn

D VVVL

WkI ⋅+⋅−⋅⋅= λ12

2’

CLM

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Modes of Operation

Cutoff:

VGS < VT

Resistive:VGS > VDS + VT

Saturation:VT < VGS < VDS + VT

( )

−⋅−⋅⋅=

2

2DS

DSTGSnDVVVV

LWkI ’

( )22 TGSn

D VVL

WkI −⋅⋅=’

0=DI

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QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Current-Voltage Relations:A Good Ol’ Transistor

VDS (V)

I D(A

)

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A Model for Manual Analysis

S

DG

ID

( )

−⋅−⋅⋅=

2

2DS

DSTGSnDVVVV

LWkI ’

( ) ( )DSTGSn

D VVVL

WkI ⋅+⋅−⋅⋅= λ12

2’

( )FSBFTT VVV φφγ 220 −+⋅+=

VDS > VGS – VT

VDS < VGS – VT

with

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Outline



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LinearRelationship

-4

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

EarlySaturation

Current-Voltage Relations:The Deep Sub-Micron Era

VDS (V)

I D(A

)

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Velocity Saturation

ξ (V/µm)ξc = 1.5

υn

(m/s

)

υsat = 105

Constant mobility (slope = µ)

Constant velocity

Velocity saturates due to carrier scattering effects

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Velocity Saturation

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD

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ID versus VGS

0 0.5 1 1.5 2 2.50

1

2

4

5

6x 10-4

Long Channel

Short Channel

quadraticlinear

quadratic

VGS (V)

I D(A

)

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Regions of Operation

-4

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5 x 10VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6 x 10-4

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V


VDS = VGS - VT

VDS (V) VDS (V)

I D(A

)

I D(A

)

ResistiveVelocitySaturation

Long Channel(L=10µm)

Short Channel(L=0.25µm)W/L=1.5

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Including Velocity Saturation

c

n

ξξξµυ

+⋅

=1

In deep submicron, there are four regions of operation:(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation

Approximate velocity:

satυυ =

for ξ ≤ ξc

for ξ ≥ ξc

And integrate current again:

( ) ( )

−⋅−⋅⋅

⋅+⋅

=21

2DS

DSTGScDS

oxnD

VVVVL

WLV

CIξ

µ

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ID versus VDS

-4

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5 x 10VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6 x 10-4

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V


VDS = VGS - VT

VDS (V) VDS (V)

I D(A

)

I D(A

)

Long Channel(L=10µm)

Short Channel(L=0.25µm)

Early Saturation

W/L=1.5

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Regions of Operation

LinearRelationship

-4

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

VelocitySaturation

VDS (V)

I D(A

)

VDS = VGT

VDSAT = VGT

Saturation

Linear

VDS = VDSAT

Define VGT = VGS – VT VDSAT ≈ L·ξc

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A Unified Model for Manual Analysis

B

D

G

ID

S

( )DSGTD VVVVL

WkI ⋅+⋅

−⋅⋅⋅= λ1

2'

2min

min

for VGT ≤ 0: ID = 0

with Vmin = min (VGT, VDS, VDSAT)

for VGT ≥ 0:

define VGT = VGS – VT

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Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS (V)

I D(A

)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

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A PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

Assume all variables negative!

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

VDS (V)

I D(A

)

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Sub-Threshold Conduction

0 0.5 1 1.5 2 2.510

-12

10-10

10-8

10-6

10-4

10-2

VGS (V)

I D(A

)

VT

Linear

Exponential

Quadratic

Typical values for S:60 – 100 mV/decade

The Slope Factor

ox

DnkTqV

D CCneII

GS

+=1 ,~ 0

S is ∆VGS for ID2/ID1 =10

VGS (V)

I D(A

)

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Transistor Model for Manual Analysis

Textbook: page 103

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The Transistor as a Switch

VGS ≥ VT

S DRon

( ) ( )

⋅+⋅

+⋅+⋅

⋅=21

212

1

DDDSAT

DD

DDDSAT

DDeq VI

VVI

VRλλ

⋅⋅−⋅≈ DD

DSAT

DDeq V

IVR λ

651

43

ID

VDS

VDDVDD /2

VGS = VDD

Rmid

R0

( )021 RRR mideq +⋅=

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0.5 1 1.5 2 2.50

1

2

3

4

5

6

7 x 105

VDD (V)

Req

(Ohm

)

W/L=1, L=0.25µm

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Textbook: page 106

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Outline



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Vin Vout

CL

VDD

The CMOS Inverter:A First Glance

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Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

CMOS Inverter

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Two Inverters

Connect in Metal

VDD

Share power and ground

Abut cells

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VDD VDD

Vin = VDD Vin = 0

VoutVout

Rn

Rp

CMOS Inverter:First Order DC Analysis

VOL = 0VOH = VDD

VM = f(Rn, Rp)

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V outV out

R n

R p

V DDV DD

V in = V DDV in = 0

(a) Low-to-high (b) High-to-low

CLCL

CMOS Inverter: Transient Response

tpHL = f(Ron·CL)= 0.69 Ron·CL

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CMOS Properties

Full rail-to-rail swing

Symmetrical VTC

Propagation delay function of load capacitance and resistance of transistors

No static power dissipation

Direct path current during switching

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Future Perspectives

25 nm MOS transistor (Folded Channel)

ee141 – fall 2005 lecture...

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