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IC ManufacturingDesign Rules

EE141EE141-- Spring 2004Spring 2004Lecture 2Lecture 2

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OverviewOverview

1st LectureIntroduction

TodayWrap-up IntroIC manufacturing

TomorrowDesign metrics

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AdministriviaAdministrivia

Discussion sessions start this week. Only one this week We 2-3pm in 203 McLaughlinHomework 1 due on Th

If you have problems running SPICE, check with the TAs

Labs start next week!Make sure to get your card key coded for 353 CoryCourse accounts have been provided for the PCs in 353 Cory. Please check with the TAs.

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Productivity TrendsProductivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty

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Challenges in Digital DesignChallenges in Digital Design

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

∝ DSM ∝ 1/DSM

?

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Design Abstraction LevelsDesign Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

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Why Scaling?Why Scaling?

Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xHow to design chips with more and more functions?Design engineering population does not double every two years…Need to understand different levels of abstraction

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CMOSCMOSManufacturingManufacturingProcessProcess

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The MOS Transistor The MOS Transistor –– 3D Perspective3D Perspective

Polysilicon Aluminum

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CMOS ProcessCMOS Process

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A Modern CMOS ProcessA Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process

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Transistor LayoutTransistor Layout

p-well SiO2

poly

SiO2

n+

Cross-Sectional View

Layout View

poly

p-well

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Circuit Under DesignCircuit Under Design

This two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.

VDD VDD

VinVout

M1

M2

M3

M4

Vout2

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CMOS InverterCMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

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Two InvertersTwo Inverters

Connect in Metal

Share power and ground

Abut cells

VDD

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oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

PhotoPhoto--Lithographic ProcessLithographic Process

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Patterning of SiO2Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

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CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

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CMOS Process WalkCMOS Process Walk--ThroughThrough

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

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CMOS Process WalkCMOS Process Walk--ThroughThroughSiO2

(d) After trench filling, CMPplanarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p

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CMOS Process WalkCMOS Process Walk--ThroughThrough

(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2

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CMOS Process WalkCMOS Process Walk--ThroughThrough

(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.

AlSiO2

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Advanced Advanced MetalizationMetalization

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Advanced Advanced MetalizationMetalization

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Design RulesDesign Rules

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Design RulesDesign Rules

Interface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line width

scalable design rules: lambda parameterabsolute dimensions (micron rules)

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CMOS Process LayersCMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green

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Layers in 0.25 Layers in 0.25 µµm CMOS processm CMOS process

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IntraIntra--Layer Design RulesLayer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole

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Transistor LayoutTransistor Layout

1

2

5

3

Tra

nsis

tor

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ViasVias and Contactsand Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

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Select LayerSelect Layer

1

3 3

2

2

2

WellSubstrate

Select3

5

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CMOS Inverter LayoutCMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

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Layout Editor Layout Editor –– Cadence VirtuosoCadence Virtuoso

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Design Rule CheckerDesign Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks DiagramSticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important• Final layout generated by

“compaction” program

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Next LectureNext Lecture

Design Metrics