ee141- spring 2004 digital integrated circuits
TRANSCRIPT
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EE141EE141-- Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuits
Lecture 20Lecture 20PowerPowerSequential Logic Sequential Logic -- IntroIntro
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Administrative StuffAdministrative StuffMidterm 2 Th 6:30pm in 277 CoryMaterial:
– Wires– Complex logic– Arithmetic
Review session on We at 5:30pm in 241 CoryHomework 7 posted – Due April 15
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Class MaterialClass Material
Last lectureMultipliers – Shifters – Power Intro
Today’s lecturePowerIntro to sequential logic
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PowerPower
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Power Dissipation in CMOSPower Dissipation in CMOS
Dynamic powerCharging capacitancesDominant today
Leakage powerLeaky transistorsConcern in low-activity, portable devices
Short circuit powerStatic power
E.g. pseudo-NMOS
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Dynamic Power ConsumptionDynamic Power Consumption
( ) ( ) ∫∫ ∫ ====→
DDV
DDLoutLDD
T T
DDDDDD VCdvCVdttiVdttPE0
2
0 010
( ) ( ) ∫∫ ∫ ====DDV
DDLoutoutL
T T
LoutCC VCdvvCdttivdttPE0
2
0 021
Vdd
Vout
iL
CL
PMOS
NETWORK
NMOS
A1
AN
NETWORK
210 DDLVCE =→
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Dynamic Power ConsumptionDynamic Power ConsumptionPower = Energy/transition • Transition rate
= CLVDD2 • f0→1
= CLVDD2 • f • P0→1
= CswitchedVDD2 • f
Power dissipation is data dependent – depends on the switching probabilitySwitched capacitance Cswitched = CL • P0→1
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Transition Activity and PowerTransition Activity and PowerEnergy consumed in N cycles, EN:
EN = CL • VDD2 • n0→1
n0→1 – number of 0→1 transitions in N cycles
fVCN
nf
NE
P DDLN
N
Navg ⋅⋅⋅⎟⎠⎞
⎜⎝⎛=⋅= →
∞→∞→
210limlim
fN
nN
⋅= →
∞→→10
10 limα
fVCP DDLavg ⋅⋅⋅= →2
10α
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“Dynamic” or timing dependent component
➟Type of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)
➟Circuit Topology
➟Type of Logic Style (Static vs. Dynamic)
➟Signal Statistics
➟ Inter-signal Correlations
➟Signal Statistics and Correlations
Factors Affecting Transition ActivityFactors Affecting Transition Activity
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Type of Logic Function: NOR vs. XORType of Logic Function: NOR vs. XOR
011
001
010
100OutBA
Example: Static 2-input NOR Gate
Assume signal probabilitiespA=1 = 1/2pB=1 = 1/2
Then transition probabilityp0→1 = pOut=0 x pOut=1
= 3/4 x 1/4 = 3/16
α0→1 = 3/16
If inputs switch every cycle
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Type of Logic Function: NOR vs. XORType of Logic Function: NOR vs. XOR
011
101
110
000OutBA
Example: Static 2-input XOR Gate
Assume signal probabilitiespA=1 = 1/2pB=1 = 1/2
Then transition probabilityp0→1 = pOut=0 x pOut=1
= 1/2 x 1/2 = 1/4
α0→1 = 1/4
If inputs switch in every cycle
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Power Consumption of Dynamic GatesPower Consumption of Dynamic Gates
In1
In2 PDN
In3
Me
Mp
CLK
CLK
Out
CL
Power only dissipated when previous Out = 0
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Dynamic Power Consumption is Dynamic Power Consumption is Data DependentData Dependent
011
001
010
100OutBA
Dynamic 2-input NOR Gate
Assume signal probabilitiesPA=1 = 1/2PB=1 = 1/2
Then transition probabilityP0→1 = Pout=0 x Pout=1
= 3/4 x 1 = 3/4
Switching activity always higher in dynamic gates!P0→1 = Pout=0
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Vdd
I
I
Vdd
IN
INB
OUTB OUT
Guaranteed transition for every operation!
α0->1 = 1
Dynamic CVSLDynamic CVSL
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Problem: Problem: ReconvergentReconvergent FanoutFanout
A
B
X
Z
Reconvergence
P(Z = 1) = P(B = 1) . P(X = 1 | B=1)
Becomes complex and intractable fast
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InterInter--Signal CorrelationsSignal Correlations
Logic withoutreconvergent fanout
Logic with reconvergent fanout
A
BZ
CA
Z
C
B
p0→1 = (1 – pApB) pApBP(Z = 1) = p(C=1 | B=1) p(B=1)
p0→1 = 0
Need to use conditional probabilities to model inter-signal correlationsCAD tools required for such analysis
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GlitchingGlitching in Static CMOSin Static CMOSA
B
X
CZ
ABC 101 000
X
Z
Gate Delay
Also known asdynamic hazards
The result is correct,but there is extra power dissipated
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Example: Chain of NOR GatesExample: Chain of NOR Gates1
Out1 Out2 Out3 Out4 Out5
0 200 400 6000.0
1.0
2.0
3.0
Time (ps)
Vol
tage
(V
)
Out8
Out6
Out2
Out6
Out1
Out3
Out7
Out5
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Principles for Power ReductionPrinciples for Power Reduction
Prime choice: Reduce voltage!Recent years have seen an acceleration in supply voltage reductionDesign at very low voltages still open question (0.6 … 0.9 V by 2010!)Reducing thresholds to improve performance increases leakage
Reduce switching activityReduce physical capacitance
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Sequential Logic
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Sequential LogicSequential Logic
2 storage mechanisms
• positive feedback
• charge-based
COMBINATIONALLOGIC
Registers
Outputs
Next state
CLK
Q D
Current State
Inputs
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Latch versus RegisterLatch versus Register
Latchstores data when clock is low
D
Clk
Q D
Clk
Q
Registerstores data when clock rises
Clk Clk
D D
Q Q
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Naming ConventionNaming Convention
In our book, latch is level sensitive, register is edge-triggeredThere are many different naming conventionsMany books call edge-triggered elements flip-flops
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LatchesLatches
In
clk
In
Out
Positive Latch
CLK
DG
Q
Out
Outstable
Outfollows In
In
clk
In
Out
Negative Latch
CLK
DG
Q
Out
Outstable
Outfollows In
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NLatch
Logic
Logic
PLatch
φ
LatchLatch--Based DesignBased Design
• N latch is transparentwhen φ = 0
• P latch is transparent when φ = 1
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Timing DefinitionsTiming Definitions
t
CLK
t
D
tc →q
tholdtsu
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
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Characterizing TimingCharacterizing Timing
Register Latch
Clk
D Q
tC →Q
Clk
D Q
tC →Q
tD →Q
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Maximum Clock FrequencyMaximum Clock Frequency
FF
’s
LOGIC
tp,comb
φ
Also:tcdreg + tcdlogic > thold
tcd: contamination delay = minimum delay
tclk-Q + tp,comb + tsetup = T
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Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1 Vo2
Vo2 = Vi 1
Vo1 = Vi 2
V
o
1
Vi1
A
C
B
V
i
2
5
V
o
1
Vo2
V
i
2
5
V
o
1
Vi1 = Vo2
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MetaMeta--StabilityStability
Gain should be larger than 1 in the transition region
A
C
d
B
Vi2
5V
o1
Vi1 5 Vo2
A
C
d
B
Vi2
5V
o1
Vi1 5 Vo2
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Writing into a Static LatchWriting into a Static Latch
CLK
CLK
CLK
D
Q D
CLK
CLK
D
Converting into a MUXForcing the state(can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
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PseudoPseudo--Static LatchStatic Latch
D
CLK
CLK
D
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MuxMux--Based LatchesBased LatchesNegative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q 0
CLK
1D
Q
InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=
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MuxMux--Based LatchBased Latch
CLK
CLK
CLK
D
Q
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MuxMux--Based LatchBased Latch
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
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Storage MechanismsStorage Mechanisms
D
CLK
CLK
Q
Dynamic
CLK
CLK
CLK
D
Q
Static