digital integrated circuits - purdue universityvlsi/ece559_fall09/notes... · 2009. 12. 2. · ©...

EE141© Digital Integrated Circuits2nd Wires1

Digital Integrated

CircuitsA Design Perspective

The Wire

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolic


The Wire

transm itters rec eivers

schematics physical


Interconnect Impact on Chip


Wire Models

All-inclusive modelCapacitance-only


Impact of Interconnect Parasitics

Interconnect parasitics

reduce reliability

affect performance and power consumption

Classes of parasitics

Capacitive

Resistive

Inductive


10 100 1,000 10,000 100,000

Length (u)

No

of

net

s

(Lo

g S

cale

)

Pentium Pro (R)

Pentium(R) II

Pentium (MMX)

Pentium (R)

Pentium (R) II

Nature of Interconnect

Lo cal Inte rco nnect

Global Interconnect

SLocal = STechnologySGlobal = SDie

So

urc

e:

Inte

l


INTERCONNECT


Capacitance of Wire Interconnect

V DD V D D

V inV ou t

M 1

M2

M 3

M 4C db2

C db1

C gd12

C w

C g4

C g3

V ou t2

Fanout

Interconnect

V outV in

C L

S im p lified

M o d el


Capacitance: The Parallel Plate Model

Die le ctr ic

Su bstrat e

L

W

H

t d i

Ele ctrica l- fie ld lines

Cu rre nt flow

WLt

c

di

di

int

LL

CwireSSS

SS

1


Permittivity


Fringing Capacitance

W - H /2H

+

(a)

(b )


Fringing versus Parallel Plate

(from [Bakoglu89])


Interwire Capacitance

fr in ging pa rallel


Impact of Interwire Capacitance

(from [Bakoglu89])


Wiring Capacitances (0.25 mm CMOS)


INTERCONNECT


Wire Resistance

W

L

H

R =

H W

L

Shee t Re sistance

R o

R 1 R 2


Interconnect Resistance


Dealing with Resistance

Selective Technology Scaling

Use Better Interconnect Materials

reduce average wire-length

e.g. copper, silicides

More Interconnect Layers

reduce average wire-length


Polycide Gate MOSFET

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi

Conductivity: 8-10 times better than Poly


Sheet Resistance


Modern Interconnect


Example: Intel 0.25 micron Process

5 metal layers

Ti/Al - Cu/Ti/TiN

Polysilicon dielectric


INTERCONNECT


Interconnect

Modeling


The Lumped Model

Vo ut

D river

cwi re

Vin

Clumped

Rdriver

Vout


The Lumped RC-Model

The Elmore Delay


The Ellmore Delay

RC Chain


Wire Model

Assume: Wire modeled by N equal-length segments

For large values of N:


The Distributed RC-line


Step-response of RC wire as a

function of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

vo

lta

ge

(V

)

x= L/10

x = L/4

x = L/2

x= L


RC-Models


Driving an RC-line

Vin

Rs V

out

(rw,cw,L )


Design Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> tpgate/0.38rc

rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RC when not met, the change in the signal is slower

than the propagation delay of the wire

© MJIrwin, PSU, 2000

digital integrated circuits - purdue universityvlsi/ece559_fall09/notes... · 2009. 12. 2. · ©...

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