ee141 © digital integrated circuits 2nd arithmetic circuits 1 low power design in cmos [adapted...

EE1411

© Digital Integrated Circuits2ndArithmetic Circuits

Low Power DesignLow Power Design in CMOS in CMOS

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE1412


Why Power MattersWhy Power Matters

Packaging costs Power supply rail design Chip and system cooling costs Noise immunity and system reliability Battery life (in portable systems) Environmental concerns

Office equipment accounted for 5% of total US commercial energy usage in 1993

Energy Star compliant systems

EE1413


Why worry about power? -- Why worry about power? -- ChipChip Power DensityPower Density

40048008

80808085

8086

286386

486Pentium®

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Sun’sSurface

…chips might become hot…

Source: Borkar, De Intel

EE1414


Why worry about power?Why worry about power?-- -- Heat DissipationHeat Dissipation

DEC 21164

source : arpa-esto

microprocessor power dissipation

EE1415


Why worry about power ? -- Why worry about power ? -- Battery Size/WeightBattery Size/Weight

Expected battery lifetime increase over the next 5 years: 30 to 40%

From Rabaey, 1995From Rabaey, 1995

65 70 75 80 85 90 95

0

10

20

30

40

50

Rechargable Lithium

Year

Nickel-Cadmium

Ni-Metal Hydride

Nom

inal

Cap

acity

(W

-hr/

lb)

Battery(40+ lbs)

EE1416


Why worry about power? -- Why worry about power? -- Standby PowerStandby Power

Drain leakage will increase as VT decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption.

8KW

1.7KW

400W

88W 12W

0%

10%

20%

30%

40%

50%

2000 2002 2004 2006 2008

Sta

nd

by

Po

wer

Source: Borkar, De Intel

Year 2002 2005 2008 2011 2014

Power supply Vdd (V) 1.5 1.2 0.9 0.7 0.6

Threshold VT (V) 0.4 0.4 0.35 0.3 0.25

…and phones leaky!

EE1417


Problem IllustrationProblem Illustration

EE1418


Power and Energy Figures of MeritPower and Energy Figures of Merit Power consumption in Watts

determines battery life in hours Peak power

determines power ground wiring designs sets packaging limits impacts signal noise margin and reliability analysis

Energy efficiency in Joules rate at which power is consumed over time

Energy = power * delay Joules = Watts * seconds lower energy number means less power to perform a

computation at the same frequency

EE1419


Power versus EnergyPower versus Energy

Watts

time

Power is height of curve

Watts

time

Approach 1

Approach 2

Approach 2

Approach 1

Energy is area under curve

Lower power design could simply be slower

Two approaches require the same energy

EE14110


PDP and EDPPDP and EDP Power-delay product (PDP) = Pav * tp = (CLVDD

2)/2 PDP is the average energy consumed per switching event

(Watts * sec = Joule) lower power design could simply be a slower design

allows one to understand tradeoffs better

0

5

10

15

0.5 1 1.5 2 2.5

Vdd (V)

Energ

y-Dela

y (no

rmali

zed)

energy-delay

energy

delay

Energy-delay product (EDP) = PDP * tp = Pav * tp2

EDP is the average energy consumed multiplied by the computation time required

takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption)

EE14112


Understanding TradeoffsUnderstanding Tradeoffs

Ene

rgy

1/Delay

a

b

c

d

Lower EDP

Which design is the “best” (fastest, coolest, both) ?

bett

er

better

EE14113


CMOS Energy & Power EquationsCMOS Energy & Power Equations

E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD Ileakage

P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage

Dynamic power

Short-circuit power

Leakage power

f01 = P01 * fclock

EE14114


Dynamic Power ConsumptionDynamic Power Consumption

Energy/transition = CL * VDD2 * P01

Pdyn = Energy/transition * f = CL * VDD2 * P01 * f

Pdyn = CEFF * VDD2 * f where CEFF = P01 CL

Not a function of transistor sizes!Data dependent - a function of switching activity!

Vin Vout

CL

Vdd

f01

EE14116


Lowering Dynamic PowerLowering Dynamic Power

Pdyn = CL VDD2 P01 f

Capacitance:Function of fan-out, wire length, transistor sizes

Supply Voltage:Has been dropping with successive generations

Clock frequency:Increasing…

Activity factor:How often, on average, do wires switch?

EE14117


Short Circuit Power ConsumptionShort Circuit Power Consumption

Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.

Vin Vout

CL

Isc

EE14118


Short Circuit Currents DeterminatesShort Circuit Currents Determinates

Duration and slope of the input signal, tsc

Ipeak determined by the saturation current of the P and N transistors which

depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes

– a function of CL

Esc = tsc VDD Ipeak P01

Psc = tsc VDD Ipeak f01

EE14119


Impact of CImpact of CLL on P on Pscsc

Vin Vout

CL

Isc 0

Vin Vout

CL

Isc Imax

Large capacitive load

Output fall time significantly larger than input rise time.

Small capacitive load

Output fall time substantially smaller than the input rise

time.

EE14120


IIpeakpeak as a Function of C as a Function of CLL

-0.5

0

0.5

1

1.5

2

2.5

0 2 4 6

I pea

k (A

)

time (sec)

x 10-10

x 10-4

CL = 20 fF

CL = 100 fF

CL = 500 fF

500 psec input slope

Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.

When load capacitance is small, Ipeak is large.

EE14121


PPscsc as a Function of Rise/Fall Times as a Function of Rise/Fall Times

0

1

2

3

4

5

6

7

8

0 2 4

P n

orm

aliz

ed

tsin/tsout

VDD= 3.3 V

VDD = 2.5 V

VDD = 1.5V

normalized wrt zero input rise-time dissipation

When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc

If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time.

W/Lp = 1.125 m/0.25 mW/Ln = 0.375 m/0.25 mCL = 30 fF

EE14122


Leakage (Static) Power ConsumptionLeakage (Static) Power Consumption

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

VDD Ileakage

Vout

Drain junction leakage

Sub-threshold currentGate leakage

EE14123


Leakage as a Function of VLeakage as a Function of VTT

0 0.2 0.4 0.6 0.8 1

VGS (V)

ID (A

)

VT=0.4V

VT=0.1V

10-2

10-12

10-7

Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation.

An 90mV/decade VT roll-off - so each 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance)

EE14124


TSMC Processes Leakage and VTSMC Processes Leakage and VTT

80

0.25 V

13,000

920/400

0.08 m

24 Å

1.2 V

CL013 HS

52

0.29 V

1,800

860/370

0.11 m

29 Å

1.5 V

CL015 HS

42 Å42 Å42 Å42 ÅTox (effective)

43142230FET Perf. (GHz)

0.40 V0.73 V0.63 V0.42 VVTn

3000.151.6020Ioff (leakage) (A/m)

780/360320/130500/180600/260IDSat (n/p) (A/m)

0.13 m 0.18 m 0.16 m 0.16 m Lgate

2 V1.8 V1.8 V1.8 VVdd

CL018 HS

CL018 ULP

CL018 LP

CL018 G

From MPR, 2000

EE14125


Exponential Increase in Leakage CurrentsExponential Increase in Leakage Currents

1

10

100

1000

10000

30 40 50 60 70 80 90 100 110

0.25

0.18

0.13

0.1

Temp(C)

I leak

age(n

A/

m)

From De,1999

EE14126


Review: Energy & Power EquationsReview: Energy & Power Equations

E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD

Ileakage

P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage

Dynamic power(~90% today and

decreasing relatively)

Short-circuit power(~8% today and

decreasing absolutely)

Leakage power(~2% today and

increasing)

f01 = P01 * fclock

EE14127


Power and Energy Design SpacePower and Energy Design Space

Constant Throughput/Latency

Variable Throughput/Latency

Energy Design TimeNon-active Modules

Run Time

Active

Logic Design

Reduced Vdd

Sizing

Multi-Vdd

Clock Gating

DFS, DVS

(Dynamic Freq,

Voltage Scaling)

Leakage + Multi-VT

Sleep Transistors

Multi-Vdd

Variable VT

+ Variable VT

EE14128


Dynamic Power as a Function of Device SizeDynamic Power as a Function of Device Size Device sizing affects dynamic energy consumption

gain is largest for networks with large overall effective fan-outs (F = CL/Cg,1)

The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F’s e.g., for F=20,

fopt(energy) = 3.53 while fopt(performance) = 4.47

If energy is a concern avoid oversizing beyond the optimal

1 2 3 4 5 6 70

0.5

1

1.5

f

norm

aliz

ed e

nerg

y

F=1

F=2

F=5

F=10

F=20

From Nikolic, UCB

EE14129


Dynamic Power Consumption is Data DependentDynamic Power Consumption is Data Dependent

A B Out

0 0 1

0 1 0

1 0 0

1 1 0

2-input NOR Gate

With input signal probabilities PA=1 = 1/2 PB=1 = 1/2

Static transition probability P01 = Pout=0 x Pout=1

= P0 x (1-P0)

Switching activity, P01, has two components

A static component – function of the logic topology A dynamic component – function of the timing behavior

(glitching)

NOR static transition probability = 3/4 x 1/4 = 3/16

EE14130


NOR Gate Transition ProbabilitiesNOR Gate Transition Probabilities

CL

A

B

BA

P01 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)

PA

PB

0

1 0 1

Switching activity is a strong function of the input signal statistics PA and PB are the probabilities that inputs A and B are one

EE14132


Transition Probabilities for Some Basic GatesTransition Probabilities for Some Basic Gates

P01 = Pout=0 x Pout=1

NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)

OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))

NAND PAPB x (1 - PAPB)

AND (1 - PAPB) x PAPB

XOR (1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)

B

AZ

X0.5

0.5

For Z: P01 = P0 x P1 = (1-PXPB) PXPB

For X: P01 = P0 x P1 = (1-PA) PA

= 0.5 x 0.5 = 0.25

= (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16

EE14134


Inter-signal CorrelationsInter-signal Correlations

B

A

Z

X

P(Z=1) = P(B=1) & P(A=1 | B=1)

0.5

0.5

(1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16

(1- 3/16 x 0.5) x (3/16 x 0.5) = 0.085Reconvergent

Determining switching activity is complicated by the fact that signals exhibit correlation in space and time reconvergent fan-out

Have to use conditional probabilities

EE14135


Logic RestructuringLogic Restructuring

Chain implementation has a lower overall switching activity than the tree implementation for random inputs

Ignores glitching effects

Logic restructuring: changing the topology of a logic network to reduce transitions

A

BC

D F

AB

CD Z

FW

X

Y0.5

0.5

(1-0.25)*0.25 = 3/16

0.50.5

0.5

0.5

0.5

0.5

7/64

15/256

3/16

3/16

15/256

AND: P01 = P0 x P1 = (1 - PAPB) x PAPB

EE14137


Input OrderingInput Ordering

Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5)

A

BC

X

F

0.5

0.20.1

B

CA

X

F

0.2

0.10.5

(1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196

EE14139


Glitching in Static CMOS NetworksGlitching in Static CMOS Networks

ABC

X

Z

101 000

Unit Delay

AB

X

ZC

Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards) glitch: node exhibits multiple transitions in a single

cycle before settling to the correct logic value

EE14140


Glitching in an RCAGlitching in an RCA

S0S1S2S14S15

Cin

0

1

2

3

0 2 4 6 8 10 12

Time (ps)

S O

utp

ut

Vo

ltag

e (

V)

Cin

S0

S1

S2

S3

S4

S5S10

S15

EE14141


How to Cope with Glitching?How to Cope with Glitching?

F1

F2

F3

F1

F3

F2

0

0

0

0

1

2

0

0

0

01

1

Equalize Lengths of Timing Paths Through Design

EE14142


Power Analysis in SPICEPower Analysis in SPICE

RC

k iDDCircuitUnder Test

+

-

VDD

iDD

Pav

Equivalent Circuit for Measuring Power in SPICE

EE14143


Reducing Reducing VVdddd

P x td = Et = CL * Vdd2

E(Vdd=2)=

(CL) * (2)2

(CL) * (5)2E(Vdd=5)

Strong function of voltage (V2 dependence).

Relatively independent of logic function and style.

E(Vdd=2) 0.16 E(Vdd =5)

0.03

0.05

0.07

0.1

0.15

0.20

0.30

0.50

0.70

1.00

1.5

1 2 5

51 stage ring oscillator

8-bit adder

Vdd (volts)

quadratic dependence

NO

RM

AL

IZE

D P

OW

ER

-DE

LA

Y P

RO

DU

CT

Power Delay Product Improves with lowering VDD.

EE14144


Lower VLower Vdddd Increases DelayIncreases Delay

CL * Vdd

I=Td

Td(Vdd=5)

Td(Vdd=2)=

(2) * (5 - 0.7)2

(5) * (2 - 0.7)2

4

I ~ (Vdd - Vt)2

Relatively independent of logic function and style.

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

5.50

6.00

6.50

7.00

7.50

2.00 4.00 6.00Vdd (volts)

NO

RM

AL

IZE

D D

EL

AY

adder (SPICE)

microcoded DSP chip

multiplier

adder

ring oscillator

clock generator2.0m technology

EE14145


Lowering the ThresholdLowering the Threshold

DESIGN FOR PLeakage == PDynamic

Vt = 0.2Vt = 0

ID

VGS

Reduces the Speed Loss, But Increases Leakage

Vdd

Delay

2Vt

Interesting Design Approach:

Reduced threshold

EE14146


Transistor Sizing for Power MinimizationTransistor Sizing for Power Minimization

Minimum sized devices are usually optimal for low-power.

Small W/L’s

Large W/L’s

Higher Voltage

Lower Voltage

Lower Capacitance

Higher Capacitance

Larger sized devices are useful only when interconnect dominated.

EE14147


Balanced Delay Paths to Reduce GlitchingBalanced Delay Paths to Reduce Glitching

So equalize the lengths of timing paths through logic

F1

F2

F3

0

0

0

0

1

2

F1

F2

F3

0

0

0

0

1

1

Glitching is due to a mismatch in the path lengths in the logic network; if all input signals of a gate change simultaneously, no glitching occurs

EE14148





Energy Design TimeNon-active Modules

Run Time

Active

Logic Design

Reduced Vdd

Sizing

Multi-Vdd

Clock Gating

DFS, DVS

(Dynamic Freq,

Voltage Scaling)

Leakage + Multi-VT

Sleep Transistors

Multi-Vdd

Variable VT

+ Variable VT

EE14149


Dynamic Power as a Function of VDynamic Power as a Function of VDDDD

Decreasing the VDD

decreases dynamic energy consumption (quadratically)

But, increases gate delay (decreases performance)

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

VDD (V) t p

( no

r ma

l ize

d)

Determine the critical path(s) at design time and use high VDD for the transistors on those paths for speed. Use a lower VDD on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits).

EE14150


Multiple VMultiple VDDDD Considerations Considerations

How many VDD? – Two is becoming common Many chips already have two supplies (one for core and one for

I/O) When combining multiple supplies, level converters are required

whenever a module at the lower supply drives a gate at the higher supply (step-up) If a gate supplied with VDDL drives a gate at VDDH, the PMOS never

turns off– The cross-coupled PMOS transistors

do the level conversion– The NMOS transistor operate on a

reduced supply Level converters are not needed

for a step-down change in voltage Overhead of level converters can be mitigated by doing

conversions at register boundaries and embedding the level conversion inside the flipflop (see Figure 11.47)

VDDH

Vin

VoutVDDL

EE14151


Dual-Supply Inside a Logic BlockDual-Supply Inside a Logic Block Minimum energy consumption is achieved if all logic paths are

critical (have the same delay) Clustered voltage-scaling

Each path starts with VDDH and switches to VDDL (gray logic gates) when delay slack is available

Level conversion is done in the flipflops at the end of the paths

EE14152





Energy Design Time Non-active Modules Run Time

Active

Logic Design

Reduced Vdd

Sizing

Multi-Vdd

Clock Gating

DFS, DVS

(Dynamic Freq, Voltage

Scaling)

Leakage + Multi-VT

Sleep Transistors

Multi-Vdd

Variable VT

+ Variable VT

EE14153


Stack EffectStack Effect Leakage is a function of the circuit topology and the value of the

inputs

VT = VT0 + (|-2F + VSB| - |-2F|)where VT0 is the threshold voltage at VSB = 0; VSB is the source- bulk

(substrate) voltage; is the body-effect coefficient

A B

B

A

Out

VX

A B VX ISUB

0 0 VT ln(1+n) VGS=VBS= -VX

0 1 0 VGS=VBS=0

1 0 VDD-VT VGS=VBS=0

1 1 0 VSG=VSB=0 Leakage is least when A = B = 0 Leakage reduction due to stacked

transistors is called the stack effect

EE14154


Short Channel Factors and Stack EffectShort Channel Factors and Stack Effect

In short-channel devices, the subthreshold leakage current depends on VGS,VBS and VDS. The VT of a short-channel device decreases with increasing VDS due to DIBL (drain-induced barrier loading). Typical values for DIBL are 20 to 150mV change in VT per voltage

change in VDS so the stack effect is even more significant for short-channel devices.

VX reduces the drain-source voltage of the top nfet, increasing its VT and lowering its leakage

For our 0.25 micron technology, VX settles to ~100mV in steady state so VBS = -100mV and VDS = VDD -100mV which is 20 times smaller than the leakage of a device with VBS = 0mV and VDS = VDD

EE14155


Leakage as a Function of Design Time VLeakage as a Function of Design Time VTT

Reducing the VT increases the sub-threshold leakage current (exponentially) 90mV reduction in VT

increases leakage by an order of magnitude

But, reducing VT decreases gate delay (increases performance)

0 0.2 0.4 0.6 0.8 1

VGS (V)ID

(A)

VT=0.4V

VT=0.1V

Determine the critical path(s) at design time and use low VT devices on the transistors on those paths for speed. Use a high VT on the other logic for leakage control. A careful assignment of VT’s can reduce the leakage by as much

as 80%

EE14156


Dual-Thresholds Inside a Logic BlockDual-Thresholds Inside a Logic Block

Minimum energy consumption is achieved if all logic paths are critical (have the same delay)

Use lower threshold on timing-critical paths Assignment can be done on a per gate or transistor basis;

no clustering of the logic is needed No level converters are needed

EE14157


Variable VVariable VTT (ABB) at Run Time (ABB) at Run Time

VT = VT0 + (|-2F + VSB| - |-2F|)

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

-2.5 -2 -1.5 -1 -0.5 0

VSB (V)

VT (

V)

A negative bias on VSB causes VT to increase

Adjusting the substrate bias at run time is called adaptive body-biasing (ABB)

Requires a dual well fab process

For an n-channel device, the substrate is normally tied to ground (VSB = 0)

EE14158


SummarySummary

• Power Dissipation is becoming Prime DesignConstraint

• Low Power Design requires Optimization at all Levels

• Sources of Power Dissipation are well characterized

• Low Power Design requires operation at lowest

possible voltage and clock speed

ee141 © digital integrated circuits 2nd arithmetic circuits 1 low power design in cmos [adapted...

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