EE415 VLSI Design

The Devices: Diode

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design

Goal of this chapter

•Present intuitive understanding of device operation

•Introduction of basic device equations

•Introduction of models for manual analysis

•Introduction of models for SPICE simulation

•Analysis of secondary deep-sub-micron effects

•Future trends

EE415 VLSI Design

Outline Motivation and Goals Semiconductor Basics Diode Structure Operation

» Static model– Depletion capacitance– Carrier density profiles

Diffusion capacitance

» Dynamic response – Switching speed next session

Spice model

EE415 VLSI Design

Semiconductor Basics I

Electrons in intrinsic (pure) Silicon

» covalently bonded to atoms

» “juggled” between neighbors

» thermally activated: density eT

» move around the lattice, if free

» leave a positively charged `hole’ behind

http://www.masstech.org/cleanenergy/solar_info/images/crystal.gif

EE415 VLSI Design

Semiconductor Basics II Two types of intrinsic carriers

» Electrons (ni) and holes (pi)

» In an intrinsic (no doping) material, ni=pi

» At 300K, ni=pi is low (1010cm-3)

» Use doping to improve conductivity

EE415 VLSI Design

Semiconductor Basics III Extrinsic carriers

» Also two types of dopants (donors or acceptors)– Donors bring electron (n-type) and become ive ions

– Acceptors bring holes (p-type) and become ive ions

» Substantially higher densities (1015cm-3)» Majority and minority carriers

– if n>>p (n-type) electrons majority and holes minority

– Random recombination and thermal generation

EE415 VLSI Design

The Diode

p

n

B ASiO 2

Al

Cross section of pn-junction in an IC process

P-type region

doped with acceptor impurities (boron)

N-type region

doped with donor impurities (phosphorus, arsenic)

EE415 VLSI Design

The Diode

A

B

n

p

A

B

Al

One-dimensionalrepresentation diode symbol

The pn region is assumed to be thin (step or abrupt junction)

Different concentrations of electrons (and holes) of the p and n-type regions cause a concentration gradient at the boundary

Simplified structure

EE415 VLSI Design

•Concentration Gradient causes electrons to diffuse from n to p, and holes to diffuse from p to n

•This produces immobile ions in the vicinity of the boundary

•Region at the junction with the charged ions is called the depletion region or space-charge region

•Charges create electric field that attracts the minority carriers, causing them to drift

•Drift counteracts diffusion causing equilibrium ( Idrift = -Idiffusion )

Depletion Region

hole diffusionelectron diffusion

p n

hole driftelectron drift

EE415 VLSI Design

Depletion Regionhole diffusion

electron diffusion

p n

hole driftelectron drift

ChargeDensity

Distancex+

-

ElectricalxField

x

PotentialV

W2-W1

(a) Current flow.

(b) Charge density.

(c) Electric field.

(d) Electrostaticpotential.

•Zero bias conditions

•p more heavily doped than n (NA > NB)

•Electric field gives rise to potential difference in the junction, known as the built-in potential

EE415 VLSI Design

Built-in Potential

Where T is the thermal voltage

0 2

T

A D

i

N N

nln

)300(26 KatmVq

kTT

ni is the intrinsic carrier concentration for

pure Si (1.5 X 1010 cm-3 at 300K), so for

mVmV 63810*5.1

1010ln26 210

1615

0

,1

10,1

103

163

15

cmN

cmN BA

EE415 VLSI Design

Forward Biashole diffusion

electron diffusion

p n

hole driftelectron drift

+ -

•Applied potential lowers the potential barrier, Idiffusion > I drift

•Mobile carriers drift through the dep. region into neutral regions

•become excess minority carriers and diffuse towards terminals

•Read about drift and diffusion currents at:

•http://ece-www.colorado.edu/~bart/book/book/chapter2/ch2_10.htm

EE415 VLSI Design

Forward Bias

pn0

np0

-W1 W20p n

(W2)

n-regionp-region

Lp

diffusion

Typically avoided in Digital ICs

xWn

Meta

l co

nta

ct t

o n

-regio

n

-Wp

Meta

l co

nta

ct t

o p

-regio

np (x)n

n (x)p

minority carrier concentration

EE415 VLSI Design

Reverse Bias

hole diffusionelectron diffusion

p n

hole driftelectron drift

- +

•Applied potential increases the potential barrier

•Diffusion current is reduced

•Diode works in the reverse bias with a very small drift current

EE415 VLSI Design

Reverse Bias

x

np0

-W1 W20

n-regionp-region

pn0

diffusion

The Dominant Operation Mode

-Wp

Meta

l co

nta

ct t

o p

-regio

n

Wn

Meta

l co

nta

ct t

o n

-regio

n

np0

EE415 VLSI Design

Models for Manual Analysis

VD

ID = IS(eVD/T – 1)+

–

VD

+

–

+

–VDon

ID

(a) Ideal diode model (b) First-order diode model

•Accurate

•Strongly non-linear

•Prevents fast DC bias calculations

•Conducting diode replaced by voltage source VDon=0.7V

•Good for first order approximation

EE415 VLSI Design

Typical Diode Parameters

VD ID = IS(eVD/T – 1)

+

–

•Dn=25 cm2/sec

•Dp=10cm2/sec

•Wn=5 m

•Wp=0.7 m

•W2=0.15 m

•W1=0.03 m

Geometry, doping and material constants lumped in Is

217 /10

)(1

0

2

0

mAI

valuetypical

qAI

S

WW

nD

WW

pD

DS p

pn

n

np

Diffusion coefficientminority carrier concentration

EE415 VLSI Design

Diode Current

Ideal diode equation:

VVDon 7.0

VVDon 7.0

EE415 VLSI Design

Depletion Capacitance

Due to depletion charges » VD changes space charge » Forms a capacitor Cj

– Charge modulated by voltage

Ideality factor (m) depends on junction gradient

EE415 VLSI Design

Equivalent Capacitances I

Linearize diode capacitances » Cj is a non-linear function of VD

– When bias changes then Cj also changes

– Hard to use in manual analyses

» Instead use equivalent capacitance – Gives the same total charge for a given VD transition

» Equivalent depletion capacitance– Must be worked out for a given V1V2 transition

)1)((

)()(

)()(

12

110

1200

012

12

mVVVV

K

CKVV

VQVQ

V

QC

mmm

eq

jeqjj

D

jeq

EE415 VLSI Design

Equivalent Capacitances II

» Equivalent diffusion capacitance– Must be worked out for currents at given V1V2 transition

Ceq depends on process constants and {V1,V2} » Example:

– for AD=0.5 m2 Cj0=2 fF/m2, 0=0.64 V and m=0.5 then Keq0.622 and Ceq1.24 fF/m2 if switched between 0 and -2.5 V

So unit capacitance Cj 0.9 fF/m2 or Cj 0.45 fF for the total diode area

12

12

12

12 )()()()(VV

VCVCVV

VIVIV

QC dd

TDD

TD

jeq

EE415 VLSI Design

Secondary Effects: Breakdown

–25.0 –15.0 –5.0 5.0

VD (V)

–0.1

I D (A

)

0.1

0

0

Cannot bear too large reverse biases» Drift field in depletion region will get extremely large» Minority carriers caught in this large field will get very energetic

– Energetic carriers can knock atoms and create a new n-p pair– These carriers will get energetic, too, and so on: thus large currents!

Two types» Avalanche

breakdown– Above mechanism

» Zener breakdown– More complicated

Can damage diode

EE415 VLSI Design

Diode SPICE Model

ID

RS

CD

+

-

VD

Required for circuit simulations» Must capture important characteristics but also remain efficient » Extra parameter in the model: n (emission coefficient, 1 n 2)

– Fixes non-ideal behavior due to broken assumptions

Additional series resistance accounts for body+contact Nonlinear capacitance includes both CD and Cj

ID IS (eVD /nT 1)

EE415 VLSI Design

SPICE Parameters Often supplied by the fab to the designer

» If not must be measured and fit the parameters Assumes default values, if not explicitly defined Pay attention to the units and spelling