ee415 vlsi design. read 4.1, 4.2 combinational logic
DESCRIPTION
EE415 VLSI Design Example Gate: COMPLEX CMOS GATETRANSCRIPT
EE415 VLSI Design
EE415 VLSI Design
Read 4.1, 4.2
COMBINATIONAL LOGIC
EE415 VLSI Design
Example Gate: COMPLEX CMOS GATE
VDD
AB
C
D
DA
B C
OUT = D + A• (B+C)
EE415 VLSI Design
Propagation Delay Analysis - The Switch Model
VDDVDDVDD
CL
F CL
CL
F
F
RpRp Rp Rp
Rp
Rn
Rn
Rn Rn Rn
AA
A
AA
A
B B
B
B
(a) Inverter (b) 2-input NAND (c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
= RON
EE415 VLSI Design
Analysis of Propagation DelayVDD
CL
F
Rp Rp
Rn
Rn
A
A B
B
2-input NAND
1. Assume Rn=Rp= resistance of minimum sized NMOS inverter
2. Determine “Worst Case Input” transition(Delay depends on input values)
3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pulls
up the output node- For 2 PMOS devices in parallel, the
resistance is lower
4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in series
tpLH = 0.69RpCL
tpHL = 0.69(2Rn)CL
EE415 VLSI Design
What is the Value of Ron?
Computing Ron for tPHL , for an inverter
2/21
DDoutNMOSDDoutNMOSon VVRVVRR
2/21
DDoutDDout VVD
DS
VVD
DSon I
VI
VR
EE415 VLSI Design
Numerical Examples of Resistances for 1.2m CMOS
See Example 4.2, table 3.3
EE415 VLSI Design
Transistor Sizing
VDD
AB
C
D
DA
B C
12
22
6
612
12
F
• for symmetrical response (dc, ac)• for performance
Focus on worst-case
Input Dependent
Numbers indicate transistor sizingwith minimum sizeequal to 1
EE415 VLSI Design
Design for Worst CaseVVDD
CL
F
A
A B
B
2
2
1 1
DD
AB
C
D
DA
B C
12
22
2
24
4
F
Here it is assumed that Rp = Rn
Additional geometry changeswhich compensate for the worstcase path
EE415 VLSI Design
Problems with Complementary CMOS
•Gate with N inputs requires 2N transistors•other circuit styles use N+1 transistors
•tp deteriorates with high fan-in•increases total capacitance•series connected transistors slows down gate
•fan-out loads down gate•1 fan-out = 2 gate capacitors (PMOS and NMOS)
FOaFIaFIat p 32
21
EE415 VLSI Design
Influence of Fan-In and Fan-Out on Delay
VDD
A B
A
B
C
D
C D
tp a1FI a2FI2 a3FO+ +=
Fan-Out: Number of Gates Connected2 Gate Capacitances per Fan-Out
FanIn: Quadratic Term due to:
1. Resistance Increasing2. Capacitance Increasing(tpHL )
EE415 VLSI Design
tp as a Function of Fan-In
1 3 5 7 9fan-in
0.0
1.0
2.0
3.0
4.0
t p (nsec)
tpHL
tp
tpLHlinear
quadratic
AVOID LARGE FAN-IN GATES! (Typically than FI < 4)
Gate: NANDfan-out = 1
EE415 VLSI Design
As long as Fan-out Capacitance dominates• Progressive Sizing:
CL
In1
InN
In3
In 2
Out
C1
C2
C3
M1 > M2 > M3 > MN
M1
M2
M3
MN
Distributed RC-line
Can Reduce Delay by more than 30%!
Example 4.3:no sizing: tpHL = 1.1 nsecwith sizing: tpHL = 0.81 nsec
Fast Complex Gate - Design Techniques
EE415 VLSI Design
Fast Complex Gate - Design Techniques
•Transistor Ordering
In1
In3
In2
C1
C2
CL
M1
M2
M3
In3
In1
In2
C3
C2
CL
M3
M2
M1
(a) (b)
critical pathcritical path
EE415 VLSI Design
Fast Complex Gate - Design Techniques
•Improved Logic Design
EE415 VLSI Design
Fast Complex Gate - Design Techniques
•Buffering:• Isolate Fan-in from Fan-out
CLCL
Read Example 4.5
EE415 VLSI Design
Example: Full Adder
VDD
VDD
VDD
VDD
A B
Ci
S
Co
X
B
A
Ci A
BBA
Ci
A B Ci
Ci
B
A
Ci
A
B
BA
Co = AB + Ci(A+B)
28 transistors
EE415 VLSI Design
A Revised Adder Circuit
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
EE415 VLSI Design
Ratioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
EE415 VLSI Design
Ratioed LogicVDD
VSS
PDNIn1
In2
In3
F
RLLoadResistive
N transistors + Load
• VOH = VDD
• VOL = RDN
RDN + RL
• Asymmetrical response
• Static power consumption
•
• tpLH= 0.69 RL CL
VDD
LPDNLpHL CRRt ||69.0
EE415 VLSI Design
Active LoadsVDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
DepletionLoad
PMOSLoad
depletion load NMOS pseudo-NMOS
VT < 0
EE415 VLSI Design
Load Lines of Ratioed Gates
0.0 1.0 2.0 3.0 4.0 5.0Vout (V)
0
0.25
0.5
0.75
1
I L(Normalized)
Resistive load
Pseudo-NMOS
Depletion load
Current source
EE415 VLSI Design
Pseudo-NMOS
VDD
A B C D
FCL
VOH = VDD (similar to complementary CMOS)
kn VDD VTn– VOLVOL
2
2-------------–
kp
2------ VDD VTp– 2=
VOL VDD VT– 1 1kpkn------–– (assuming that VT VTn VTp )= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
EE415 VLSI Design
Pseudo-NMOS NAND Gate
VDD
GND
Out