EE415 VLSI Design

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EE415 VLSI Design

The Devices: MOS Transistor

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design

The MOS Transistor

Polysilicon Aluminum

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MOS Transistor Cross Section

MOS transistor

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The MOS Transistor

n+n+

p-substrate

Field-Oxyde

(SiO2)

p+ stopper

Polysilicon

Gate Oxyde

DrainSource

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor

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Switch Model of NMOS Transistor

Gate

Source(of carriers)

Drain(of

carriers)

| VGS |

| VGS | < | VT | | VGS | > | VT |

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)

Ron

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Switch Model of PMOS Transistor

Gate

Source(of carriers)

Drain(of carriers)

| VGS |

| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |

Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)Ron

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MOS transistors Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact

Channel

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MOSFET Static Behavior

Depletion Region

VGS

=0

Mobile electrons

With drain and source grounded, and VGS = 0, both back-to-back (sub-source, sub-drain) junctions have 0V bias and are OFF

EE415 VLSI Design

MOSFET Static Behavior

Positive voltage applied to the gate (VGS > 0)

•The gate and substrate form the plates of a capacitor.

•Negative charges accumulate on the substrate side (repels mobile holes)

•A depletion region is formed under the gate (like pn junction diode)

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

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Inversion

As the VGS increases, the surface under the gate undergoes inversion to n-type material. This is the beginning of a phenomenon called strong inversion.

Further increases in VGS do not change the width of the depletion layer, but result in more electrons in the thin inversion layer, producing a continuous channel from source to drain

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The Threshold Voltage

The value of VGS where strong inversion occurs is called the Threshold Voltage, VT , and has several components:

•The flat-band voltage, VFB , is the built-in voltage offset across the MOS structure and depends on fixed charge and implanted impurities charge on the oxide-silicon interface

•VB represents the voltage drop across the depletion layer at inversion and equals to minus twice the Fermi potential ~(0.6V)

•Vox represents the potential drop

across the gate oxide

oxBFBT VVVV

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The Threshold Voltage

Where:

F is the Fermi potential ( ~ -0.3V for p-type substrates

Cox is the gate oxide capacitance

VSB is the substrate bias voltage

VT0 is VT at VSB = 0

Note:

VT is positive for NMOS transistors and negative for PMOS

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Body-Bias The body-bias factor

and the adjusted threshold voltage

Typical values: the body bias n0.4 [V1/2], Fermi potential F -0.3 [V],

gate oxide xox 0.01 [µm].

n

1C

ox

2 q Si

Na

[V 1/2]

VTn

VT0n

n( 2

F V

SB 2

F)

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The Body Effect

-2.5 -2 -1.5 -1 -0.5 00.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VBS

(V)

VT (

V)

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Current-Voltage Relations

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions

Assume VGS > VT

•A voltage difference VDS will cause ID to flow from drain to source

•At a point x along the channel, the voltage is V(x), and the gate-to-channel voltage is VGS - V(x)

•For channel to be present from drain to source, VGS - V(x) > VT, i.e. VGS - VDS > VT for channel to exist from drain to source

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Linear (triode) Region

•When VGS - VDS > VT , the channel exists from drain to source•Transistor behaves like voltage controlled resistor

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Saturation Region

•When VGS - VDS VT , the channel is pinched off•Electrons are injected into depletion region and accelerated towards drain by electric field•Transistor behaves like voltage-controlled current source

Pinch-off

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Current-Voltage RelationsLong-Channel Device

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Current-Voltage RelationsLong Channel transistor

NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

VDS = VGS - VT

cut-off

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A model for manual analysis

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Dynamic Behavior of MOS Transistor

•MOSFET is a majority carrier device (unlike pn junction diode)•Delays depend on the time to (dis)charge the capacitances between MOS terminals•Capacitances originate from three sources:

•basic MOS structure (layout)•charge present in the channel•depletion regions of the reverse-biased pn-junctions of drain and source

•Capacitances are non-linear and vary with the applied voltage

DS

G

B

CGDCGS

CSB CDBCGB

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MOS Structure Capacitances

Gate Capacitance

•Gate isolated from channel by gate oxide

oxoxox tC /•tox small as possible

•Results in gate capacitance Cg

WLCC oxg

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Gate Capacitance

n+n+

p-substrate

Field-Oxide

(SiO 2)

p+ stopper

Polysilicon

Gate Oxide

DrainSource

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor

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The Gate Capacitance

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The Gate Capacitance

Gate Capacitance depends on•channel charge (non-linear)•topology

Capacitance due to topology•Source and drain extend below the gate oxide by xd (lateral diffusion)•Effective length of the channel Leff is shorter than the drawn length by factor of 2xd

•Cause of parasitic overlap capacitance, CgsO, between gate and source (drain)

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The Gate Capacitance

Overlap Capacitance

Channel Capacitance

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The Channel Capacitance

Channel Capacitance has three components•capacitance between gate and source, Cgs

•capacitance between gate and drain, Cgd

•capacitance between gate and bulk region, Cgb

Channel Capacitance values•non-linear, depends on operating region•averaged to simplify analysis

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The Channel Capacitance

Most important regions in digital design: saturation and cut-off

Different distributions of gate capacitance for varying

operating conditions

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Diffusion Capacitance

Bottom Plate CapacitanceJunction Depth

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Capacitive Device Model

DS

G

B

CGDCGS

CSB CDBCGB

CGS = Cgs+ CgsO

CGD = Cgd+ CgdO

CGB = Cgb

CSB = CSdiff

CDB = CDdiff

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The Sub-Micron MOS Transistor

•Actual transistor deviates substantially from

model

•Channel length becomes comparable to other

device parameters. Ex: depth of drain and source

junctions

•Referred to as a short-channel device

•Influenced heavily by secondary effects

•Latchup problems

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The Sub-Micron MOS Transistor

Secondary Effects:

•Threshold Variations

•Parasitic Resistances

•Velocity Saturation and Mobility

Degradation

•Sub-threshold Conduction

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Threshold VariationsPart of the region below gate is depleted by source and drain fields, which reduce the threshold voltage for short channel. Similar effect is caused by increase in Vds, so threshold is smaller with larger Vds VT

L

Long-channel threshold Low VDS threshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

Vds

VT

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Parasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff

CSQDS

DS RRW

LR ,

,

Silicide the bulk region

increase W

RSQ is the resistance per squareRC is the contact resistance

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Variations in I-V Characteristics

•The velocity of the carriers is proportional to the electric

field up to a point. When electric field reaches a critical

value, Esat, the velocity saturates.

•When the channel length decreases, only a small VDS is

needed for saturation

•Causes a linear dependence of the saturation current wrt

the gate voltage (in contrast to squared dependence of

long-channel device)

•Current drive cannot be increased by decreasing L

•Reduced L decreases the mobility of the carriers due to

the vertical component of the electric field (decreases ID)

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Velocity Saturation

(V/µm)c = 1.5

n

(m/s

)

sat = 105

Constant mobility (slope = µ)

Constant velocity

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Voltage-Current Relation: Velocity Saturation

For short channel devices Linear: When VDS VGS – VT

ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]

where

(V) = 1/(1 + (V/cL)) is a measure of the degree of velocity saturation

Saturation: When VDS = VDSAT VGS – VT

IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]

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Velocity Saturation Effects

VDSAT < VGS – VT so the device enters saturation before VDS reaches VGS – VT and operates more often in saturation

For short channel devices and large enough VGS – VT

IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage

0

10 Long channel devices

Short channel devices

VDSAT VGS-VT

VGS = VDD

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Velocity Saturation

VDS (V)

I D (

mA

)

Lin

ea

r D

ep

en

de

nc

e

VGS = 5

VGS = 4

VGS = 3

VGS = 2

VGS = 1

0.0 1.0 2.0 3.0 4.0 5.0

0.5

1.0

1.5

(a) ID as a function of VDS (b) ID as a function of VGS(for VDS = 5 V).

0.0 1.0 2.0 3.0VGS (V)

0

0.5

I D (

mA

)

Linear Dependence on VGS

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Sub-Threshold Conduction

0 0.5 1 1.5 2 2.510

-12

10-10

10-8

10-6

10-4

10-2

VGS (V)

I D (

A)

VT

Linear

Exponential

Quadratic

Typical values for S:60 .. 100 mV/decade

The Slope Factor

ox

DnkT

qV

D C

CneII

GS

1 ,~ 0

S is VGS for ID2/ID1 =10

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Short Channel I-V Plot (NMOS)

NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

0

0,5

1

1,5

2

2,5

0 0,5 1 1,5 2 2,5

I D (

A)

VDS (V)

X 10-4

VGS = 1.0V

VGS = 1.5V

VGS = 2.0V

VGS = 2.5V

Lin

ear

de

pe

nde

nce

Early VelocitySaturation

Linear Saturation

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Sub-Threshold ID vs VGS

VDS from 0 to 0.5V

kT

qV

nkT

qV

D

DSGS

eeII 10

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Sub-Threshold ID vs VDS

DSkT

qV

nkT

qV

D VeeIIDSGS

110

VGS from 0 to 0.3V

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ID versus VGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS (V)

I D (

A)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VGS (V)

I D (

A)

quadratic

quadratic

linear

Long Channel Short Channel

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ID versus VDS

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

ResistiveSaturation

VDS = VGS - VT

Long Channel Short Channel

EE415 VLSI Design

A unified modelfor manual analysis

S D

G

B

VT0(V) (V0.5) VDSAT(V) k’(A/V2) (V-1)

NMOS 0.43 0.4 0.63 115 x 10-6 0.06

PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1

EE415 VLSI Design

A PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

VDS (V)

I D (

A) Assume all variables

negative!

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V

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The Transistor as a Switch

VGS VT

RonS D

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

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The Transistor as a Switch

0

1

2

3

4

5

6

7

0,5 1 1,5 2 2,5

VDD (V)

Re

q (

Oh

m)

x105

S DRon

VGS VT

VDD(V) 1 1.5 2 2.5

NMOS(k) 35 19 15 13

PMOS (k) 115 55 38 31

(for VGS = VDD, VDS = VDD VDD/2)

Resistance inversely proportional to W/L (doubling W halves Ron)

For VDD>>VT+VDSAT/2, Ron independent of VDD

Once VDD approaches VT, Ron

increases dramatically

Ron (for W/L = 1)For larger devices divide Req by W/L

EE415 VLSI Design

The Transistor as a Switch

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Summary of MOSFET Operating Regions

Strong Inversion VGS > VT

» Linear (Resistive) VDS < VDSAT

» Saturated (Constant Current) VDS VDSAT

Weak Inversion (Sub-Threshold) VGS VT

» Exponential in VGS with linear VDS dependence

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Latchup

(a) Origin of latchup (b) Equivalent circuit

VDD

Rpsubs

Rnwell p-source

n-source

n+ n+p+ p+ p+ n+

p-substrateRpsubs

Rnwell

VDD

n-well

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Fitting level-1 model to short channel characteristics

VGS = 5 V

VDS = 5 V VDS

ID

Long-channel

approximation

Short-channelI-V curve

Region of

matching

Select k’ and such that best matching is obtained @ Vgs= Vds = VDD

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SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular

Berkeley Short-Channel IGFET Model

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MAIN MOS SPICE PARAMETERS

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SPICE Parameters for Parasitics

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SPICE Transistors Parameters

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Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS

(V)

I D (

A)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

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Technology Evolution

EE415 VLSI Design

Process Variations

Devices parameters vary between runs and even on the same die!

Variations in the process parameters, such as impurity concentration den-sities, oxide thicknesses, and diffusion depths. These are caused by non-uniform conditions during the deposition and/or the diffusion of theimpurities. This introduces variations in the sheet resistances and transis-tor parameters such as the threshold voltage.

Variations in the dimensions of the devices, mainly resulting from thelimited resolution of the photolithographic process. This causes (W/L)variations in MOS transistors and mismatches in the emitter areas ofbipolar devices.

EE415 VLSI Design

Impact of Device Variations

1.10 1.20 1.30 1.40 1.50 1.60

Leff (in mm)

1.50

1.70

1.90

2.10

De

lay

(nse

c)

–0.90 –0.80 –0.70 –0.60 –0.50

VTp (V)

1.50

1.70

1.90

2.10

De

lay

(nse

c)

Delay of Adder circuit as a function of variations in L and VT

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Future Perspectives

25 nm FINFET MOS transistor