EE415 VLSI Design

THE INVERTER

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design

DIGITAL GATES Fundamental Parameters

The key parameters that govern a digital gate’s performance and usability.

Area and Complexity Functionality and Robustness

(Reliability) Performance

» Speed (delay)» Power Consumption (dissipation)» Energy

EE415 VLSI Design

Area and Complexity

•Small area very desirable for digital gate

•higher integration density•smaller die size•lower fabrication cost•faster (smaller Cg)

•Implementation area•depends on number of transistors•interconnection area

EE415 VLSI Design

Functionality and Robustness

•Prime requirement for digital gate: •perform designed function

•Measured behavior deviates from expected response. Why?

•variations in process•noise (unwanted variations of voltages and currents at the logic nodes)

•Logic levels•VOH and VOL represent high and low logic levels•difference is called the logic swing

EE415 VLSI Design

Noise in Digital Integrated Circuits

VDDv(t)

i(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground

noise

EE415 VLSI Design

The Voltage-Transfer Characteristic

•Electrical function of gate is best

expressed by its voltage-transfer

characteristic (VTC)

(DC transfer characteristic)

•Plots Vout =f(Vin)

•Gate (Switching) logic threshold voltage,

VM:

•VM=f(VM)

•intersection of VTC at Vout=Vin

EE415 VLSI Design

DC Operation: Voltage Transfer Characteristic (VTC)

V(x)

V(y)

VOH

VOL

VM

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

V(y)V(x)

EE415 VLSI Design

Mapping between analog and digital signals

Problem:•Output signal deviates from expected nominal value due to:

•noise•loading of the gate output

Solution:•Logic levels represented by range of acceptable values

•Regions of acceptable values delimited by VIH and

VIL

•represents points in VTC where (dVout/dVin) = -1•undefined region known as transition width

EE415 VLSI Design

Mapping between analog and digital signals

"1"

"0"

VOH

VIH

VIL

VOL

UndefinedRegion

V(x)

V(y)

VOH

VOL

VIH

VIL

Slope = -1

Slope = -1

EE415 VLSI Design

Noise Margins

•Measure of a gate sensitivity to noise•Quantize the size of legal “0” and “1”•Represents level of noise that can be tolerated when gates are cascaded•NML (noise margin low)

NML = VIL - VOL

•NMH (noise margin high)

NMH = VOH - VIH

•Should be large as possible for good noise immunity

EE415 VLSI Design

Definition of Noise Margins

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

Noise Margin High

Noise Margin Low

EE415 VLSI Design

The Regenerative Property

•Large noise margin alone not sufficient for proper operation•Gate must “boost” weak levels back to nominal values•Known as regeneration (of levels)•Non-regenerative gate output will converge to intermediate value•Conditions for regeneration:

•VTC transient region gain >1 (absolute value)•Gain in the two legal zones must be < 1

EE415 VLSI Design

The Regenerative Property

(a) A chain of inverters.

v0, v2, ...

v1, v3, ... v1, v3, ...

v0, v2, ...

(b) Regenerative gate

f(v)

finv(v)

finv(v)

f(v)

(c) Non-regenerative gate

v0 v1 v2 v3 v4 v5 v6

...

EE415 VLSI Design

Directivity

•A gate must be unidirectional:•input not affected by output changes•causes noise in input otherwise

•Real gate:•full directivity never achievable•capacitive coupling causes feedback

EE415 VLSI Design

Fan-in and Fan-out

•Fan-out:•Number of load gates, N, that are connected to the output of the driving gate•tends to lower the logic levels•deteriorates dynamic performance•gate must have low output resistance to drive load•library cells have maximum fan-out specification

•Fan-in:•Number of inputs, M, to the gate•large fan-in gates are more complex•results in inferior static and dynamic performance

EE415 VLSI Design

Fan-in and Fan-out

N

M

(a) Fan-out N

(b) Fan-in M

EE415 VLSI Design

The Ideal Gate

Vin

Vout

g=

Ri =

Ro = 0

Static CMOS comes close to ideal

EE415 VLSI Design

VTC of Real Inverter

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

1.0

2.0

3.0

4.0

5.0

Vo

ut (V

)

VMNMH

NML

EE415 VLSI Design

Dynamic Behavior

Propagation Delay, Tp

•Defines how quickly output is affected by input•Measured between 50% transition from input to output•tpLH defines delay for output going from low to high

•tpHL defines delay for output going from high to low

•Overall delay, tp, defined as the average of tpLH and

tpHL

EE415 VLSI Design

Dynamic Behavior

Rise and fall time, Tr and Tf

•Defines slope of the signal

•Defined between the 10% and 90% of the

signal swing

Propagation delay and rise and fall times

affected by the fan-out due to larger

capacitance loads

EE415 VLSI Design

Delay Definitions

tpHL

tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf

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The Ring Oscillator

•A standard method is needed to measure the

gate delay

•It is based on the ring oscillator

•2Ntp >> tf + tr for proper operation

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Ring Oscillator

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2 tp N

EE415 VLSI Design

Power Dissipation

•Power consumption determines heat dissipation and

energy consumption

•Influence design decisions:

•packaging and cooling

•width of supply lines

•power-supply capacity

•# of transistors integrated on a single chip

Power requirements make high density bipolar ICs

impossible (feasibility, cost, reliability)

EE415 VLSI Design

Power Dissipation

Battery drain, cooling

Supply-line sizing

EE415 VLSI Design

Power Dissipation

•Ppeak = static power + dynamic power

•Dynamic power:

•(dis)charging capacitors

•temporary paths from VDD to VSS

•proportional to switching frequency

•Static power:

•static conductive paths between rails

•leakage

•increases with temperature

EE415 VLSI Design

Power Dissipation

•Propagation delay is related to power

consumption

•tp determined by speed of charge transfer

•fast charge transfer => fast gate

•fast gate => more power consumption

•Power-delay product (PDP)

•quality measure for switching device

•PDP = energy consumed /gate / switching

event

•measured using ring oscillator

EE415 VLSI Design

Power Dissipation

Supply-line sizing

Battery drain, cooling

Energy consumed /gate /switching event

EE415 VLSI Design

•CMOS technology:

•No path exists between VDD and VSS in

steady state

•No static power consumption! (ideally)

•Main reason why CMOS replaced NMOS in

early 80’s

•NMOS technology:

•Has NMOS pull-up device that is always ON

•Creates voltage divider when pull-down is

ON

•Power consumption puts upper bound on (#

devices / chip)

CMOS Inverter: Steady State Response

EE415 VLSI Design

•VOH = VDD , VOL = VSS (GND)

•voltage swing equal to supply voltage

•provides high noise margins

•Logic levels not dependent on relative device

sizes

•transistors can be minimum size

•known as ratioless logic (as opposed to

ratioed logic based on NMOS devices)

Static CMOS: Properties

EE415 VLSI Design

•Finite resistance always exists between

output and supply rails (in steady state)

•low output impedance (typically 10K ohms)

•less sensitive to noise

•Extremely high input resistance

•MOSFET gate perfect insulator and draws

no DC current

•steady-state input current zero (ignoring

leakage)

•can have large fan-out and still be

functional

•fan-out has no effect on steady-state

behavior

Static CMOS: Properties

EE415 VLSI Design

Voltage Transfer

Characteristic

EE415 VLSI Design

CMOS Inverter Load Characteristics

VDD

Vin Vout

CL

G S

D

D

G

S

EE415 VLSI Design

PMOS Load Lines

VDSp

IDp

VGSp=-5

VGSp=-2VDSp

IDnVin=0

Vin=3

Vout

IDnVin=0

Vin=3

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

Vout

IDn

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

VDD

Vin Vout

CL

G S

D

D

G

S

EE415 VLSI Design

CMOS Inverter Load Lines

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5

I Dn (

A)

Vout (V)

X 10-4

Vin = 1.0V

Vin = 1.5V

Vin = 2.0V

Vin = 2.5VVin = 0V

Vin = 0.5V

Vin = 1.0V

Vin = 1.5VVin = 0.5VVin = 2.0V

Vin = 2.5V

Vin = 2VVin = 1.5V Vin = 1V

Vin = 0.5V

Vin = 0V

PMOS NMOS

EE415 VLSI Design

Cutoff Linear Saturation

pMOS Vin -VDD= VGS> VT Vin -VDD=VGS< VT

Vin -Vout=VGD< VT

Vin -VDD=VGS> VT

Vin -Vout=VGD>VT

nMOS Vin = VGS< VT Vin =VGS> VT

Vin -Vout =VGD> VT

Vin =VGS> VT

Vin -Vout =VGD< VT

VDD

Vin Vout

CL

G S

D

D

G

S

Regions of operationsFor nMOS and pMOSIn CMOS inverter

EE415 VLSI Design

CMOS Inverter Load Characteristics

•For valid dc operating points:

•current through NMOS = current through

PMOS

•=> dc operating points are the intersection of

load lines

•All operating points located at high or low

output levels

•=> VTC has narrow transition zone

•high gain of transistors during switching

•transistors in saturation•high transconductance (gm)

•high output resistance (voltage controlled current

source)

EE415 VLSI Design

CMOS Inverter VTC

00.5

11.5

22.5

0 0.5 1 1.5 2 2.5Vin (V)

Vo

ut (

V)

NMOS offPMOS res

NMOS satPMOS res

NMOS satPMOS sat

NMOS resPMOS sat NMOS res

PMOS off

EE415 VLSI Design

Voltage TransferCharacteristic

EE415 VLSI Design

Switching Threshold

VM where Vin = Vout (both PMOS and NMOS in saturation since VDS = VGS)

VM rVDD/(1 + r) where r = kpVDSATp/knVDSATn

Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors

Want VM = VDD/2 (to have comparable high and low noise margins), so want r 1

(W/L)p kn’VDSATn(VM-VTn-VDSATn/2)

(W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2)

=

EE415 VLSI Design

Switch Threshold Example In our generic 0.25 micron CMOS process, using the

process parameters from table a VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5)

VT0(V) (V0.5) VDSAT(V) k’(A/V2) (V-1)

NMOS 0.43 0.4 0.63 115 x 10-6 0.06

PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1

(W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2)

(W/L)n -30 x 10-6 -1.0 (1.25 – 0.4 – 1.0/2)= x x = 3.5

(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V

EE415 VLSI Design

Simulated Inverter VM

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

0 1 10(W/L)p/(W/L)n

VM (

V)

VM is relatively insensitive to variations in device ratio

setting the ratio to 3, 2.5 and 2 gives VM’s of 1.22V, 1.18V, and 1.13V

Increasing the width of the PMOS moves VM towards VDD

Increasing the width of the NMOS moves VM toward GND

.1

Note: x-axis is semilog

~3.4

EE415 VLSI Design

Noise Margins Determining VIH and VIL

0

1

2

3

VIL VIHVin

Vo

ut

VOH = VDD

VM

By definition, VIH and VIL are where dVout/dVin = -1 (= gain)

VOL = GND

A piece-wise linear approximation of VTC

NMH = VDD - VIH

NML = VIL - GND

Approximating: VIH = VM - VM /g VIL = VM + (VDD - VM )/g

So high gain in the transition region is very desirable

EE415 VLSI Design

CMOS Inverter VTC from Simulation

00.5

11.5

22.5

0 0.5 1 1.5 2 2.5

Vin (V)

Vo

ut (

V)

0.25um, (W/L)p/(W/L)n = 3.4(W/L)n = 1.5 (min size)VDD = 2.5V

VM 1.25V, g = -27.5

VIL = 1.2V, VIH = 1.3VNML = NMH = 1.2(actual values are VIL = 1.03V, VIH = 1.45VNML = 1.03V & NMH = 1.05V)

Output resistance low-output = 2.4khigh-output = 3.3k

EE415 VLSI Design

Gain Determinates

Gain is a strong function of the slopes of the currents in the saturation region, for Vin = VM

(1+r)g ---------------------------------- (VM-VTn-VDSATn/2)(n - p )

Determined by technology parameters, especially channel length modulation (). Only designer influence through supply voltage and VM (transistor sizing).-18

-16

-14

-12

-10

-8

-6

-4

-2

0

0 0.5 1 1.5 2

Vin

gai

n

EE415 VLSI Design

Impact of Process Variation

00.5

11.5

22.5

0 0.5 1 1.5 2 2.5

Vin (V)

Vo

ut (

V)

Nominal

Good PMOSBad NMOS

Bad PMOSGood NMOS

Pprocess variations (mostly) cause a shift in the switching threshold

EE415 VLSI Design

Scaling the Supply Voltage

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5Vin (V)

Vo

ut (

V)

Device threshold voltages are kept (virtually) constant

0

0.05

0.1

0.15

0.2

0 0.05 0.1 0.15 0.2

Vin (V)

Vo

ut (

V)

Gain=-1

Device threshold voltages are kept (virtually) constant

EE415 VLSI Design

Propagation Delay

EE415 VLSI Design

Switch Model of Dynamic Behavior

VDD

Rn

Vout

CL

Vin = V DD

VDD

Rp

Vout

CL

Vin = 0 Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)

EE415 VLSI Design

What is the Inverter Driving?

VDD VDD

VinVout

M1

M2

M3

M4Cdb 2

Cdb 1

Cgd 12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CL

SimplifiedModel

EE415 VLSI Design

CMOS Inverter Propagation Delay

Approach 1

VDD

Vout

Vin = VDD

CLIav

tpHL = CL Vswing/2

Iav

CL

kn VDD

~

EE415 VLSI Design

VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

)/( LonCRtOHout eVV

CMOS Inverter Propagation Delay

Approach 2

EE415 VLSI Design

CMOS Inverter: Transient Response

How can the designer build a fast gate?

•tpHL = f(Ron*CL)

•Keep output capacitance, CL, small

•low fan-out

•keep interconnections short (floor-plan

your layout!)

•Decrease on-resistance of transistor

•increase W/L ratio

•make good contacts (slight effect)

EE415 VLSI Design

CMOS Properties

Full rail-to-rail swing Symmetrical VTC Propagation delay function of load

capacitance and resistance of transistors

No static power dissipation Direct path current during switching

EE415 VLSI Design

MOS Transistor Small Signal Model

rogmvgsvgs

+

-

S

DG

Define

EE415 VLSI Design

Determining VIH and VIL

VIH and VIL are based on derivative of VTC equal to -1

EE415 VLSI Design

0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vou

t(V)

Transient Response

tp = 0.69 CL (Reqn+Reqp)/2

?

tpLHtpHL

EE415 VLSI Design

Inverter Transient Response

VDD=2.5V0.25mW/Ln = 1.5W/Lp = 4.5Reqn= 13 k ( 1.5)Reqp= 31 k ( 4.5)tpHL = 36 psec

tpLH = 29 psec

so

tp = 32.5 psec

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vin

Vo

u t (V

)

t (sec) x 10-10

tf trtpHL tpLH

From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec

EE415 VLSI Design

Design for Performance

Keep capacitances small Increase transistor sizes

» watch out for self-loading!

Increase VDD (????)

EE415 VLSI Design

Delay as a function of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(nor

mal

ized

)

EE415 VLSI Design

Sizing Impacts on Delay

The majority of the improvement is already obtained for S = 5. Sizing factors larger than 10 barely yield any extra gain (and cost significantly more area).

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1 3 5 7 9 11 13 15

S

t p(s

ec)

x 10-11

for a fixed load

self-loading effect (intrinsic capacitance dominates)

EE415 VLSI Design

PMOS/NMOS Ratio Effects

of 2.4 (= 31 k/13 k) gives symmetrical response

of 1.6 to 1.9 gives optimal performance

3

3.5

4

4.5

5

1 2 3 4 5

= (W/Lp)/(W/Ln)

t p(s

ec)

x 10-11

tpLH

tp

tpHL

EE415 VLSI Design

Impact of Rise Time on Delayt p

HL(n

sec

)

0.35

0.3

0.25

0.2

0.15

trise (nsec)10.80.60.40.20

Rise time is a function of fan-in

EE415 VLSI Design

Inverter Sizing

EE415 VLSI Design

CMOS Inverter: Four Views

Logic Transistor Layout Physical

Vdd

Gnd

Vin Vout Vin Vout

EE415 VLSI Design

CMOS Inverter Layout

VDD

GND

NMOS (2/.24 = 8/1)

PMOS (4/.24 = 16/1)

metal2

metal1polysilicon

InOut

metal1-poly via

metal2-metal1 via

metal1-diff via

pdiff

ndiff

EE415 VLSI Design

Inverter Delay• Minimum length devices, L=0.25m• Assume that for WP = 2WN =2W

• same pull-up and pull-down currents• approx. equal resistances RN = RP

• approx. equal rise tpLH and fall tpHL delays• Analyze as an RC network

WNunit

Nunit

unit

PunitP RR

W

WR

W

WRR

11

tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):

2W

W

unitunit

gin CW

WC 3Load for the next stage:

EE415 VLSI Design

Inverter with Load

Load (CL)

Delay

Assumptions: no load -> zero delay

CL

tp = k RWCL

RW

RW

Wunit = 1

k is a constant, equal to 0.69

EE415 VLSI Design

Inverter with Load

Load

Delay

Cint CL

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)

CN = Cunit

CP = 2Cunit

2W

W

EE415 VLSI Design

Delay Formula

/1/1

~

0int ftCCCkRt

CCRDelay

pintLWp

LintW

Cint = Cgin with 1f = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunit

tp0 = 0.69RunitCunit

EE415 VLSI Design

Impact of Fanout on Delay

Extrinsic capacitance, Cext, is a function of the fanout of the gate - the larger the fanout, the larger the external load.

First determine the input loading effect of the inverter. Both Cg and Cint are proportional to the gate sizing, so Cint = Cg is independent of gate sizing and

tp = tp0 (1 + Cext/ Cg) = tp0 (1 + f/)

i.e., the delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan-out f

f = Cext/Cg

EE415 VLSI Design

Inverter Chain

If CL is given

» How should the inverters be sized?» How many stages are needed to minimize the delay?

Real goal is to minimize the delay through an inverter chain

the delay of the j-th inverter stage is

tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ )

and tp = tp1 + tp2 + . . . + tpN

so tp = tp,j = tp0 (1 + Cg,j+1/(Cg,j))

In Out

CLCg,1

1 2 N

EE415 VLSI Design

Apply to Inverter Chain

CL

In Out

1 2 N

tp = tp1 + tp2 + …+ tpN

jgin

jginunitunitpj C

CCRt

,

1,1~

LNgin

N

i jgin

jginp

N

jjpp CC

C

Cttt

1,

1 ,

1,0

1, ,1

EE415 VLSI Design

Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay

1,1,, jginjginjgin CCC

EE415 VLSI Design

Optimum Delay and Number of Stages

1,/ ginLN CCFf

When each stage is sized by f and has same eff. fanout f:

N Ff

/10N

pp FNtt

Minimum path delay

Effective fanout of each stage:

EE415 VLSI Design

Example

CL= 8 C1

In Out

C11 f f2

283 f

CL/C1 has to be evenly distributed across N = 3 stages:

EE415 VLSI Design

Determining N: Optimal Number of Inverters

What is the optimal value for N given F (=fN) ?» if the number of stages is too large, the intrinsic delay of the

stages becomes dominate» if the number of stages is too small, the effective fan-out of each

stage becomes dominate

N N

The optimum N is found by differentiating the minimum delay expression divided by the number of stages and setting the result to 0, giving

+ F - ( F lnF)/N = 0 For = 0 (ignoring self-loading) N = ln (F) and the effective-fan out

becomes f = e = 2.71828 For = 1 (the typical case) the optimum effective fan-out (tapering

factor) turns out to be close to 3.6

EE415 VLSI Design

Optimum Number of Stages

For a given load, CL and given input capacitance Cin

Find optimal sizing f

ff

fFtFNtt pN

pp lnln

ln1/ 0/1

0

0ln

1lnln2

0

f

ffFt

f

t pp

For = 0, f = e, N = lnF

f

FNCfCFC in

NinL ln

ln with

ff 1exp

EE415 VLSI Design

Optimum Effective Fan-Out

Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area).» Common practice to use f = 4 (for = 1)» But too many stages has a substantial negative impact on delay

2.5

3

3.5

4

4.5

5

0 0.5 1 1.5 2 2.5 3

Fo

p

t

0

1

2

3

4

5

6

7

1 1.5 2 2.5 3 3.5 4 4.5 5

fn

o rm

al iz

ed

de

lay

EE415 VLSI Design

Example of Inverter (Buffer) Staging

CL = 64 Cg,1Cg,1 = 1

1

CL = 64 Cg,1Cg,1 = 1

1 8

CL = 64 Cg,1Cg,1 = 1

1 4 16

CL = 64 Cg,1Cg,1 = 1

1 2.8 8 22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

EE415 VLSI Design

Impact of Buffer Staging for Large CL

Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads.

F ( = 1) Unbuffered Two Stage Chain

Opt. Inverter Chain

10 11 8.3 8.3

100 101 22 16.5

1,000 1001 65 24.8

10,000 10,001 202 33.1

EE415 VLSI Design

Input Signal Rise/Fall Time

In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CL and impacts propagation delay.

3.6

3.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

0 2 4 6 8ts(sec)

t p(s

ec)

x 10-11

x 10-11

for a minimum-size inverter with a fan-out of a single gate

tp increases linearly with increasing input slope, ts, once ts > tp

ts is due to the limited driving capability of the preceding gate

EE415 VLSI Design

Design Challenge

A gate is never designed in isolation: its performance is affected by both the fan-out and the driving strength of the gate(s) feeding its inputs.

tip = ti

step + ti-1step ( 0.25)

Keep signal rise times smaller than or equal to the gate propagation delays.» good for performance» good for power consumption

Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering.

EE415 VLSI Design

Delay with Long Interconnects

When gates are farther apart, wire capacitance and resistance can no longer be ignored.

tp = 0.69RdrCint + (0.69Rdr+0.38Rw)Cw + 0.69(Rdr+Rw)Cfan

where Rdr = (Reqn + Reqp)/2

= 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2

cint

Vin

cfan

(rw, cw, L)Vout

Wire delay rapidly becomes the dominate factor (due to the quadratic term) in the delay budget for longer wires.

EE415 VLSI Design

Power Dissipation

EE415 VLSI Design

Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

EE415 VLSI Design

Dynamic Power Dissipation

Vin Vout

CL

Vdd

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Need to reduce CL, Vdd, and f to reduce power.

Not a function of transistor sizes!

EE415 VLSI Design

Modification for Circuits with Reduced Swing

CL

Vdd

Vdd

Vdd -Vt

E0 1 CL Vdd Vdd Vt– =

Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)

EE415 VLSI Design

Adiabatic Charging

22

2

EE415 VLSI Design

Adiabatic Charging

EE415 VLSI Design

Node Transition Activity and PowerNode Transition Activity and Power

Consider switching a CMOS gate for N clock cycles

EN CL Vdd 2 n N =

n(N): the number of 0->1 transition in N clock cycles

EN : the energy consumed for N clock cycles

Pavg N lim

ENN

-------- fclk= n N

N------------

N lim

C

LVdd

2fclk

=

0 1

n N N

------------N

lim=

Pavg = 0 1 C

LVdd

2 fclk

EE415 VLSI Design

Transistor Sizing for Minimum Energy

Goal: Minimize Energy of whole circuit» Design parameters: f and VDD

» tp tpref of circuit with f=1 and VDD =Vref

1Cg1

In

fCext

Out

TEDD

DDp

pp

VV

Vt

f

Fftt

0

0 11

EE415 VLSI Design

Transistor Sizing (2) Performance Constraint (=1)

Energy for single Transition

13

2

3

2

0

0

F

fF

f

VV

VV

V

V

F

fF

f

t

t

t

t

TEDD

TEref

ref

DD

refp

p

pref

p

F

Ff

V

V

E

E

FfCVE

ref

DD

ref

gDD

4

22

112

12

EE415 VLSI Design

1 2 3 4 5 6 70

0.5

1

1.5

2

2.5

3

3.5

4

f

vdd

(V

)

1 2 3 4 5 6 70

0.5

1

1.5

f

no

rma

lize

d e

ne

rgy

Transistor Sizing (3)

F=1

2

5

10

20

VDD=f(f) E/Eref=f(f)

EE415 VLSI Design

Short Circuit CurrentsShort Circuit Currents

Vin Vout

CL

Vdd

I VD

D (m

A)

0.15

0.10

0.05

Vin (V)5.04.03.02.01.00.0

EE415 VLSI Design

How to keep Short-Circuit Currents Low?How to keep Short-Circuit Currents Low?

Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic, so ...

EE415 VLSI Design

Minimizing Short-Circuit PowerMinimizing Short-Circuit Power

0 1 2 3 4 50

1

2

3

4

5

6

7

8

tsin

/tsout

Pno

rm

Vdd =1.5

Vdd =2.5

Vdd =3.3

EE415 VLSI Design

LeakageLeakage

Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

Sub-Threshold Current Dominant FactorSub-threshold current one of most compelling issuesin low-energy circuit design!

EE415 VLSI Design

Reverse-Biased Diode LeakageReverse-Biased Diode Leakage

Np+ p+

Reverse Leakage Current

+

-Vdd

GATE

IDL = JS A

JS = 1-5pA/m2 for a 1.2m CMOS technology

Js double with every 9oC increase in temperature

JS = 10-100 pA/m2 at 25 deg C for 0.25m CMOSJS doubles for every 9 deg C!

EE415 VLSI Design

Subthreshold Leakage ComponentSubthreshold Leakage Component

EE415 VLSI Design

Static Power ConsumptionStatic Power Consumption

Vin=5V

Vout

CL

Vdd

Istat

Pstat = P(In=1).Vdd . Istat

• Dominates over dynamic consumption

• Not a function of switching frequency

Wasted energy …Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)

EE415 VLSI Design

Principles for Power Reduction

Prime choice: Reduce voltage!» Recent years have seen an acceleration in supply

voltage reduction» Design at very low voltages still open question (0.6

… 0.9 V by 2010!)

Reduce switching activity Reduce physical capacitance

» Device Sizing: for F=20– fopt(energy)=3.53, fopt(performance)=4.47

EE415 VLSI Design

Impact ofTechnology

Scaling

EE415 VLSI Design

Goals of Technology Scaling

Make things cheaper:» Want to sell more functions (transistors)

per chip for the same money» Build same products cheaper, sell the

same part for less money» Price of a transistor has to be reduced

But also want to be faster, smaller, lower power

EE415 VLSI Design

Technology Scaling

Goals of scaling the dimensions by 30%:» Reduce gate delay by 30% (increase operating

frequency by 43%)» Double transistor density» Reduce energy per transition by 65% (50% power

savings @ 43% increase in frequency

Die size used to increase by 14% per generation

Technology generation spans 2-3 years

EE415 VLSI Design

Technology Generations

EE415 VLSI Design

Technology Evolution (2000 data)

International Technology Roadmap for Semiconductors

18617717116013010690Max P power [W]

1.4

1.2

6-7

1.5-1.8

180

1999

1.7

1.6-1.4

6-7

1.5-1.8

2000

14.9-3.6

11-37.1-2.53.5-22.1-1.6Max frequency

[GHz],Local-Global

2.52.32.12.42.0Bat. power [W]

109-10987Wiring levels

0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V]

30406090130Technology node

[nm]

20142011200820042001Year of

Introduction

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

EE415 VLSI Design

Technology Evolution (1999)

EE415 VLSI Design

ITRS Technology Roadmap Acceleration Continues

EE415 VLSI Design

Technology Scaling (1)

Minimum Feature Size 1960 1970 1980 1990 2000 2010

10-2

10-1

100

101

102

Year

Min

imum

Fea

ture

Siz

e (m

icro

n)

EE415 VLSI Design

Technology Scaling (2)

Number of components per chip

EE415 VLSI Design

Technology Scaling (3)

Propagation Delay

tp decreases by 13%/year 50% every 5 years!

EE415 VLSI Design

Technology Scaling Models

• Full Scaling (Constant Electrical Field)

• Fixed Voltage Scaling

• General Scaling

ideal model — dimensions and voltage scaletogether by the same factor S

most common model until recently —only dimensions scale, voltages remain constant

most realistic for todays situation —voltages and dimensions scale with different factors

EE415 VLSI Design

Scaling Relationships for Long Channel

Devices

EE415 VLSI Design

Transistor Scaling(velocity-saturated devices)

EE415 VLSI Design

Dilbert

EE415 VLSI Design

Dilbert

EE415 VLSI Design

Dilbert

EE415 VLSI Design

Dilbert

EE415 VLSI Design

Dilbert