jan m. rabaey anantha chandrakasan borivoje nikolićbaccaran/rabaey/chapter10.pdfee141 1 © digital...

EE1411

© Digital Integrated Circuits2nd Timing Issues

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Timing IssuesTiming Issues

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolić

January 2003

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Synchronous TimingSynchronous Timing

CombinationalLogic

R1 R2Cin Cout Out

In

CLK

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Timing Timing DefinitionsDefinitions

EE1414


Latch ParametersLatch Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

PWm tsu

td-q

Delays can be different for rising and falling data transitions

T

EE1415


Register ParametersRegister Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

T

tsu

Delays can be different for rising and falling data transitions

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Clock UncertaintiesClock Uncertainties

2

43

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

Sources of clock uncertainty

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ClockClock NonidealitiesNonidealities

Clock skewSpatial variation in temporally equivalent clock edges; deterministic + random, tSK

Clock jitterTemporal variations in consecutive edges of the clock signal; modulation + random noiseCycle-to-cycle (short-term) tJSLong term tJL

Variation of the pulse width Important for level sensitive clocking

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Clock Skew and JitterClock Skew and Jitter

Both skew and jitter affect the effective cycle timeOnly skew affects the race margin

Clk

Clk

tSK

tJS

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Clock SkewClock Skew# of registers

Clk delayInsertion delayMax Clk skew

Earliest occurrenceof Clk edgeNominal – δ/2

Latest occurrenceof Clk edge

Nominal + δ /2

δ

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Positive and Negative SkewPositive and Negative Skew

R1In

(a) Positive skew

CombinationalLogicD Q

tCLK1CLK

delay

tCLK2

R2D Q Combinational

Logic

tCLK3

R3• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogicD Q

tCLK1

delay

tCLK2

R2D Q Combinational

Logic

tCLK3

R3• • •D Q

delay CLK

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Positive SkewPositive Skew

CLK1

CLK2

TCLK

δ

TCLK + δ

+ thδ

2

1

4

3

Launching edge arrives before the receiving edge

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Negative SkewNegative Skew

CLK1

CLK2

TCLK

δ

TCLK + δ

2

1

4

3

Receiving edge arrives before the launching edge

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Timing ConstraintsTiming Constraints

R1D Q Combinational

LogicIn

CLK tCLK1

R2D Q

tCLK2

tc − qtc − q, cdtsu, thold

tlogictlogic, cd

Minimum cycle time:T - δ = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (positive δ)

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Timing ConstraintsTiming ConstraintsR1

D Q CombinationalLogic

In

CLK tCLK1

R2D Q

tCLK2

tc − qtc − q, cdtsu, thold

tlogictlogic, cd

Hold time constraint:t(c-q, cd) + t(logic, cd) > thold + δ

Worst case is when receiving edge arrives lateRace between data and clock

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Impact of JitterImpact of Jitter

CLK-tji tter

TC LK

t j itter

CLK

InCombinational

Logic

tc-q , tc-q, cdt log ict log ic, cdtsu, thold

REGS

tjitter

1

2

3 4

5

6

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Longest Logic Path in Longest Logic Path in EdgeEdge--Triggered SystemsTriggered Systems

Clk

T

TSU

TClk-Q TLM

Latest point of launching

Earliest arrivalof next cycle

TJI + δ

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Clock Constraints in Clock Constraints in EdgeEdge--Triggered SystemsTriggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU < T – TJI,1 – TJI,2 - δ

Tc-q + TLM + TSU + δ + 2 TJI < T

Skew can be either positive or negative

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Shortest PathShortest Path

ClkTClk-Q TLm

Earliest point of launching

Data must not arrivebefore this time

ClkTH

Nominalclock edge

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Clock Constraints Clock Constraints in Edgein Edge--Triggered SystemsTriggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

Tc-q + TLM – TJI,1 < TH + TJI,2 + δ

Tc-q + TLM < TH + 2TJI+ δ

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How to counter Clock Skew?How to counter Clock Skew?

RE

G

φ

REG

φR

EG

φ

.

REG

φ

log Out

In

Clock Distribution

Positive Skew

Negative Skew

Data and Clock Routing

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FlipFlip--Flop Flop –– Based TimingBased Timing

Flip-flop

Logic

φ

φ = 1φ = 0

Flip-flopdelay

Skew

Logic delay

TSUTClk-Q

Representation after M. Horowitz, VLSI Circuits 1996.

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FlipFlip--Flops and Dynamic LogicFlops and Dynamic Logic

φ = 1φ = 0

Logic delay

TSUTClk-Q

φ = 1φ = 0

Logic delay

TSUTClk-Q

PrechargeEvaluateEvaluatePrecharge

Flip-flops are used only with static logic

EE14123


Latch timingLatch timing

D

Clk

Q

tD-Q

tClk-Q

When data arrives to transparent latch

When data arrives to closed latch

Data has to be ‘re-launched’

Latch is a ‘soft’ barrier

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SingleSingle--Phase Clock with LatchesPhase Clock with Latches

Latch

Logic

φ

Clk

P

PW

Tskl Tskl TsktTskt

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LatchLatch--Based DesignBased Design

L1Latch Logic

Logic

L2Latch

φ

L1 latch is transparentwhen φ = 0

L2 latch is transparent when φ = 1

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SlackSlack--borrowingborrowing

QDIn CLB_A QD QD

CLK1

L1 L2 L1

CLK2 CLK1

CLB_Btpd,A tpd,B

CLK1

CLK2

TCLK

321 4

a b c d e

tpd,A

a valid b val id

tDQtpd,B

c valid d valid

tDQ

e valid

slack passed to next stage

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LatchLatch--Based TimingBased Timing

L1Latch Logic

Logic

L2Latch

φ

φ = 1

φ = 0

L1 latch

L2 latch

Skew

Can tolerate skew!

Longpath

Shortpath

Static logic

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Clock DistributionClock Distribution

CLK

Clock is distributed in a tree-like fashion

H-tree

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More realistic HMore realistic H--treetree

[Restle98]

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The Grid SystemThe Grid System

Driver

Driver

Dri

ver

Driv

er

GCLK GCLK

GCLK

GCLK

•No rc-matching•Large power

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Example: DEC Alpha 21164Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million Transistors

Total Clock Load: 3.75 nF

Power in Clock Distribution network : 20 W (out of 50)

Uses Two Level Clock Distribution:

• Single 6-stage driver at center of chip• Secondary buffers drive left and right side

clock grid in Metal3 and Metal4Total driver size: 58 cm!

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21164 Clocking21164 Clocking2 phase single wire clock, distributed globally2 distributed driver channels

Reduced RC delay/skewImproved thermal distribution3.75nF clock load58 cm final driver width

Local inverters for latchingConditional clocks in caches to reduce powerMore complex race checkingDevice variation

trise = 0.35ns tskew = 150ps

tcycle= 3.3ns

Clock waveform

Location of clockdriver on die

pre-driver

final drivers

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Clock Drivers

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Clock Skew in Alpha ProcessorClock Skew in Alpha Processor

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2 Phase, with multiple conditional buffered clocks

2.8 nF clock load40 cm final driver width

Local clocks can be gated “off” to save powerReduced load/skewReduced thermal issuesMultiple clocks complicate race checking

trise = 0.35ns tskew = 50ps

tcycle= 1.67ns

EV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz 600 MHz –– 0.35 micron CMOS0.35 micron CMOS

Global clock waveform

PLL

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21264 Clocking21264 Clocking

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EV6 Clock ResultsEV6 Clock Results

GCLK Skew(at Vdd/2 Crossings)

ps5

101520253035404550

ps300305310315320325330335340345

GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)

EE14138


EV7 Clock HierarchyEV7 Clock Hierarchy

GCLK(CPU Core)L2

L_C

LK(L

2 C

ache

)

L2R

_CLK

(L2

Cac

he)

NCLK(Mem Ctrl)

DLL

PLL

SYSCLK

DLL

DLL

+ widely dispersed drivers

+ DLLs compensate static and low-frequency variation

+ divides design and verification effort

- DLL design and verification is added work

+ tailored clocks

Active Skew Management and Multiple Clock Domains

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SelfSelf--timed and Asynchronous timed and Asynchronous DesignDesign

Functions of clock in synchronous design

1) Acts as completion signal2) Ensures the correct ordering of events

Truly asynchronous design

2) Ordering of events is implicit in logic1) Completion is ensured by careful timing analysis

Self-timed design

1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol

EE14140


Synchronous PipelinedSynchronous Pipelined DatapathDatapath

In

tpd,reg tpd1

DR1

Q

CLK

LogicBlock #1

tpd2

DR2

QLogic

Block #2

tpd3

DR3

Q DR4

QLogic

Block #3

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SelfSelf--Timed PipelinedTimed Pipelined DatapathDatapath

R2 OutF2In

tpF2

Start Done

R1 F1

tpF1

Start Done

R3 F3

tpF3

Start Done

Req Req Req Req

Ack Ack Ack ACKHS HS HS

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Completion Signal GenerationCompletion Signal Generation

LOGIC

NETWORK

DELAY MODULE

In Out

Start Done

Using Delay Element (e.g. in memories)

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Completion Signal GenerationCompletion Signal Generation

Using Redundant Signal Encoding

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Completion Signal in DCVSLCompletion Signal in DCVSL

PDN

B0

PDNIn1In1In2In2

B1

Start

Start

VDD VDD

DoneB0

B1

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SelfSelf--Timed AdderTimed Adder

P0

C0

P1

G0

P2

G1

P3

G2 G3

VDD

Start

Start

P0

C0

P1

K0

P2

K1

P3

K2 K3

VDD

Start

Start

C0 C1 C2 C3 C4 C4

C4C0 C1 C2 C3 C4

VDD

Start

C4

C3

C2

C1

C4

C3

C2

C1

Start Done

(a) Differential carry generation

(b) Completion signal

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Completion Signal Using Current SensingCompletion Signal Using Current Sensing

Min Delay Generator

StartGNDsense

VDD

Inputs

Current Sensor

Static CMOS Logic

Inpu

t Reg

iste

r

Done

Output

A

B

tdelay

toverlap

tpd-NOR

tMDG

Start

A

B

Done

Output valid

EE14147


HandHand--Shaking ProtocolShaking Protocol

11

3RECEIVERSENDER

Req Req

Ack

Data

Ack

Data

(a) Sender-receiver configuration

(b) Timing diagram

cycle 1 cycle 2Sender’s actionReceiver’s action

2

Two Phase Handshake

EE14148


Event Logic Event Logic –– The MullerThe Muller--C ElementC ElementA B Fn+1

0011

010

(b) Truth table(a) Schematic

1

0FnFn1

F

A

BC

S

FF

R

QA

B

(a) Logic

(b) Majority Function

(c) Dynamic

A B

B

B

A

VDD

B

FA

B

VDDVDD

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22--Phase Handshake ProtocolPhase Handshake Protocol

Advantage : FAST - minimal # of signaling events (important for global interconnect)

Disadvantage : edge - sensitive, has state

Senderlogic

Receiverlogic

Data

Handshake logic

Data ready Data accepted

CReq

Ack

EE14150


Example: SelfExample: Self--timed FIFOtimed FIFO

All 1s or 0s -> pipeline empty

Alternating 1s and 0s -> pipeline full

C C

R1In Out

En

Acki

Reqi

R2 R3

CReq0

Acko

Done

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22--Phase ProtocolPhase Protocol

EE14152


ExampleExample

From [Horowitz]

EE14153


ExampleExample

EE14154


ExampleExample

EE14155


ExampleExample

EE14156


44--Phase Handshake ProtocolPhase Handshake Protocol

Slower, but unambiguous

Also known as RTZ

1 1

2

3 5

4Req

Ack

Data

Cycle 1 Cycle 2

Sender’s action

Receiver’s action

EE14157


44--Phase Handshake ProtocolPhase Handshake ProtocolImplementation using Muller-C elements

Handshake logic

Data ready Data accepted

ReqS

Ack

C C

Senderlogic

Receiverlogic

Data

EE14158


SelfSelf--Resetting LogicResetting Logic

PrechargedLogic Block(L1)



completiondetection

(L1)

completiondetection

(L2)

completiondetection

(L3)

VDD

A B C

intout

Post-chargelogic

EE14159


ClockClock--Delayed DominoDelayed Domino

PulldownNetwork

CLK1

GND

CLK2 (to next stage)

Q1 (also D2)

D1

VDD

EE14160


AsynchronousAsynchronous--Synchronous InterfaceSynchronous Interface

Asynchronoussystem

Synchronous system

Synchronization

fCLK

fin

EE14161


Synchronizers and ArbitersSynchronizers and Arbiters

Arbiter: Circuit to decide which of 2 events occurred firstSynchronizer: Arbiter with clock φ as one of the inputsProblem: Circuit HAS to make a decision in limited time - which decision is not importantCaveat: It is impossible to ensure correct operationBut, we can decrease the error probability at the expense of delay

EE14162


A Simple Synchronizer A Simple Synchronizer

• Data sampled on rising edge of the clock

• Latch will eventually resolve the signal value,but ... this might take infinite time!

CLK

int

I2

I1D Q

CLK

EE14163


Synchronizer: Output Trajectories Synchronizer: Output Trajectories

Single-pole model for a flip-flop

2.0

1.0

0.00 100 200 300

Vou

t

time [ps]

EE14164


Mean Time to FailureMean Time to Failure

EE14165


ExampleExampleTf = 10 nsec = TTsignal = 50 nsectr = 1 nsect = 310 psecVIH - VIL = 1 V (VDD = 5 V)

N(T) = 3.9 10-9 errors/secMTF (T) = 2.6 108 sec = 8.3 yearsMTF (0) = 2.5 µsec

EE14166


Influence of NoiseInfluence of Noise

Initial Distribution

p(v)

0 VIL VIH

T

Uniform distributionaround VM

Still Uniform

logarithmic reduction

Low amplitude noise does not influence synchronization behavior

EE14167


Typical SynchronizersTypical Synchronizers

φ1

φ2

Q

Q

φ1

φ2

Using delay line

2 phase clocking circuit

EE14168


Cascaded Synchronizers Reduce MTFCascaded Synchronizers Reduce MTF

Sync Sync SyncIn O1 O2 Out

φ

EE14169


ArbitersArbiters

Req1

Req2

Req1

Req2

Ack1

Ack2Arbiter

Ack1

Ack2

(a) Schematic symbol

(b) Implementation

A

B

Req1

Req2

A

BAck1 t

(c) Timing diagramVT gap

metastable

EE14170


PLLPLL--Based SynchronizationBased Synchronization

DigitalSystem

Divider

CrystalOscillator

PLL

Chip 1

DigitalSystem

PLL

Chip 2

fsystem = N x fcrystal

fcrystal , 200<Mhz

Data

ClockBuffer

referenceclock

EE14171


PLL Block DiagramPLL Block Diagram

Phasedetector

Chargepump

Divide byN

Loopfilter VCO

Referenceclock

Localclock

SystemClock

Up

Down

vcont

EE14172


Phase DetectorPhase Detector

ref

localclock

localclock

Output

Output

ref

VDD

-180 -90 90 180 phase error (deg)

Output (Low pass filtered)(a)

(c)

(b)

Output before filtering

Transfercharacteristic

EE14173


PhasePhase--Frequency DetectorFrequency Detector

(c) Timing waveforms

(a) schematic (b) state transition diagram

A

B

UP

DN

A

B

UP

DN

D Q

D Q

A

B

Rst

Rst

UP

DN

UP = 0DN = 1

UP = 0DN = 0

UP = 1DN = 0

B

B A

A

A B

EE14174


PFD Response to FrequencyPFD Response to Frequency

A

B

UP

DN

EE14175


PFD Phase Transfer CharacteristicPFD Phase Transfer Characteristic

VDD

phase error (deg)

Average (UP-DN)

2π

−2 π

EE14176


Charge PumpCharge PumpVDD

UP

DN

To VCO Control Input

EE14177


PLL SimulationPLL Simulation

00.0

0.2

0.4

0.6

0.8

1.0

1 2 3 4 5

Con

trol V

olta

ge (V

)

Time ( s)µ

ref

div

vco

ref

div

vco

EE14178


Clock Generation using DLLsClock Generation using DLLs

PhaseDet

ChargePump

FilterDL

PD CP VCO÷N

Delay-Locked Loop (Delay Line Based)

Phase-Locked Loop (VCO-Based)

U

D

U

D

fREF

fO

fO

fREF

Filter

EE14179


Delay Locked LoopDelay Locked LoopPhasedetect

Chargepump VCDL

FREF∆PH

U

DC VCTRL

FO

REF

OUT

UP

DN

Delay

∆PH

VCTRL

(a)

(b)

(c)

EE14180


DLLDLL--Based Clock DistributionBased Clock Distribution

VCDL

CP/LF

PhaseDetector

VCDL

CP/LF

PhaseDetector

DigitalCircuit•••

DigitalCircuit•••

GLOBAL CLK

jan m. rabaey anantha chandrakasan borivoje nikolićbaccaran/rabaey/chapter10.pdfee141 1 © digital...

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