ee141-fall 2012 digital integrated...
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EE141
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EE141EECS141 1Lecture #17
EE141-Fall 2012Digital Integrated Circuits
Lecture 17CMOS Scaling
EE141EECS141 2Lecture #17
Announcements
Homework #7 due today Project #1 out today, due next Thurs.
Midterm 2 two weeks from today
Let us know ASAP if you still don’t have a project partner
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EE141EECS141 3Lecture #17
CMOS Transistor Scaling
EE141EECS141 4Lecture #17
Goals of Technology Scaling
Make things cheaper: Want to sell more functions (transistors)
per chip for the same money
Or build same products cheaper
Price of a transistor has to be reduced
But also want to be faster, smaller, lower power…
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EE141EECS141 5Lecture #17
Technology Scaling
Benefits of 30% “Dennard” scaling (1974): Double transistor density
Reduce gate delay by 30% (increase operating frequency by 43%)
Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)
Die size used to increase by 14% per generation (not any more)
Technology generation spans 2-3 years
EE141EECS141 6Lecture #17
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
• Fixed Voltage Scaling
• General Scaling
ideal model — dimensions and voltages scaletogether by the same factor S
most common model until 1990’sonly dimensions scale, voltages remain constant
most realistic for today’s situation —voltages and dimensions scale with different factors
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EE141EECS141 7Lecture #17
ScalingL
x
LD
L/S
x/S
LD/S
L
W
L/S
W/S
EE141EECS141 8Lecture #17
Full Scaling (Dennard, Long-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
Area: WL
Cox: 1/tox
CL: CoxWL
ID: Cox(W/L)(VDD-VT)2
Req: VDD/IDSAT
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EE141EECS141 9Lecture #17
Full Scaling (Dennard, Long-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
tp: ReqCL
Pavg: CLVDD2/tp
Pavg/A: CoxVDD2/tp
EE141EECS141 10Lecture #17
Scaling Relationships for Long Channel Devices
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EE141EECS141 11Lecture #17
Full Scaling (Dennard, Short-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
Area: WL
Cox: 1/tox
CL: CoxWL
ID: WCoxvsat(VDD-VT)2/(VDD-VT-EcritL)
Req: VDD/IDSAT
EE141EECS141 12Lecture #17
Full Scaling (Dennard, Short-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
tp: ReqCL
Pavg: CLVDD2/tp
Pavg/A: CoxVDD2/tp
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EE141EECS141 13Lecture #17
Transistor Scaling(Velocity-Saturated Devices)
EE141EECS141 14Lecture #17
Interconnect Scaling
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EE141EECS141 15Lecture #17
Interconnect Length Distribution
From Magen et al., “Interconnect Power Dissipation in a Microprocessor”
SLocal = STechnology
SGlobal = SDie
EE141EECS141 16Lecture #17
Resistance Scaling (local)
W
L
H
Scale W, H, and L:
Rw = ρL/(WH)
Rw α (1/S) / [(1/S) (1/S)]
Rw α S
(R/□ α S)
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EE141EECS141 17Lecture #17
Resistance Scaling (global)
W
L
H
Scale W, H, constant L:
Rw = ρL/(WH)
Rw α 1/[(1/S) (1/S)]
Rw α S2
EE141EECS141 18Lecture #17
Local Wire Scaling (Scenario 1)
Cpp α WL/H Cpp’ α 1/SCfringe α ~L Cfringe’α 1/SRw α L/(WT) Rw’α Stpwire α RwCw tpwire’ const.
Bad news: gates speed up by S…
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EE141EECS141 19Lecture #17
Local Wire Scaling (Scenario 2)
Cpp α WL/H Cpp’ α 1/SCfringe α ~L Cfringe’α 1/SRw α L/(WT) Rw’ const.tpwire α RwCw tpwire’ α 1/S
Better (wire RC tracks inverters), but…
EE141EECS141 20Lecture #17
Scenario 2: Intralayer Capacitance
Cpp,side α LT/D Cpp,side’ const.
• Cpp,side/Length increases Crosstalk, coupling issues get worse
• Aspect ratio limited – eventually have to scale T• Different metal layers have different T
W
L
D W/S
L/S
D/S
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EE141EECS141 21Lecture #17
Global Wire Scaling (Scenario 2)
Cpp α WL/H Cpp’ constCfringe α ~L Cfringe’ ~constRw α L/(WT) Rw’ α Stpwire α RwCw tpwire’ α S
Very bad: wire delay S2 worse than gates
EE141EECS141 22Lecture #17
Modern Interconnect
90nm process
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EE141EECS141 23Lecture #17
Next Lecture
Ratioed and Pass Transistor Logic