18 july 2001 work in progress – not for publication 2001 itrs front end process july 18, 2001 san...

18 July 2001 Work In Progress – Not for Publication

2001 ITRS Front End Process

July 18, 2001

San Francisco, CA


FEP Chapter Scope

• The scope of the FEP Chapter of the ITRS is to define comprehensive future requirements and identify potential solutions for the key technology areas in front-end-of-line IC wafer fabrication processing


FEP Chapter Topics

• Starting Substrate Materials• Surface Preparation• Critical Dimension Etch• MOSFET Isolation, Gate Stack, Doping, and

Contact Requirements– High Performance Logic

– Low Operating Power Logic (new 2001 addition)

– Low Standby Power Logic (new 2001 addition)

• DRAM Trench and Stack Capacitor materials and processes


• Pre-Metal dielectric layers (new)• FLASH memory materials and processes (new)• FeRAM materials and processes (new) • Non-classical double gate CMOS materials and

processes (new)

FEP Chapter Topics


1999 vs 2001 ITRS Technology Nodes1999 vs 2001 ITRS Technology Nodes

2001 2002 2003 2004 20051999 ITRS DRAM 1/2 Pitch (nm) 150 130 120 110 1002001 ITRS DRAM 1/2 Pitch (nm) 130 115 100 90 80

1999 ITRS MPU Physical Gate Length (nm) 100 88 80 70 652001 ITRS MPU Physical Gate Length (nm) 65 53 45 37 32

45 nm gate length was forecasted for year 2008 in 1999 ITRS

32 nm gate length was forecasted for year 2011 in 1999 ITRS

•There has been an unprecedented acceleration in MOSFET gate length scaling! In many instances, FEP processes have not kept pace, resulting in compromised device performance expectations. This is reflected in the 2001 FEP & PIDS requirements and difficult challenges


FEP Near Term Difficult Challenges

For the years up to and including 2007, with DRAM 1/2 Pitch 65nm, and MPU

physical gate length 25nm


Near Term Difficult Challenges

1 New gate stack processes and materials for continued planar MOSFET scaling• Remains the number one FEP priority

2 Critical Dimension and MOSFET effective channel length (Leff ) Control

3 CMOS integration of new memory materials and processes

4 Surfaces and Interfaces; structure, composition, and contamination control

5 Scaled MOSFET dopant introduction and control


Challenge #1 New Gate Stack Processes- Issues

• Extend oxynitride gate dielectric materials to ~0.8-1nm EOT for high-performance MOSFETS

• Introduce and integrate high- gate stack dielectric materials for low operating power MOSFETS

• Control boron penetration from doped polysilicon gate electrodes

• Minimize depletion of dual-doped polysilicon electrodes• Possible introduction of dual metal gate electrodes with

appropriate work function (toward end of period)• Metrology issues associated with gate stack electrical and

materials characterization


YEAR 2001 2002 2003 2004 2005 2006 2007MPU Physical Gate Length (nm) 65 53 45 37 32 28 25MPU Effective Oxide Thickness (nm) 1.4 1.4 1.2 1.0 0.9 0.9 0.8Low Power Effective Oxide Thickness (nm) 2.0 1.8 1.6 1.4 1.3 1.1 1.0Polysilicon Active Dopant Na (per cm3) 1.5E+20 1.5E+20 1.8E+20 2.4E+20 2.6E+20 2.7E+20 3.0E+20

Gate Stack Challenges

Direct tunneling currents limit allowable gate oxide thickness reduction, thereby limiting gate capacitance and gate control over channel charge

Electrical depletion of doped polysilicon results in unwanted parasitic capacitance that limits gate control of channel charge

Earlier “red wall” for low power results from lower allowed tunneling curents


Challenge #2 CD & Leff Control:Issues

• Control of gate etch processes to yield a physical gate length that is smaller than the printed feature size, while maintaining 15% 3- control of the combined lithography and etch processes

• Control of profile shape, line and space width for isolated, as well as closely-spaced fine line patterns

• Control of self-aligned doping introduction process and thermal activation budgets to yield ~ 25% 3- Leff control

• Maintenance of CD and profile control throughout the transition to new gate stack materials and processes

• Metrology


Resist Trim Process Sequence

Photoresist

Hardmask

Gate Poly

Gate Oxide

Substrate

Example150nm

Example100nm

TrimResist

OpenHardmask

EtchGate Poly


Challenge #3 CMOS Integration of New Memory Materials: Issues

• Development & Introduction of very high- DRAM capacitor dielectric layers

• Migration of DRAM capacitor structures from Silicon-Insulator-Metal to Metal-Insulator-Metal

• Integration and scaling of ferroelectric materials for FeRAM

• Scaling of Flash inter-poly and tunnel dielectric layers may require high-

• Limited temperature stability of high- and ferroelectric materials challenges CMOS integration


Technology Migration of Stack Capacitor

130nm 100nm 80nm 65nm

MIS MIM MIM MIM

TiN

Ta2O5

Poly Si

Metal

Barrier MetalBST

Perovskite

epi-BST


Selection from DRAM Stack Capacitor Roadmap

Year of First Product ShipmentTechnology Node

2001130 nm

2002 20032004

90 nm2005 2006

200765 nm

Minimum feature size (nm) 130 115 100 90 80 70 65 DRAM Product (A) 4GCell size factor a (B) 8. 0 8. 0 6.0 6.0 6.0 6.0 6. 0Cell size [um2] (C) 0. 14 0. 11 0. 06 0.049 0.038 0.029 0. 03

=0. 26*0. 52 =0. 23*0. 46 =0. 2*0. 3 =0.18*0.27 =0.16*0.24 =0.14*0.21 =0. 13*0. 2Storage Node size [um2] (D) 0. 051 0. 040 0. 020 0.016 0.013 0.010 0. 008

=0. 13*0. 39 =0. 115*0. 35 =0. 1*0. 2 =0.09*0.18 =0.08*0.16 =0.07*0.14 =0. 065*0. 13

CapacitorStructure

Cyl i nderMI S

Ta2O5

Cyl i nderMI S

Ta2O5

PedestalMI M

Ta2O5 (Ref. U)

PedestalMI M

Ta2O5 (Ref. U)

PedestalMI MBST

PedestalMI MBST

PedestalMI MBST

Dielectric Constant 22 22 50 Ref. U 50 Ref. U 250 300 450SN Height H [um] 0.9 0.9 0.9 0.9 0.65 0.53 0.38

Cylinder Factor (E) 1. 5 1. 5 1. 5 1. 5 1. 0 1. 0 1. 0Roughness Factor 1. 0 1. 0 1. 0 1. 0 1. 0 1. 0 1. 0

Total Capacitor Area [um2] 1. 48 1. 30 0. 87 0. 72 0. 32 0. 23 0. 16Structural Coefficient (F) 10. 9 12. 3 14. 5 14. 8 8. 5 7. 9 6. 2

teq@25fF [nm] (G) 2. 0 1. 80 1. 20 1. 00 0. 45 0. 32 0. 22t phy.@25fF [nm] (H) 5. 9 4. 5 15. 3 12. 8 28. 7 24. 7 25. 0

512M 1G 2G


FLASH Memory

Source Drain

Floating Gate

Control Gate

Tunnel Oxide

Interpoly Oxide

Operating Principle: Charge stored on the floating gate (a bit) , will determine whether a voltage applied to the control gate turns the MOSFET on or off. (read)


FLASH RoadmapYear 2001 2002 2003 2004 2005 2006 2007Technology Node 130 nm 115 nm 100 nm 90 nm 80 nm 70 nm 65 nmDRAM half pitch (nm) 130 115 100 90 80 70 65MPU/ASIC half pitch (nm) 160 130 115 100 90 80 70Flash technology node (nm) 150 130 115 100 90 80 70Flash NOR cell size (F2) 10-12 10-12 10-12 11-14 11-14 11-14 11-14Flash NAND cell size (F2) - SLC/MLC 5.5 5.5 4.5 4.5 4.5 4.5/2.3 4.5/2.3Flash NOR typical cell size (m2) 0.248 0.186 0.145 0.125 0.101 0.080 0.061Flash NOR Lg-stack (physical- m) 0.29-0.31 0.25-0.27 0.22-0.24 0.21-0.23 0.2-0.22 0.2-0.22 0-19-0.21Flash NOR highest W/E voltage (V) 8-10 8-10 8-10 8-10 7-9 7-9 7-9Flash NAND highest W/E voltage (V) 19-21 18-20 18-20 18-20 18-20 17-19 17-19Flash NOR I_read (A) 36-44 35-43 34-42 33-41 31-39 28-36 29-37Flash Coupling Ratio 0.65-0.75 0.65-0.75 0.65-0.75 0.65-0.75 0.65-0.75 0.65-0.75 0.6-0.7Flash NOR tunnel oxide thickness (nm) 9.5-10.5 9.5-10 9-10 9-10 8.5-9.5 8.5-9.5 8.5-9.5Flash NAND tunnel oxide thickness (nm) 8.5-9.5 8.5-9 8-9 8-9 8-9 7.5-8 7.5-8Flash NOR interpoly dielectric thickness (nm) 13-15 12-14 11-13 11-13 10-12 9-11 9-11Flash NAND interpoly dielectric thickness (nm) 14-16 13-15 12-14 12-14 12-14 11-13 10-12Flash endurance (erase/write cycles) 1E5 1E5 1E5 1E5 1E5 1E5 1E5Flash nonvolatile data retention (years) 10 10-20 10-20 10-20 10-20 10-20 10-20Flash max Nr. of bits per cell (MLC) 2 2 4 4 4 4 4

Issues: Scaling of the NOR L gate

Tunnel oxide must be thick enough to assure charge retention, but thin enough to allow lower write voltage

Interpoly oxide must be thick enough to assure charge retention bu thin enough assure almost constant coupling ratio, making charge retention difficult.


Challenge #4 Surfaces & Interfaces: Issues

• Contamination, composition and structure control of channel/gate dielectric interface

• Contamination, composition and structure control of gate dielectric/gate electrode interface

• Interface control of DRAM capacitor structures

• Maintenance of surface and interface integrity through full-flow CMOS process

• Statistically significant characterization of surfaces having extremely low defect concentrations– Starting materials

– Pre-gate cleans


Pre-Gate Clean Requirements

Year of First Product ShipmentTechnology Node

2001 130nm

2002 2003 2004 90nm

2005 2006 2007 65nm

Driver

DRAM 1/2 Pitch (nm) 130 115 100 90 80 70 65 D ½MPU/ASIC Physical Gate Length (nm) 65 53 45 37 32 30 25 M

Wafer diameter (mm) 300 300 300 300 300 300 300 D ½, M

Wafer edge exclusion (mm) 3 3 1 1 1 1 1 D ½, M

Front surface particles

Critical Particle Size (nm) (A) D ½

Particle Size For Measurement (nm) (A)

Particles (cm–2) (B) D ½

Particles (#/wafer) (C) M

Back surface particle size (nm), latex sphere equivalent (D) D ½, M

Particles (cm–2) (E) MPU

Particles (#/wafer) (F) MPU

Critical surface metals (E+9 ions/cm2) (G) MPU

Mobile ions (E+10 ions/cm2) (H) D ½

Organic contamination (E+13 C at/cm2) (I) MPU

Surface Roughness nm (J) D ½, M

Water Marks (#/wafer) (K) D ½

Surface Oxygen ( O at/cm2) (L) D ½, M

Table 33 2001 Near Term Surface Preparation Technology Requirements*


Challenge #5 Scaled MOSFET Doping: Issues

• Doping and activation processes to achieve source/drain parasitic resistance that is less than ~16-20% of ideal channel resistance (=Vdd/Ion)

• Control of parasitic capacitance to achieve less than ~19-27% of gate capacitance with acceptable Ion and short channel effect

• Achievement of activated doping concentration greater than solid solubility levels in dual doped polysilicon gate electrodes

• Formation of continuous self-aligned silicon contacts over shallow source/drain regions

• Metrology issues associated with 2-D doping profiling


Scaled MOSFET Parasitic Resistance Elements

Spreading and Accumulation resistances

Extension Sheet Resistivity

Contact Junction Sheet Resistivity

Contact Resistivity


Parasitic Capacitance Elements

Gate/Drain Overlap Capacitance

Halo/Extension Junction Capacitance

Contact Junction Capacitance


PIDS Forecasted High Performance MOSFET Parasitic Elements

YEAR 2001 2002 2003 2004 2005 2006 2007MPU Physical Gate Length (nm) 65 53 45 37 32 28 25Parasitic Capacitance % of Gate Cap. 19% 23% 24% 25% 27% 28% 27%Parasitic Resistance % of Channel Res. 16% 16% 17% 18% 19% 19% 20%Delay (Cgate*Vdd/Id-NMOS) Picoseconds 1.63 1.34 1.16 0.99 0.96 0.79 0.66Note: Cgate includes parasitic capacitance


FEP Long Term Difficult Challenges

For the years beyond 2007, with DRAM 1/2 Pitch < 65nm, and MPU

physical gate length <25nm


Long Term FEP Challenges

1 Continued scaling of planar CMOS devices2 Introduction and CMOS integration of non-

standard double-gate MOSFET devices• These devices may be needed as early as 2007• Increased allocation of long term research resources

would be highly desireable

3 Starting material alternatives beyond 300mm4 New memory storage cells, storage devices and

memory architectures5 Surfaces and Interfaces; structure, composition,

and contamination control


Challenge #1- Continued Planar MOSFET Scaling; Issues

• Higher- gate dielectric materials• Dual metal gate electrodes with appropriate work

function• Possible single drain MOSFET’s with elevated

contacts• CMOS Integration consistent with higher-

temperature constraints• CD and Leff control• Chemical, electrical, and structural

characterization


Challenge #2 Dual-Gate MOSFETS: Issues

• Selection and characterization of optimum device types

• Device performance and reliability characterization

• CMOS Integration with other devices, including planar MOSFETS

• Introduction, characterization, and production hardening of new FEP unit processes

• Metrology


Challenge #3 Starting Material Alternatives Beyond 300mm: Issues

• Future productivity enhancement needs dictate the requirement for a next generation, large substrate material

• Historical trends suggest that the new starting material have nominally 2X present generation area, e.g. 450mm

• Cost-effective scaling of the incumbent Czochralzki crystal pulling and wafer slicing process is questionable

• Research is required for a cost-effective substrate alternative


Challenge #4 New Memory Devices; Issues

• Scaling DRAM storage cells beyond 6F2 and ultimately to 4F2

• Possible further scaling of Flash memory interpoly- and tunnel-oxide thickness

• FeRAM storage cell scaling

• Introduction of new memory types and storage concepts


Challenge #5 Surface & Interface Control; Issues

• Achievement and maintenance of structural, chemical, and contamination control over surfaces and interfaces that may be horizontally or vertically oriented relative to the chip surface

• Statistically significant characterization of surfaces and interfaces having extremely low defect counts

• Metrology and characterization of surfaces and interfaces that may be horizontally or vertically oriented relative to the chip surface.


FeRAM Roadmap

Here’s a newcomer…

July 2001 FEP & PIDS ITWG

S. Kawamura (FEP)


Why FeRAM?

• FeRAM has the following outstanding features: – Non-volatility– Low voltage (power) operation– High speed– High Endurance– Capable of high levels of integration

• cell size similar to DRAM


FeRAM Roadmap (version 7.0)

Year of First Product Shipment 2000 2001 2002 2003 2004 2005 2007 2010 2013 2016

Technology Node 180nm 130nm 115nm 100nm 90nm 80nm 65nm 45nm 32nm 22nm

1) Feature Size (um): F 0.5 0.5 0.35 0.25 0.18 0.18 0.13 0.1 0.07 0.05

2) FeRAM Generation (MassProduction)

Standard Memory (bit) 256Kb 1Mb 4Mb 16Mb 64Mb 128Mb 256Mb 1Gb 4Gb 16Gb

Embedded Memory (Byte)8KB

(64Kb)32KB

(256Kb)128KB(1Mb)

512KB(4Mb)

2MB(16Mb)

4MB(32Mb)

8MB(64Mb)

32MB(256Mb)

128MB(1Gb)

512MB(4Gb)

3) Access time (ns) 120 100 80 65 40 30 20 10 8 6

4) Cycle time (ns) 180 160 130 100 70 50 32 16 12 10

5) Cell Area Factor a 81 60 40 24 16 10 10 8 8 8

6) Cell size (um2) 20.25 15.000 4.900 1.500 0.518 0.324 0.169 0.080 0.039 0.020

7) Total cell area (mm2) forStandard Memory

5.31 15.73 20.55 25.17 34.79 43.49 45.37 85.90 168.36 343.60

8) Total cell area (mm2) forEmbedded Memory

1.33 3.93 5.14 6.29 8.70 10.87 11.34 21.47 42.09 85.90

9) Projected Capacitor size (um2) 3.00 2.00 0.98 0.50 0.26 0.13 0.07 0.03 0.015 0.0075

10) Capacitor area (um2) 3.00 2.00 0.98 0.50 0.26 0.13 0.09 0.08 0.06 0.05

11) Cap area/Proj Cap size 1.00 1.00 1.00 1.00 1.00 1.00 1.34 2.53 4.06 6.37

12) Height of Bottom Electrode/F(for 3D Capacitor)

n/a n/a n/a n/a n/a n/a 0.17 0.57 1.15 2.01

13) Capacitor Structure planar planar stack stack stack stack 3D 3D 3D 3D

14) 2T2C or 1T1C 2T2C 2T2C 2T2C 1T1C 1T1C 1T1C 1T1C 1T1C 1T1C 1T1C

15) Vdd (Volt) 3.3 3.3 3.3 2.5 1.8 1.5 1.2 1.0 0.7 0.7

16) Minimum Switching ChargeQsw (uC/cm2) @Vdd

3.0 4.4 7.1 11.2 19.7 34.5 40.0 40.0 40.0 40.0

17) Minimum Switching Chargeper cell (fC/cell) @Vdd

88.5 88.5 69.8 55.8 51.2 44.8 36.1 30.3 23.9 19.1

18) Retention @85C (Years) 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years

19) Fatigue with assuringRetention

1.0E+10 1.0E+12 1.0E+13 1.0E+14 1.0E+15 ＞1.0E16 ＞1.0E16 ＞1.0E16 ＞1.0E16 >1.0E16

FeRAM Ferroelectric Materials Potential Solutions PZT:Pb(Zr,Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi,La)4Ti3O12

Ferroelectric Materials PZT*, SBT PZT, SBT, New Materials (BLT, etc.)

Deposition Methods PVD, CSD# PVD, CSD, MOCVD MOCVD, New Methods

*) Since the PZTcontains the lead, it may pose a problem from the viewpoint of ESH.

#) Chemical Solution Deposition


Assumptions (1)

Feature Size: 0.35m expected to be available in early 2002, 0.25m in 2003. x0.7 every 1-3 years.Memory Capacity: Intend to be aggressive to establish FeRAM market. x4 every 1-3 years.



1) Feature Size (um): F 0.5 0.5 0.35 0.25 0.18 0.18 0.13 0.1 0.07 0.05




Assumptions (2)

Cell Size: planar stack (x 0.6) 2T2C 1T1C (x 0.6)

Switching Charge Qsw: Constant Vbitline=140mV for sensingQsw=Cbitline x Vbitline

(Stack)

PlateFerro. FilmStorage Node

(Planar)

Storage NodeFerro. FilmPlate


Evolution in Cell Structure

Planar Cell

Stack Cell (COB)

Stack Cell (CUB)

3D CapacitorBit Line

Word LineCapacitor

W, etc.Ferroelectic FilmPt, IrO2, etc.

Metal

Bit Line(Polycide, W, etc.)

Bit Line Bit Line(Polycide, W, etc.)

Al

(Polycide, W, etc.)


1.00E-01

1.00E+00

1.00E+01

1.00E+02

1.00E+03

1.00E+04

1.00E+05

1.00E+06

1.00E+07

2000 2005 2010 2015 2020

DRAMFeRAM

FeRAM vs. DRAM

Year

Cap

acit

y (M

b)

Giga scale integration will be available with a 3D capacitor

Plate

Ferro. Film

Storage Node

Year 2001 2002 2003 2004 2005 2007 2010 2013 2016DRAM 2Gb 2Gb 4Gb 4Gb 8Gb 16Gb 32Gb 64Gb 128GbFeRAM 1Mb 4Mb 16Mb 64Mb 128Mb 256Mb 1Gb 4Gb 16Gb

1T1C3D


Vbitline Estimation

Based on DRAM roadmap, Vbitline estimated to be 140mV.Feature Size (um): F 0.5 0.35 0.25 0.18 0.13 0.1 0.07 0.05

Storage Capacitance Cs [fF/cell] 25 25 25 25 25 25 25 25

Vdd [V] 3.3 3.3 2.5 1.8 1.5 1.2 0.9 0.6

Charge Qs [fC/cell]: Cs*Vdd 82.5 82.5 62.5 45 37.5 30 22.5 15

F^2/3 0.630 0.497 0.397 0.319 0.257 0.215 0.170 0.136

a) F^2/3 (Normalized) 1@ 0.18um 1.98 1.56 1.24 1.00 0.80 0.68 0.53 0.43

b) cf. F^2/3 (Normalized, ITRS1999) 1.98 1.56 1.24 1 0.79 0.62 0.49 0.39

c) Cbitline [fF], [email protected] 632.3 498.5 398.3 320.0 257.6 216.3 170.5 136.2

d) deltaVbitline [mV]: Qs/Cb 130.5 165.5 156.9 140.6 145.6 138.7 132.0 110.1

b) Values from ITRS 1999. Not used for calculation here.c) 320*a)d) Qs divided by c).

About 140mV


Qsw and Capacitor Structure

FeRAM Requirements

Feature Size (um): F 0.5 0.35 0.25 0.22 0.2 0.18 0.13 0.1 0.07 0.05

F^2/3 0.630 0.497 0.397 0.364 0.342 0.319 0.257 0.215 0.170 0.136

a) F^2/3 (Normalized) 1@ 0.18um 1.98 1.56 1.24 1.14 1.07 1.00 0.80 0.68 0.53 0.43

b) cf. F^2/3 (Normalized, ITRS1999) 1.98 1.56 1.24 n/a n/a 1 0.79 0.62 0.49 0.39

c) Cbitline [fF], [email protected] 632.3 498.5 398.3 365.8 343.3 320.0 257.6 216.3 170.5 136.2

d) deltaVbitline [mV]: Constant 140.0 140.0 140.0 140.0 140.0 140.0 140.0 140.0 140.0 140.0

e) minimum Qsw [fC]: c)*d) 88.5 69.8 55.8 51.2 48.1 44.8 36.1 30.3 23.9 19.1

Cap Area [um2] @2Pr=20uC/cm2 0.443 0.349 0.279 0.256 0.240 0.224 0.180 0.151 0.119 0.095



Projected Capacitor Size[um2]3.00 0.98 0.50 0.39 0.32 0.13 0.07 0.03 0.015 0.0075

b) Values from ITRS 1999. Not used for calculation here.c) 320*a)d) Constant.e) Qsw=Cbitline*deltaVbitline. 3D Capacitor

Qsw/2Pr=Required Capacitor Area> Projected Capacitor Size3D.


In order to enjoy (Lambs)

“The Silence of the (other) RAM’s,”

reliability comes first to be focused on,

followed by application and cost.

Issues (1)


Issues (2)

*) Since the PZT contains the lead, it may pose a problem from the viewpoint of ESH.#) Chemical Solution Deposition

Ferroelectric materials:Should be stable under thermal budgets.Usually being used with some dopants.

PZT:Pb(Zr,Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi,La)4Ti3O12



1) Feature Size (um): F 0.5 0.5 0.35 0.25 0.18 0.18 0.13 0.1 0.07 0.05



FeRAM Ferroelectric Materials Potential Solutions

Ferroelectric Materials PZT*, SBT PZT, SBT, New Materials (BLT, etc.)

Deposition Methods PVD, CSD# PVD, CSD, MOCVD MOCVD, New Methods


Fatigue:More than 1E+15 cycles are required to compete with SRAM and DRAM. Practical testing is critical.

Issues (3)



1) Feature Size (um): F 0.5 0.5 0.35 0.25 0.18 0.18 0.13 0.1 0.07 0.05



19) Fatigue with assuringRetention

1.0E+10 1.0E+12 1.0E+13 1.0E+14 1.0E+15 ＞1.0E16 ＞1.0E16 ＞1.0E16 ＞1.0E16 >1.0E16


Application:Limited to small capacity (embedded) memory for RFID, Smart Card, etc.Some “killer applications” should be needed to establish FeRAM market.

Cost:Not competitive due to large cell size. 1T1C and 3D capacitor are mandatory to reduce cost.

Issues (4)

18 july 2001 work in progress – not for publication 2001 itrs front end process july 18, 2001 san...

Documents

gate capacitance

nm gate length

gate stack electrical

fep processes

control slide

mosfet gate length scaling

nm slide

gate control of channel