2004 symposium on vlsi circuitssscs.ieee.org/images/files/newsletter_archive/sscs...t he symposium...

The Symposium on VLSI Cir-cuits will meet 17–19 June 2004at the Hilton Hawaiian Village,

Honolulu, Hawaii. This year the tech-nical program committee reviewed 329submissions to the conference andchose 108 papers for inclusion in thetechnical program. The unusually largenumber of top-quality technicalpapers has resulted in a technical con-ference that will be bigger and betterthan ever. Papers describing new andinnovative demonstrations of leading-

edge concepts dominate every ses-sion. The three days of technical pre-sentations and the informal eveningrump sessions are a companion con-ference to the Symposium on VLSITechnology, which precedes it at thesame hotel. The one-day overlap inthe schedules for the Technology andCircuits meetings features a ShortCourse as well as a joint rump session.

The scope of the Circuits Sympo-sium covers all aspects of VLSI cir-cuits, such as:

• Digital, analog, and mixed digi-tal-analog circuits such asprocessors, ASICs, A/D and D/Aconverters, and interface circuits

• Memory circuits such as staticmemory, nonvolatile memory,cache memory, dynamic mem-ory, and new concepts in mem-ories based on quantummechanical effects, magnetism,and polymers

• System architecture, circuits,and building blocks for net-working applications

• Circuits, functional blocksusing quantum dots, MEMS,and sensors

• Circuits for wireless and wire-line communications

The emphasis is on circuit design.Papers are considered on the basis oforiginality and quality. Implementa-tion in a semiconductor chip andmeasured results are not mandatory:they are required only when feasibil-ity of the presented circuit is not clearby simulations alone, as in the case ofmost analog submissions. It is under-stood that papers in new areas arelikely to contain less quantitativeevaluations than those in more estab-lished areas.

About the VenueHilton Hawaiian Village2005 Kalia Road, Honolulu, HI, USATelephone: 1-808-949-4321Fax: 1-808-947-7898

The Hilton Hawaiian Village is alush 22-acre resort on Waikiki’s pre-mier beach, conveniently located nearIolani Palace, Pearl Harbor, WaikikiAquarium, Honolulu Zoo, and BishopMuseum. Guests can enjoy snorkeling,sailing, surfing, windsurfing, scubadiving, and more. Atlantis Submarinesoffers dives daily. Other amenitiesinclude exceptional dining at Bali-by-the-Sea, Golden Dragon, and 13 otherrestaurants and lounges, plus a busi-ness center. The Rainbow ExpressChildren’s Program provides super-vised activities for young people.

Technical HighlightsThis year there are several interestingpapers in areas that are at the fore-front of integrated circuit design.Among the highlights of this confer-ence is a “Mixed signal rotator/shifterfor 8-GHz Intel Pentium® 4-integercore” from Intel, which further dis-closes the double-pumped low-volt-age swing integer ALU. Samsungauthors present “64-Mb mobilestacked single-crystal Si SRAM(S3RAM) with selective dual pump-ing scheme (SDPS) and multi-Cellburn-in scheme (MCBS) for high-density and lower-power SRAM.” Inwireline technology, Stanford Uni-versity presents a “20-Gb/s 0.13-micron CMOS serial link transmitterusing an LC-PLL to directly drive theoutput multiplexer.” Authors fromInfineon report the highest speed 6-bit ADC to date with reasonable

IEEE Solid-State Circuits Society Quarterly Newsletter

Volume 9Number 2April 2004

Solid-State Circuits Society Newsletter 1

2004 Symposium on VLSI Circuits . . .1

JSSC Best Paper Awarded to Shrivani, Su and Wooley . . . . . . . . . . . . . . . .3

Building a Line Card on a Chip: WhyMore Interaction is Needed Between Design and EDA . . . . . . . . . . . . . . .4

Upgrade to IEEE Xplore: JSSC Article theOne-Millionth Posted . . . . . . . . . . . .5

2004 RFIC Symposium . . . . . . . . . . . .6

Congratulations New Senior Members 7

SSCS IEEE Fellows of 2004 . . . . . . . . .8

Fourth IEEE Asia-Pacific Conference inFukuoka, Japan 4-5 August 2004 . .9

SSCS —Relevant to Industry . . . . . . .10

Bangalore Named SSCS Outstanding Chapter for 2003 . . . . . . . . . . . . . .11

Chapters are Volunteer Powered — the Bangalore Chapter Case Study . . . .12

Nine to One, SSCS Members Who Try Chapter Events Like Them . . . . . . .13

SSCS AdCom Reports . . . . . . . . . . . .14

Conference Digital Library . . . . . . . .14

SSCS Events Calendar . . . . . . . . . . .15

2004 Symposium on VLSI Circuits

IN

Continued on page 2

April 2004 • Volume 9 – Number 22

power consumption, a 4-GS/s 6-bitflash ADC in 0.13-micron CMOS.

Invited SpeakersInvited papers are always a high pointof the Symposium and focus on bothtechnical information and businessimplications of technology change byleaders in their fields. This year, ChrisDyer from Compact Power describeshis work on “Fuel cells and portableelectronics.” Touma Fujikawa of Toy-ota Motors presents “ Semiconductortechnologies support new generationhybrid cars.” In the following talk,Ryo Imura of Mu Solutions VentureCompany, Hitachi, discusses “Theworld’s smallest RFID Mu-chip, bring-ing about new business andlifestyles.” Finally, Albert Theuwissenof Dalsa presents “Image-processingchain in digital still cameras.”

Rump SessionsEach evening rump session is orga-nized around a hot controversialtopic, and experts are recruited topresent their divergent views. Allaspects of the issue are explored, anda spirited discussion ensues; activeaudience participation is encouraged!This year the rump session topics forthe Circuit Symposium are

• Analog CAD: Computer-aideddesign or computer-accelerateddisaster?

• On-chip 6T SRAM: Forever orbe fired?

• Limitations of low-FO4 designsThese rump session topics give a

good idea of controversies plaguingthe industry. Will the 6T memory celllast forever or is there something elseon the horizon? Is there such a thingas analog CAD, or is it a disaster? What

is the circuit limitation on the fan-outnumber of four-gate delays in a clock?All these issues will be debated at therump sessions by the experts, and wehope that you will enjoy them.

About the SymposiaThe VLSI Symposia began in 1981 withthe Symposium on VLSI Technology,an international conference on currentsemiconductor research and develop-ment. It continues to be sponsored bythe IEEE Electron Devices Society,IEEE Solid-State Circuits Society, andthe Japan Society of Applied Physics incooperation with the Institute of Elec-tronics, Information, and Communica-tion Engineers of Japan. Its intent is toprovide an intense but limited-sizeforum for Japanese and U.S.researchers and engineers to moreopenly discuss and exchange newideas and directions. The Symposiumon VLSI Technology has alternatedeach year between sites in the UnitedStates and in Japan.

In 1987 the first Symposium on VLSICircuits was held in conjunction withthe Technology Symposium in recog-nition of the growing interest in pro-viding the same small but intense andopen forum for discussing circuit andsystem implementations. For manyreasons, these meetings haveremained linked to provide opportuni-ties for technologists and circuit andsystem designers to interact with oneanother. These interactions are aug-mented with workshops, invitedspeakers, and several evening rumpsessions. The meetings are organizedto give participants substantial time tointeract at breaks, meals, and numer-ous evening events.

Overlap DayAnother special feature of the Sympo-sium is the one-day overlap in theschedules for the Technology and Cir-cuits meetings. This is an excellentopportunity to meet with members ofthe opposite discipline to share experi-ences, issues, and ideas for futureimprovements. In addition there is ajoint rump session organized by mem-bers of both the circuits and technolo-gy committees. This year’s topic is

President:Stephen H. LewisUniversity of CaliforniaDavis, [email protected]: +1 530 752 8428

Vice President:Richard C. JaegerAlabama Microelectronics CenterAuburn University, AL

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:David HodgesUniversity of California Berkeley, CA

Past President:Charles G. SodiniMassachusetts Institute of TechnologyCambridge, MA

Other Representatives:Representative to Sensors Council

Darin YoungRepresentative from CAS to SSCS

Georges GielenRepresentative to CAS from SSCS

Ian Galton

Newsletter Editor:Lewis TermanIBM Somers [email protected]: +1 914 766 2814

Elected AdCom Members at LargeTerms to 31 Dec. 04:Gerhard FettweisRichard C. JaegerDavid A. JohnsTakayasu SakuraiNeil Weste

Terms to 31 Dec. 05:Anantha ChandrakasanJohn CorcoranWanda GassTeresa MengJan Sevenhans

Terms to 31 Dec. 06:Brian AcklandGary BaldwinTom LeeJan RabaeyJan Vander Spiegel

Chairs of Standing Committees:Awards Richard C. JaegerChapters Jan Van der SpeigelEducation CK Ken YangMeetings Anantha ChandrakasanMembership Teresa MengNominations Charles G. SodiniPublications Richard C. Jaeger

For detailed contact information, see the Society Web page: www.sscs.org

For questions regarding Society business, contact the SSCS Executive Office.

Contributions for the July 2004 issue of the newsletter must be received by 2 May 2004 at the SSCS Executive Office.

Anne O’Neill, Executive Director Tel: +1 732 981 3400IEEE SSCS Fax: +1 732 981 3401445 Hoes Lane Email: [email protected], NJ 08854

IEEE Solid-State Circuits Society AdCom

Continued from page 1

2004 Symposium on VLSI Circuits


“What’s beyond the planar MOSFET?”

VLSI Circuits Short CourseDr. Ajith Amerasekera of TexasInstruments and Dr. MasayukiMizuno of NEC have organized an

excellent one-day Short Course onWednesday, 16 June 2004. Thetopic is “Interfaces—Getting dataon and off high-performance ICs.”The agenda includes talks by notedexperts representing the entire

spectrum of the industry.

Further InformationFor registration and other informa-tion, visit the VLSI Symposia homepage at: www.vlsisymposium.org

The Best Paper for 2002 in theJournal of Solid-State Circuitsis “A CMOS RF power ampli-

fier with parallel amplification forefficient control,” by Alireza Shir-vani, David K. Su, andBruce A. Wooley, whichappeared in the Juneissue.

This paper is an out-standing example of theconvergence of circuit andmicrowave design. Itcombines insight fromtransmission lines with thelow cost and high densityof CMOS devices to getthe best of both worlds.The result is a CMOSradio-frequency (RF)power amplifier that usesparallel amplification toachieve high efficiency over a broadrange of output power.

The evaluation of one of theexperts selecting the best paperfrom many superb candidates startswith “I love this paper...”. When atechnical paper achieves this kind ofaffection there is no doubt that it isthe best of the best.

Section I begins by introducingthe challenge of the majority of mod-ern telecommunication protocolsthat require the transmitter power tobe adjusted over a wide range.

“This feature, commonly referredto as power control, ensures thatadequate power is received by thebase station, while saving power byreducing the transmitted powerwhen the maximum transmittedpower is not required thereby reduc-ing the potential interference inother channels. Many wireless net-works require that the transmittedpower be adjustable over a range as

wide as 20 dB. The traditionalapproach to power control is toadjust the output power by varyingthe bias conditions in the outputstage of the power amplifier, by

adjusting the bias levels in the stagethat drives the output stage, or byvarying the supply voltage. Howev-er, if a fixed matching network isused at the output, the power ampli-fier can be optimized only for a spe-cific operating condition in terms ofthe bias conditions and the supplyvoltage. Any deviation from thisoptimum results in degraded powerefficiency.

“The paper introduces a poweramplifier architecture that mitigatesthe efficiency drop at lower powerlevels through parallel amplification.The proposed architecture employsthree unit amplifiers, the outputs ofwhich are binary weighted and com-bined in a power-combination net-work implemented using quarter-wavelength transmission lines. Thecapability to turn off each individualunit amplifier, with no penalty onpower dissipation, is provided by theaddition of pMOS shorting switches.

An experimental prototype of theproposed amplifier has been integrat-ed in 0.25-mm CMOS technology andprovides a power adjustment rangeof 7–304 mW. Tested with a continu-

ous-wave (CW) signal, theamplifier achieves a maxi-mum power-added efficien-cy (PAE) of 49 % and main-tains a PAE greater than 43%over 70% of the outputpower range at 1.4 GHz.The amplifier operates froma 1.5-V supply and provideseight distinct levels of out-put power.

“A parallel architectureprovides high efficiency byreducing the current levelsin individual branches,which is especially impor-tant in low-voltage applica-

tions. By subdividing the power rangeinto separate regions that are handledby parallel amplifiers, these amplifierscan be optimized for different sectionsof the power range, resulting in highefficiency over a much wider range ofoutput power than can be achievedwith a single power amplifier.”[Excerpted from the paper]

Section II describes the architec-ture of the proposed amplifier. Anoverview of various power amplifiertopologies and the merits of class-Famplifiers are presented, followed byan introduction to the power-combi-nation and parallel-amplificationarchitectures. Section III describesthe design and implementation of theproposed architecture. Experimentalresults for the integrated prototypeare presented in Section IV, and Sec-tion V considers the possibility ofintegrating the power-combining net-work on the same die as the parallelamplifiers.

SSCS President, Steve Lewis, presents the JSSC Best PaperAward to the authors, from left to right: Bruce A. Wooley, DavidK. Su, and Alireza Shirvani.

JSSC Best Paper Awarded to Shrivani, Su and Wooley

As the telecommu-nications industryemerges from the

downturn, the focus is ondeveloping new revenue-generating products and ser-vices with minimal capitalexpenditure. One way to dothis is to provide higher lev-els of integration togetherwith increased functionalityin high-density communica-tion SOCs.

For example, with 90-nm technolo-gy we are approaching the pointwhere all the functionality of an OC48router line card could be integratedonto a single chip. These routers areplaced at the edge of the core or metroinfrastructure to form a bridge betweenthe synchronous telecom world andthe TCP/IP-based world of enterprisedata networking. Integrating function-ality in this way has obvious advan-tages in terms of cost, power, andoverall footprint but presents somemajor design challenges.

A primary challenge faced by SOCdesigners is integrating all these func-tions onto the same die. The line cardrequires digital logic, DRAM, and pos-sibly high-speed analog circuitry at thefront end. Other SOC opportunitiesmight include RF and Flash/EEPROM.

One solution is to develop modulartechnologies that allow designers tomix and match different processoptions according to the needs of thedevice, for example, embeddedDRAM or BiCMOS. The barrier withthis approach is cost because of theincreased number of mask levelsrequired, even though some of themmay be applied only to a small portionof the overall chip. A second approachis to drive toward an all-CMOS solu-tion. But that leads to compromises inboth analog and digital performanceand proves more difficult as weapproach 90-nm line widths.

An alternative to the monolithicapproach is multi-chip modules(MCM) or System In a Package (SIP).This technology has been “waiting in

the wings” for many years,and is finally gaining realtraction. SIPs allow moreinterconnect options (nolonger limited by packageI/O), improved perfor-mance (lower parasitics),reduced power, and thepossibility of efficientlycreating a family of prod-ucts from a small numberof die. In the case of theline card, one could create

a family of solutions by including dif-ferent numbers of DRAM and SRAMdie together with some standard phys-ical layer interfaces.

Another challenge is encounteredwith EDA and the lack of tools foreffectively integrating back-end silicondesign with substrate and packagedesign. We need modeling and back-end design tools that perform pack-age-level place and route, and perfor-mance analysis, taking into accountsubstrate and package parasitics. Atthe highest levels, we need a designflow that sees a die not so much as acomplete solution, but rather as apiece of IP to be incorporated into anoverall system solution.

Software must be able to accom-modate a world of changing proto-cols, standards, and market trends—including protocols and functionalitynot yet thought of, requiring softwareprogrammability. In addition, multipleembedded processors, including light-weight RISC and DSP cores and pack-et processing engines, will play anincreasingly important role in thedesign of these systems. However, sys-tem designers have consistentlyshown that they will not tolerateexplicit multiprocessor programmingenvironments. What is required is asoftware development environmentthat presents a true single-threaded(application specific, if necessary) pro-gramming model to the designer.

Here again, there is a tool gap thatneeds to be addressed. We need tobring together the best hardware andsoftware design tools to create a seam-

less design environment where thebest software tool developers are cre-ating the right programming model forspecific application environments. Andwe need a front-end design processthat allows true hardware/software co-design in which implementation deci-sions are delayed to accommodate amore complete exploration of theavailable design space.

Another challenge is managing thesheer cost of design. A complex ASSP,such as the line card on a chip, canconsume 50–100 staff years of R&Dinvestment. That is why we must findways to get more effective reuse fromour designs, where components canbe reused by essentially the samedesign team in future products/gener-ations. But reuse needs to encompassmuch more than just RTL, which rep-resents only about 25 percent of theR&D investment. In order to signifi-cantly reduce design costs, we need tofind ways to also reuse our efforts inverification, software development,and in the back end.

Architectural platforms are oneapproach to reducing this designeffort. Such a platform may consist ofprocessing modules, buses, memory,and I/O interfaces along with a well-defined interconnect scheme. It alsomay mean a standardized floor planand verification suite, along with amultilevel simulation platform thatallows one to easily transition fromsystem to RTL to verification to soft-ware development models. In addi-tion, we need new design rules andscripts built around these platformconcepts that simplify the process ofsetting up reusable components with-out overly burdening the originaldesigner.

Although the challenges in buildingcomplex SOCs are formidable, theyare by no means insurmountable. Themost effective approach for addressingthese issues is for the EDA and designcommunities to work together in cre-ating new tools and methodologiesthat can deal with increasing systemand design complexity while taking


Building a Line Card on a Chip: Why More InteractionIs Needed Between Design and EDA

Bryan Ackland


into account the limitation of deep-submicron CMOS. Conferences andtrade shows provide the critical forumfor these types of interactions.

At this year’s 41st Design Automa-tion Conference (DAC) in San Diego,California, 7–11 June, EDA vendorsand designers will be discussing these

issues in depth and dialogue will becarried on throughout the year indozens of work groups and informalrelationships established at the confer-ence. You can expect to see at DAC—the premier conference for the designand EDA industry—the unveiling ofinnovative resources, technologies,

and tools, some of which will bespecifically targeted at demandingcommunications SOC applicationssuch as a line card on a chip.

Bryan AcklandEDA Industry Chair Design Automation Conference

IEEE Publications is pleased toannounce the latest update tothe IEEE Xplore online delivery

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The International MicrowaveSymposium and the ExhibitMicrowave Week, which

include the RFIC Symposium, willtake place this year 6–8 June in FortWorth, Texas. The three-day sympo-sium is the largest conference specifi-cally focused on wireless IC designand technology. The RFIC Sympo-sium regularly brings in over 750attendees with its workshops, panelsessions, and technical sessions cov-ering all aspects of RFIC develop-ment. Technical session topicsinclude:

• Cellular system ICs and archi-tectures: GSM, EDGE, TDMA,CDMA, 3G, WCDMA, GPS

• Wireless data system ICs andarchitectures: Bluetooth, WLAN,802.11x, MMDS, UWB

• Optical system ICs and archi-tectures: OC-48, OC-192, OC-768, gigabit transceivers

• Small-signal circuits: LNAs, mixers,VGAs, active filters, modulators

• Large-signal circuits: poweramplifiers, drivers, advancedTX circuits

• Frequency generation circuits:VCOs, PLLs, synthesizers

• Device technology: IC tech-nologies, packaging, modules,RF test and characterization

• RFIC modeling and CAD:Device and behavioral model-ing, parasitic extraction, circuitsynthesis

The Symposium begins on Sunday,6 June, with a day of workshops. Inconjunction with the InternationalMicrowave Symposium, there will be

fourteen workshops and two tutorials.Seven of these workshops are RFICfocused and are sponsored by theRFIC Symposium: “WLAN front ends,”“Receiver design for 4G,” “Software-defined radio,” “RFIC technology evo-lution,” “Mixed-signal design method-ology,” “ESD protection for RFICs,”and “Noise in Si-based devices.”

The RFIC reception is on Sundaynight. Open to all attendees, this cock-tail hour gives new and old colleaguesan opportunity to meet and catch upon the real news in the wireless indus-try. This event will be held in the mainballroom of the newly renovated FortWorth Convention Center.

The conference formally opens onMonday with the Plenary Session.Three renowned speakers fromindustry give their views on the con-

2004 IEEE RFIC Symposium


vergence of wireless data and cellu-lar. Guenter Weinberger, CEO ofSandbridge Technologies, discussesthe “Architecture and design trendsof convergence devices.” NambiSeshadri, VP/CTO of the Mobile andWireless Group at Broadcom, has atalk on “Wireless nirvana-life in afully connected world.” Bill Krenik,Wireless Advanced ArchitecturesManager at Texas Instruments—whois involved in the TI single-chip radioeffort—gives a talk on “Cellularhandset evolution—convergence ofhigh-speed data services.”

The remainder of Monday andTuesday are filled with 22 technicalsessions. This year the Symposiumreceived over 315 submitted papers,of which only the best 110 will bepresented during the conference.Lunchtime on both days is occupiedwith a free panel session. DuringMonday’s panel “Ultra-wideband: Anacademic exercise or a practical pathto higher data rates?” a very distin-guished list of panelists will debatethe commercial future of UWB. Orga-nized and moderated by Chris Rudellof Berkana Wireless, the sessionincludes the following panelists:

• Robert Brodersen, University of

California, Berkeley• Ali Hajimiri, California Institute of

Technology• Ranjit Gharpurey, University of

Michigan, Ann Arbor• Andy Rappaport, August Capital• Jeffrey R. Foerster, Intel Corpo-

ration• John McCorkle, UWB Organiza-

tion, Motorola• William McFarland, Atheros Com-

municationsTuesday’s panel is cosponsored by

the IMS and is titled “EDA designflows for RFIC, module, and System-In-a-Package design: Systematicmethodologies or still an art?” Panelparticipants from different sectors ofthe wireless component food chainwill focus on design methodologies,EDA tools, and design flows thataddress the demand for highly inte-grated RFICs and wireless modules.Yorgos Koutsoyannopoulos of Helicand Cheryl Ajluni of Wireless SystemsDesign magazine have broughttogether a diverse group of panelists:

• Ron Wood, Atmel• Bob Mullen, Cadence Design

Systems• Peter Thoma, CST• Martin Versleijen, Philips Semi-

conductors• Cheryl Ajluni, Wireless Systems

Design magazine• Yorgos Koutsoyannopoulos,

HelicAn interactive forum paper presen-

tation takes place on Tuesday after-noon in the annex of the exhibit hall.This unique format allows attendeesto stroll through an open area where40 authors discuss posters of theirwork. The interactive forum is run inconjunction with the IMS, resulting in60 unique papers on each of the threedays of the forum.

The RFIC Symposium ends onTuesday, allowing plenty of time toattend the technical sessions at theIMS or roam the huge exhibit hall.This is a great opportunity to meetmany of the wireless and microwavevendors displaying their latest prod-ucts. The IMS also has a wonderful setof activities planned in the historicFort Worth area.

Come to Fort Worth this June. TheRFIC Symposium, IMS, and exhibitprovide great opportunities for con-tinuing your wireless educationthrough a wide selection of work-shops. The Symposium will keep youabreast of the latest RFIC design andtechnology developments throughthe 110 papers and 22 technical ses-sions, as well as through meeting ven-dors displaying their latest products.Please check out the con-ference Web site atwww.rfic2004.org formore details and the lat-est information.

Stephen LloydGeneral Chair2004 RFIC Symposium

Guenter WeinbergerCEO Sandbridge Technologies

Nambi SeshadriWireless Group VP/CTOBroadcom

Bill KreniWireless AdvancedArchitectures ManagerTexas Instruments

Mehran AliahmadAtila AlvandpourBob AtwellJames B. BartonAmine BermakFernando D. CarvajalWim P. DehaeneAndrei GrebennikovElmer H. GuritzPaul E. HaslerRockwell HsuKenji Itoh

Christopher A. JacobsNikolaus KlemmerRam KrishnamurthyShyamkant A. KulkarniHiroaki KuniedaYoungwoo KwonMoon Key LeeAlvin LS LokeGabriele ManganaroDonald T. McGrathRonald J. MelansonAndrei Mihnea

Perry A. MillerDong-Sun MinAli MireshghiChris J. MyersTamotsu NishinoKenneth OPhuc C. PhamSitthichai PookaiyaudomDavid C. PottsWilliam R. Richards, Jr.Ken J. SchultzRainer L. Schweer

Ramesh SenthinathanKaijian ShiJyuo-Min ShyuEfstratios SkafidasHarold L. SnyderCharles H. SobeyJohn W. SpargoMamoru TerauchiOliver WertherSeung-Moon YooOlga F. Zamorska

Congratulations to the New Senior Members

An IEEE Fellow holds the high-est grade of IEEE membership.Elevation to Fellow recognizes

unusual distinction in the profession,and is conferred by the IEEE Board ofDirectors upon a person with an extra-ordinary record of accomplishments inany of the IEEE fields of interest. Theaccomplishments honored contributesignificantly to the advancement ofengineering, science, and technology.After a rigorous evaluation processperformed each year by the IEEE Fel-low Committee, a slate of candidates isproposed to the IEEE Board of Direc-tors for approval.

The number of successful candi-dates in any year must not exceedone-tenth of one percent of IEEEmembers. For 2004, of the 260 Fellowselevated, the following five were eval-uated by the Solid-State Circuits Soci-ety. An additional 13 SSCS membersalso have been elevated and will belisted in the July issue.

Anantha P. Chandrakasan For contributions to the design of energy-efficient integrated circuits and systems

Anantha P. Chan-drakasan receivedhis BS, MS, and PhDdegrees in electricalengineering andcomputer sciencesfrom the Universityof California, Berke-

ley, in 1989, 1990, and 1994, respec-tively. Since September 1994 he hasbeen with the Massachusetts Instituteof Technology, Cambridge, where heis currently a professor of electricalengineering and computer science.

He has received several awardsincluding the 1993 IEEE Communica-tions Society’s Best Tutorial PaperAward, the IEEE Electron Devices Soci-ety’s 1997 Paul Rappaport Award for theBest Paper in an EDS publication during1997, and the 1999 Design AutomationConference Design Contest Award.

His research interests include low-power digital integrated circuit design,wireless microsensors, ultra-widebandradios, and emerging technologies.

He is a coauthor of Low-Power DigitalCMOS Design (Kluwer Academic Pub-lishers, 1995) and Digital IntegratedCircuits (Pearson Prentice-Hall, 2003,2nd edition). He is also a coeditor ofLow-Power CMOS Design (IEEE Press,1998) and Design of High-Perfor-mance Microprocessor Circuits (IEEEPress, 2000).

He served as a technical programcochair for the 1997 International Sym-posium on Low-Power Electronics andDesign (ISLPED), VLSI Design ‘98, andthe 1998 IEEE Workshop on Signal-Pro-cessing Systems. He was the signal pro-cessing subcommittee chair for ISSCC1999–2001, the program vice-chair forISSCC 2002, and the program chair forISSCC 2003. He was an associate editorfor the IEEE Journal of Solid-State Cir-cuits from 1998 to 2001. He serves onthe SSCS AdCom and is the technologydirections chair for ISSCC 2004.

Beomsup KimFor contributions to integrated circuitsfor high-speed communication systems

Beomsup Kim re-ceived his BS and MSdegrees in electronicengineering fromSeoul National Uni-versity, Seoul, Korea,in 1983 and 1985,respectively, and his

PhD in electrical engineering and com-puter sciences from the University ofCalifornia, Berkeley, in 1990. From 1990to 1991 he was with Chips and Tech-nologies Inc., San Jose, California,where he was involved in designinghigh-speed signal-processing ICs fordisk drive read/write channels.Between 1991 and 1993 he was withPhilips Research, Palo Alto, Calfornia,conducting research on digital signalprocessing for video, wireless commu-nication, and disk drive applications. In1994 he joined Korea Advanced Insti-tute of Science and Technology(KAIST), Taejon, Korea, as a facultymember with the department of electri-cal engineering. During 1999 he took asabbatical leave at Stanford Universityand also consulted for Marvell Semi-

conductor Inc., San Jose, California, onthe Gigabit Ethernet (802.11ab) andwireless LAN (802.11b) DSP architec-ture. In 2001 he started Berkana Wire-less Inc. with Cormac Conroy and isCTO/VP Engineering for the company.His research interests include mixed-mode signal-processing IC and systemdesign for wireless communication,telecommunication, disk drives, local-area networks, high-speed analog ICdesign, and VLSI system design.

Dr. Kim is a corecipient of the 1991Best Paper Award for the IEEE Journalof Solid-State Circuits and received theKAIST EE Department Best LectureAward in 1997. Between June 1993and June 1995 he served as an associ-ate editor for the IEEE Transactionson Circuits and Systems II: Analogand Digital Signal-Processing Society.In 1999 he was one of four lecturersfor the Gigabit Ethernet Short Courseat the IEEE International Solid-StateCircuits Conference.

David Barry ScottFor contributions to CMOS and BiC-MOS technology and circuits

David B. Scottreceived his BScdegree in physicsand his MASc andPhD degrees in elec-trical engineering, allfrom the Universityof Waterloo, Water-

loo, Ontario, Canada. He is a TexasInstruments Fellow in Silicon Technol-ogy Development, working on thedesign and fabrication of high-perfor-mance, low-leakage products. His pastactivities at TI include work on CMOSprocess technology, memory design,high-speed telecom circuits, and relia-bility modeling. He has presented andpublished over 40 papers in variousjournals, conferences, workshops, andbooks. Dr. Scott is an inventor or coin-ventor in over 25 patents. In additionto his work at TI, he has served thetechnical community in various capac-ities, including: chair of the 2002 VLSICircuits Symposium; associate editorof the IEEE Journal of Solid State Cir-


SSCS IEEE Fellows for the Class of 2004

cuits; ISSCC and IEDM paper selectioncommittee member; and as a panelist,moderator, or organizer for eveningpanel discussions at various confer-ences. He is actively involved with theACM/IEEE International Symposiumon Low-Power Electronics andDesign.

Christer Svensson For contributions to single-phase clock-ing and high-speed CMOS circuits

Christer Svensson is aprofessor of elec-tronic devices atLinköping University.He was born inBoras, Sweden, in1941 and received hisMS and PhD degrees

from Chalmers University of Technolo-gy, Sweden, in 1965 and 1970, respec-tively. He was with Chalmers Universi-ty from 1965 to 1978, where he per-formed research on MOS transistors,nonvolatile memories, and gas sensors.He joined Linkoping University in1978, and since 1983 he has been aprofessor of electronic devices. Svens-son initiated a new research group onintegrated circuit design and pioneeredthe fields of high-speed CMOS designin 1987 and low-power CMOS in 1993.His present interests are high-perfor-

mance and low-power analog and dig-ital CMOS circuit techniques for com-puting, signal processing, and sensors.Svensson has published more than 170papers in international journals andconferences and holds ten patents. Hefounded several companies, includingSwitchcore and Optillion, where heserves as a director. He also has servedon the board for the Swedish ResearchCouncil for Engineering Sciences andon the IEEE SSCS AdCom. He wasawarded the Solid-State Circuits Jour-nal 1988–89 Best Paper award. He is amember of the Royal Swedish Acade-my of Sciences and the Royal SwedishAcademy of Engineering Sciences.

Osamu Tomisawa For contributions to low-power, high-speed integrated circuits

Osamu Tomisawareceived his BS andMS degrees in elec-tronic engineeringfrom Kyoto Universi-ty in 1969 and 1971,respectively. Hereceived his PhD

degree in electrical engineering fromOsaka University in 1980. Tomisawajoined Mitsubishi Electric Corporationin 1971 where he has been working onmemory, logic, and processor design.

From 1976 to 1979 he worked on high-speed MOS gate array development;from 1979 to 1980, he worked on high-speed SRAMs. Tomisawa is a coinven-tor of the “divided word line” patent,which is a hierarchical word line struc-ture of memory. He spent one year(1980) at the University of California,Berkeley, as a visiting scholar, wherehe did research on VLSI computerarchitecture and participated in a RISCproject. He returned to the MitsubishiElectric LSI Laboratory in 1981. Until1992, Tomisawa was general manager,LSI Design Department in the LSI Lab-oratory of Mitsubishi Electric, where hesupervised many projects, including32-bit CPU chips, DSPs, and customprocessors. From 1992 to 1995 he wasgeneral manager, Advanced MCU andMPU Department, Kita-Itami Works,Mitsubishi Electric, working on 16-bitand 32-bit MCU development andtechnical marketing. From 1996 to1997 Tomisawa supervised a 32-bitRISC MCU development project. From1998 to 1999, he was president andCEO of VSIS Inc. in California, workingon System On Chip. From October1999 to November 2001 he was thegeneral manager of the Design Engi-neering Center, Mitsubishi Electric andElectronics USA Inc., North Carolina.Currently, Tomisawa is a professor atKochi University of Technology.


The fourth IEEE Asia-Pacif-ic Conference onAdvanced System Inte-

grated Circuits (AP-ASIC) will beheld in Fukuoka, Japan, 4–5August 2004. The objectiveof AP-ASIC is to promoteresearch and developmentactivities of solid-state cir-cuits for the new millenni-um. The conference willinclude regular sessions onintegrated circuits and sys-tems with emerging designtechnologies, and special sessionson selected advanced aspects ofsystem LSIs. Original papers are

being selected from manuscriptssolicited in the following subjects:

1.Processor and reconfigurable

computing 2. Digital signal processingand digital communicationcircuits3. Arithmetic circuits and IPcores 4. Memory circuits5. Analog and mixed-signalcircuits6. RF and analog communi-cation circuits7. Sensor, image circuits, andMEMS

AP-ASIC 2004 will includethe following four invited presenta-tions: “Mixed-signal SOC design”by Professor Akira Matsuzawa,

Fourth IEEE Asia-Pacific ASIC Conference in Fukuoka,Japan, 4–5 August 2004

Congress Outlook, in Fukuoka, Japan, site of the August2004 Asia Pacific-ASIC.

Tokyo Institute of Technology,Japan, “u (myu)-Chip” by Dr. Mit-suo Usami, Hitachi Co. Ltd., andone presentation each from Koreaand Taiwan, which will be deter-mined soon.

The university design forum willbe organized as a special session inthe fourth IEEE AP-ASIC. This ses-sion is for young researchers/designers in integrated circuit

design to present their own worksand discuss their ideas. Authors areto submit their papers in the sameformat as a regular paper, exceptfor the length (two pages maxi-mum). The papers will be judgedby the technical program commit-tee and will be published with reg-ular papers in the same proceed-ing. Many papers from universitystudents are expected.

The conference rotates its locationbiannually (every even year) withincountries of IEEE region 10. The AP-ASIC 1999 and AP-ASIC 2000 wereheld in Korea and AP-ASIC 2002was held in Taiwan. The IEEE SSCSJapan Chapter and IEEE KansaiChapter will host AP-ASIC 2004.For more details please visit theconference Web site: www.vdec.u-tokyo.ac.jp/AP-ASIC2004.


More articles from the Jour-nal of Solid-State Circuits(JSSC) are downloaded

every month through IEEE Xplore®

than from any other publication inthe IEEE collection. In official patentrecords, the JSSC is the most-citedpublication for electro-technologypatents (www.ieee.org/patentcita-tion). What are the characteristics ofSSCS members that make them such

avid readers of the Society’s Journal?As SSCS Past-President Charles

Sodini describes it, “We are relevantto industry. The academics thatpublish in the Journal are also veryinterested in industry. It is the com-bination of industry and academicsthat is so great.”

A recent IEEE member satisfac-tion survey shows that SSCS standsout as having a greater portion of

members employed in industrythan other societies. Figure 1 showsthat more than three-quarters ofSSCS members work in industrycompared to less than half for allother IEEE societies.

The survey, developed by theIEEE Strategic Planning Office underthe direction of Elena Gerstmann,was completed June 2003. A randomselection of over 1,000 members for

SSCS—Relevant to Industry

Figure 1. SSCS member/employer distribution comparedto other IEEE Societies.

Figure 2. SSCS member education compared to other IEEE Societies.

each society was emailed an invita-tion and a link to participate in thesurvey. Over 13,500 responses (a32% response rate) were tabulated,reported, grouped, and compared.Although the first results were issuedlast summer to each individual soci-ety, it’s the aggregate of all societies’results that provides a unique viewof SSCS.

The Society’s strong industryemployment base is paired with thehigher portion of master’s degrees toPhDs among SSCS members. SSCSmembers are more apt to considerSSCS their primary society. They relyon the Journal more than confer-ences for their technical information.

A corollary to the workplace ofSSCS members is their educationlevel, shown in Figure 2. Close tohalf of SSCS members have master’sdegrees, compared to 42% in theaggregate of all societies. Most soci-eties have 10% more PhDs thanSSCS. Undergraduate degrees are

about an equal portion in the aggre-gate of societies.

There are many traits of societymembers that are similar no matterwhat technical field they are in. Allsociety members are as eager foreducational opportunities as SSCSmembers. The variety of majors didnot vary much; SSCS, like the aggre-gate of society membership, had12% with degrees in physics. In allsocieties academics are more apt toattend conferences; members inindustry attend the fewest.

Given that pattern and the strongindustry base of SSCS, our membersattend fewer conferences (1.3 peryear) than the aggregate of IEEE soci-ety members (1.8 per year). Non-society members average even lowerattendance (1.1 per year). About aquarter of our members felt theyweren’t familiar enough with ourconferences to rate their usefulness.Those that attend the conferences orread the Digests find them useful.

More than half of the members donot volunteer because they don’tunderstand how SSCS activities areorganized. However, 15% have vol-unteered, which is a similar percentfor societies comparable in size toSSCS. Those who volunteer werepleased with the experience.

A whopping 99% of the respon-dents felt the Journal was useful tothem with 1% indicating they wereinsufficiently familiar with the Jour-nal to comment. No one indicatedthe Journal was not useful.

Respondents were 10% more like-ly to agree that SSCS was their pri-mary society than any other (64%for SSCS versus 54% for other soci-eties). Because of the breadth oftechnical expertise required for ICdesign and production, the corefield of interest of SSCS, many of ourmembers hold memberships in mul-tiple societies. However, more SSCSmembers feel that SSCS meets theirprimary needs.


The SSCS OutstandingChapter Award is given toa chapter that has shown

excellent leadership and initiativein organizing activities. Selectionis based the quality and quantityof activities and programs, thebenefits for local members, suc-cessful outreach to the profes-sional community, and growth inchapter membership.

The recipient of this year’saward is the Bangalore, India,Chapter, which has excelled ineach of the above criteria.Although the Bangalore Chapteris one of the newest chapters, itis also one of the most active onesin organizing educational activitiesand stimulating membershipgrowth.

The Bangalore Chapter has orga-nized two workshops, a ShortCourse, and an impressive list ofDistinguished Lectures and semi-nars. “The officers under the lead-ership of Professor Navakanta Bhatdeserve our warm congratulations

in making the Bangalore Chapterone of the most dynamic and suc-cessful ones among the 48 SSCSchapters,” said Jan Vander Spiegel,the SSCS Chapters Coordinator.

Established in October 2001, thejoint SSCS and EDS BangaloreChapter is off to a fine start withquite a few educational activities inareas spanning both electrondevices and solid-state circuits.

Their events attract students andare well accepted by local profes-sionals—as shown by the numberof attendees. The Society main-tains a Web site to publicize eventsand utilizes the Bangalore Sectionnewsletter. This is the fourth chap-ter in the IEEE Bangalore Section.

The fact that this chapter is ajoint SSCS and EDS activity is areflection of the coupling betweenthe device domain and circuitdomain that has become extreme-ly strong in state-of-the-art semi-conductor technologies. Thesefields cannot be viewed in isola-tion—the future requires a broader

perspective. In fact, device scalingtowards atomic scale and the com-plexity of circuits in System On aChip (SOC) will make this couplingstronger and also will encompassother domains such as mechanical,optical, and biological fields. TheInternational Technology Roadapfor Semiconductors (public.itrs.net/)is an authoritative reference for thisperspective.

Bangalore Named SSCS Outstanding Chapter for 2003

Navakanta Bhat accepting the SSCS OutstandingChapter Award for Bangalore from Steve Lewis,Society president.

Professor Navakanta Bhat atthe Indian Institute of Sci-ence Bangalore and chair of

the 2003 SSCS Outstanding Chap-ter, knows the value of chapteractivities. The attendance at localevents has ranged from 30 to 300,with an excellent balance betweenindustry and students.

The Chapter is joint betweenSSCS and EDS. In the BangaloreSection there are about 50 mem-bers of ED/SSCS. “But we believethat the total number of profes-sionals in Bangalore working inthe related fields such as semicon-ductor process and device tech-nology, VLSI design, ECAD,TCAD, and MEMS may be an orderof magnitude higher.” The chapterintends to bring them into the foldand offers to help their profes-sional development.

However, what the professorenjoys most about his chapterinvolvement is “the fact that everyevent that we organize under thechapter has benefited the stu-dents—the future professionals—immensely. The chapter is impor-tant to create awareness aboutIEEE and its usefulness.”

Bhat finds that local institutionsand companies help the chaptercarry out their activities. “We arefortunate that for most of theevents, local institutes and compa-nies who host the events don’tcharge us for the venue. That is abig support.”

Bhat recalls that the BangaloreChapter was started by ProfessorsRenuka P. Jindal and J. Vasi andthat both have been chapter part-ners since its inception. “Theyconvinced me that it makes a lotof sense to have a joint EDS andSSCS chapter in Bangalore. Since Ihappened to be a member of boththese societies, I immediatelydecided to take this up.”

M.K. Radhakrishnan, who waschair of the Singapore Rel/ED/CPMTChapter, has recently relocated toBangalore. Bhat reports that he hasbecome a valued colleague to theSingapore chapters with his richexperience in volunteering for IEEEand in serving as a chapter partnerto the Electron Devices Chapters ofIndia and Bombay. Radhakrishnanpoints out that “the various pro-grams, such as technical talks, Dis-tinguished Lectures, and continuingeducation programs are the impor-tant effects of chapter activities forboth student and professional.” As avolunteer he “enjoys the workingenvironment, especially the commit-ment of a few volunteers, eventhough they are only a few.”

Ideas for technical talks emergeduring discussions with industryand academic colleagues. “Thetopics are decided based on thebackground audience (undergrad-uate, graduate, etc.),” Bhat reports.“Fortunately, it has not been aproblem to identify resource per-sons in Bangalore, since this city

has the largest number of profes-sionals in the country working inEDS and SSCS and related areas.”The Bangalore Chapter also hasorganized tours of local businessesand has found them to be valuablechapter activities.

Organizing and publicizingchapter events takes a number ofpeople. The Web site is main-tained by R. Srinivasan, a gradu-ate student at IISc. A lot of thelogistics that go into the localarrangements are taken care of byvarious people, depending on thevenue of the event. From the verybeginning of the joint chapter in2001, Radhakrishnan offered tohelp the Bangalore Chapter. Hehas given three technical talks atthe chapter as an EDS Distin-guished Lecturer. C.R.Venogopalis working to set up the ED/SSCSstudents’ chapter under the IEEEstudents’ section at Mysore, about100 miles away from Bangalore.P.V. Subrahmanyam and ProfessorC.R.Venogopal also contribute asofficers.

“This kind of activity can besustained and carried forwardonly through enthusiastic volun-teers. We urge professionals andstudents to be proactive and bepart of this new chapter. By allmeans, anyone interested in vol-unteering can contact me or anyother officers. We would be veryglad to have more volunteers,”says Bhat.


Chapters Are Volunteer Powered—the BangaloreChapter Case Study

SSCS members like chapterevents but often don’t partici-pate. Respondents to a 2002 sur-

vey of SSCS members rated the qual-ity of presentations and the educa-tional opportunities of chapter eventsas very satisfactory or satisfactory, by9 to 1. The professional networking,meeting times, and locales were ratedsatisfactory or very satisfactory bybetter than three to one. However,more than two-thirds of the surveyrespondents didn’t know enoughabout chapter events to answer ques-tions about the program.

Of the 304 IEEE sections world-wide, 47 (15 percent) have an SSCSchapter. This same portion (15 per-cent) of SSCS members respondedin a 2003 All Society Research Pro-ject that they have taken advantageof chapter-sponsored activities.

Thirty percent are unsure whetherthere is a local chapter or not. If youwant to know if there’s a chapter inyour area, start at the SSCS chapterspage (sscs.org/chapter.htm) or findlocal news on your IEEE section’shome page (www.ieee.org/organiza-tions/rab/sec_chap/reg_pags.html).

Even when members knowthere is a local chapter, 47 percentreport they still don’t participate inchapter programs. Keep track of

chapter announcements andattend next time. If you have atopic and a speaker you’d like tohear, introduce yourself to yourchapter or section leader and sug-

gest a topic, or offer to organize aspeaker event or workshop. Thediscussion that ensues will giveyou a better understanding of howyour local volunteers can worktogether. You may find that thereare other volunteers who can helparrange a meeting place or publi-cize your event. Chapters are vol-unteer powered.

Eight percent of the respondentsare quite sure that there is nochapter in their area. Starting oneisn’t as hard as you think. It onlytakes twelve members to sign apetition to start a chapter. If youhave ideas about local meetingsyou’d like to attend, work withyour IEEE section to organize oneand publicize it. The meeting canserve as the kick off to finding like-minded people to plan furtherchapter activities and sign the peti-tion to form a new chapter.


Nine to One, SSCS Members Who Try Chapter EventsLike Them

SSCS now has 47 chapters around the world. 31 leaders of 14 chapters met togeth-er to exchange ideas on managing chapters while attending the ISSCC. Row 1: Peter Kennedy, Magnus Wiklund, Christian Enz, Eric Vittoz, Jan Van derSpiegel, Row 2: Michel Bron, Moon Key Lee, Bruce Hecht, Jin Burm, Atila Alvand-pour, Jonathan David, Row 3: Ammar Gharbi , Phil Allen, Steve Lewis, NavakantaBhat, Jieh-Tsorng Wu, Row 4: Kwang Sup Yoon, Katsuro Sasaki, Mohamad Sawan,Shen-Iuan Liu, Feng Chen, Row 5: Andreas Olofsson, Makoto Nagata, Rick BittingRow 6: Anas Hamoui, Richard Gu, Zhihua Wang, Row 7: Dan Oprica, Christer Svens-son, Francis Jeung, Wilhelmus Van Noije.


The publications committee members are from left toright, Dick Jaeager (Chair), Steve Lewis, Bram Nauta,Bernhard Boser, Tim Tredwell, Jan Rabaey, and IanGalton.

The AdCom members are, front row, left to right; Tim Tredwell, Gary Baldwin, Teresa Meng, David Johns, Charlie Sodini, SteveLewis (President), Dick Jaeger, Dave Hodges, Wanda Gass, Anne O’Neill, and John Corcoran. Standing, back row, left to right;Rakesh Kumar, Darrin Young, Bryan Ackland, Bram Nauta, Bernhard Boser, Takayasu Sakurai, Thomas Lee, Anantha Chan-draksan, Jan Sevenhans, Jan Rabaey, and Jan Van der Spiegel.

SSCS AdCom ReportsAt their February meeting, the SSCS AdministrativeCommittee reviewed the financial status of the Societyand evaluated and passed the motions brought forwardby the Meetings and Publications Committees. The Pub-lications Committee agreed to produce for sale in 2005,a CD of the JSSC 2003–2004 articles, and a 2004 updat-ed DVD set of the Solid-State Circuits Archives. The

committee also agreed that the newsletter will bereduced to three print issues but expanded to six elec-tronic issues in 2005. This will be managed through anew Web interface. The Meetings Committee agreed todevelop a calendar for Web posting to assist in coordi-nating the dates of major conferences for a few yearsinto the future.

SSCS Meetings Committee from left to right,Anantha Chandraksan (chair), Bryan Ackland,Steve Lewis, Dave Hodges, Rakesh Kumar, TimTredwell, Takayasu Sakurai, Gary Baldwin, andWanda Gass.


TECHNICALLY CO-SPONSORED MEETINGS2004 Radio Frequency Integrated Circuits Symposium www.rfic2004.org6–8 June 2004Fort Worth, TX, USAPaper deadline: passed

2004 Design Automation Conferencewww.dac.com7–11 June 2004San Diego, CA, USAPaper deadline: passed

2004 Symposium on VLSI Technology www.vlsisymposium.org15–17 June 2004 Honolulu, HI, USAPaper deadline: passed

2004 Asia-Pacific Conference on Advanced SystemIntegrated Circuits (AP-ASIC)www.ap-asic.org4–5 August 2004Fukuoka, JapanPaper deadline: passed

2004 International Symposium on Low-Power Elec-tronics and Designwww.islped.org9–11 August 2004Newport Beach, CA, USAPaper deadline: passed

2004 Bipoloar/BiCMOS Circuits and TechnologyMeetingwww.macs.ece.mcgill.ca/~rfic/bctm04/12–14 September 2004 Montreal, QC, Canada Paper deadline: passed

2004 European Solid-State Circuits Conferencewww.esscirc.org/20–24 September 2004Leuven, BelgiumPaper deadline: 31 March 2004

2004 Compound Semiconductor IC Symposium(Formerly IEEE GaAs IC Symposium) www.csics.org24–27 October 2004 Monterey, CA, USAPaper deadline: 3 May 2004

2004 International Conference on Computer AidedDesign www.iccad.org 7–11 November 2004 San Jose, CA, USA Paper deadline: 21 April 2004

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

445 Hoes Lane Piscataway, NJ 08854

To maintain all your IEEE and SSCS subscriptions, emailaddress corrections to: [email protected]

To make sure you receive an email alert, keep your emailaddress current at sscs.org/e-news

IEEE SOLID-STATE CIRCUITS SOCIETY NEWSLETTER (ISSN1098-4232) is published quarterly by the Solid-State Circuits Soci-ety of The Institute of Electrical and Electronics Engineers, Inc.Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016-5997. $1 per member per year (included in society fee) for eachmember of the Solid-State Circuits Society. This newsletter is print-ed in the U.S.A. Periodicals postage paid at New York, NY and atadditional mailing offices. Postmaster: Send address changes toIEEE Solid-State Circuits Society Newsletter, IEEE, 445 Hoes Lane,Piscataway, NJ 08854. ©2004 IEEE. Permission to copy without feeall or part of any material without a copyright notice is grantedprovided that the copies are not made or distributed for directcommercial advantage and the title of publication and its dateappear on each copy. To copy material with a copyright noticerequires specific permission. Please direct all inquiries or requeststo IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane,Piscataway, NJ 08854. Tel: +1 732 562 3966.

SSCS SPONSORED MEETINGS2004 Symposium on VLSI Circuitswww.vlsisymposium.org17–19 June 2004Hilton Hawaiian Village, HI, USAPaper deadline: passedContact: Phyllis Mahoney, [email protected] Business Center for Academic Societies [email protected]

2004 CICC Custom Integrated Circuits Conferencewww.ieee-cicc.org3–6 September 2004Caribe Royale Resort Suites, Orlando, FL, USAPaper deadline: 5 April 2004Contact: Ms. Melissa Widerkehr, [email protected]

2005 ISSCC International Solid-State CircuitsConferencewww.isscc.org6–10 February 2005 San Francisco Marriott Hotel, San Francisco, CA, USAPaper deadline: 20 September 2004Contact: Courtesy Associates, [email protected]

SSCS EVENTS CALENDAR continued from page 15