2005. 2. 15. lee kyung-kuk - umlsumls.kaist.ac.kr/professor/ftp/7th_workshop/7th-07.pdf · m-ary...

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Slide 1

2005. 2. 15.

Lee [email protected]

Slide 2

ProposalZigBee proposes that IEEE 802.15 SG4a address the following application requirements:– Robustness against interference improved– PHY ranging (possible for upper layers to improve) of:

• 1.5 meters accuracy e.g. Residential Automation, Meter Reading, Asset tracking

• 0.5 meters accuracy e.g. Building Automation, High value asset tracking

– Mobility• 35-40 mph e.g. Meter Reading, Drop Box – UPS, FEDEX,

Container tracking• 80 mph e.g. Toll Booths

– Greater range / link margin• 100 meters or more outdoor line of sight

– Latency• Less than 17 msec each with 8 users

– Higher data rate• 500 Kbps – 1 Mbps

Slide 3

TopologyThe alt-PHY shall support all types of topologiesRelaying messages, Coordinating Cells or Aggregated Cells

Bit Rate Link bit rate: at least 1 kbps at PHY-SAP.Aggregated bit rate (data collector only): at least 1 Mbps at PHY-SAP

Range The maximum distance between communicating nodes is generally 0 to 30 mThe range has to be extended to several hundreds of meters

Coexistence and Interference ResistanceThe devices must be able to operate in high noise and high multipath environment.

Power Consumptiona battery life of months or years without intervention.

Quality of serviceThe critical factor is the reliability of the transmission.

Form FactorSensor and RF tag applications.

TG4a Technical Requirements

Slide 4

ComplexityComplexity (gate count, die size) and BOM shall be minimizedThe components are to be considered as throwaway after use

Location awarenessIt can be related to precise (tens of centimeters) localization in some caseslimited to about one meter

MobilityThis is a mandatory feature related to intra-cell mobility, not to roaming or handover. Nodes shall be capable of reliable communication when in the move, at least for tracking.

Compliance and or Supplements to 802.15.4 functionalityIt is envisioned that the alt-PHY project will allow supplements to 802.15.4

Regulatory mattersThe alt-PHY standard will comply with necessary geopolitical or regional regulations.

TG4a Technical Requirements

Slide 5

Impulse radio: Mitsubishi / MIT / Princeton / Georgia

Pulse Gen.

TH SeqBPSK symbol mapper

BPSK symbol mapper

Delay

Central Timing Control

Multiplexer

Td

0<>

Rake ReceiverFinger

Np

Rake ReceiverFinger 2

Rake ReceiverFinger 1

Summer

Transceiver architecture

Transmitted ReferenceFirst pulse serves as template for estimating channel distortionsSecond pulse carries informationDrawback: Waste of 3dB energy on reference pulses

Bandwidth determined by pulse shape

Slide 6

Impulse Radio: Freescale / decaWave

Transceiver architecture

Code GenFilter

Sense

LNA

÷L code

1.352 GHz(104 * 13 MHz )

Agile ClockLocks to Chip Rate

Symbol Rate

3n RF Cyclesper Chip

Ternary Code{ +1, 0, -1}

Receiver

D

CkQ

Encoded TxData

dr

Idealized

Filtered (LPF + RF)

Inverted , Non -Inverted and Zero -Amplitude Wavelets

Code Clock Chip Clock

Ant

∫ S/H To ADC

x 3n

- 1- 1 - 11 1 1 10 ÷n

Chip Rate Clock

n = 1 for 1.5 GHz BW (15 .3a)n = 3 for 500 MHz BW (15 .4a)

LPF

This is as simple as anything else

9.4 Mbps0.518.778 MHz24

37 kbps0.573 kHz6144

293 kbps0.5587 kHz768

1.17 Mbps0.52.35 MHz192

PHY Bit RateFEC RateSymbol Rate Spreading code Length

Slide 7

Impulse Radio: STM / CEA-LETI / CWC / AEtherwire

Receiver architecture

Band MatchedBand Matched

LNALNALNA BPFBPF

SynchroTracking

Thresholds setting

SynchroSynchroTrackingTracking

Thresholds Thresholds settingsetting

DumpLatchDumpDumpLatchLatch

RA

ZR

AZ

DUMPDUMP

ControlledControlledIntegratorIntegrator

ADCADC

BPPM Demodulation BPPM Demodulation branchbranch

RAZRAZ

TriggerTrigger

Time baseTime baseTime base

THRESHOLTHRESHOLDD

ADCADC

ComparatorComparatorComparator

IntegratorIntegrator

Ranging Ranging branchbranch

x2x2r(t)

Recyle this branch for Enhanced Mode 2

DelayDelayDelay

TR Demodulation TR Demodulation branchbranch

DumpLatchDumpDumpLatchLatchADCADC

ControlledControlledIntegratorIntegrator BPPM BPPM

Synch Synch TriggerTrigger

TRTR

« 1 »

« 0 »Basic Mode

D« 1 1 »

« 1 0 »Enhanced Mode 1« 0 1 »

« 0 0 »

« 1 0 1 0 »

½ PRP ½ PRP

« 1 1 1 1»Enhanced Mode 2

Slide 8

Impulse Radio: General Atomics

Transceiver architecture

Shaped UWB pulses ~4 ns long and ~500 MHz BWScalable data rates from 100-400 kbpsON/OFF Keying (OOK) modulationPulse (chip) rate is 12 MHz

Transmitter

Receiver

Analog

Digital

Slide 9

Pulse Generator

I

Q

LPF Digital Block

Data

LNA

Transmitter

ReceiverLPF

0/90 PLL

Modulation & Spreading

ADC

ADC

Digital PHYAnalog RF MAC

Data•Matched Filter•Signal Acquisition•Tracking•Rangingetc.

ANT.SwitchBPF

PA

4.1GHz

<100kgates32MHz, 4bits

Xtal

40ppm

Antenna

Impulse radio: Hitachi / YRP

Transceiver architecture

Slide 10

Transceiver architecture

LPFX

LOLNA/VGA

Timing

X LPF ADC

ADC DiffDetection

MultipathCombing

DSDe-Spread

SymbolCombining

ViterbiDecoding

Acquisition

Non-CoherentDetection

MultipathCombining

(Across one DS codeword)

Gain

FrequencyCorrection

Data

Freq Offset

Spreading codes

-1 -1 1 -1 -1 1 -1 1 -1 -1 -1 1 1 1 1 1 -1 1 -1 1 -1 -1 1 1 -1 -1 -1 -1 1 1 1 1 -1 1 1 -1 1 -1 -1 -1 -1 -1 1 1 1 -1 1 1 -1 -1 -1 -1 -1 1 1 1 1 -1 1 1 -1 1 -1 1

ADC

~ BasebandProcessor MAC

Integrator

Transmitter

SRAM

Impulse radio: Staccato

Slide 11

Impulse radio: Wisair

Transmitter architecture

ConvolutionEncoder

(1,1/2,1/3)

DifferentialEncoder

Repetition(1,10,20)InterleavingScrambler

Multiply by528Mcps

hierarchicalsequence(16x8+48)

Multiply by3Mcps PN Up converter

Band Plan

10560 MHz10296 MHz10032 MHz14

10032 MHz9768 MHz9504 MHz13

9504 MHz9240 MHz8976 MHz12

8976 MHz8712 MHz8448 MHz11

8448 MHz8184 MHz7920 MHz10

7920 MHz7656 MHz7392 MHz9

7392 MHz7128 MHz6864 MHz8

6864 MHz6600 MHz6336 MHz7

6336 MHz6072 MHz5808 MHz6

5808 MHz5544 MHz5280 MHz5

5280 MHz5016 MHz4752 MHz4

4752 MHz4488 MHz4224 MHz3

4224 MHz3960 MHz3696 MHz2

3696 MHz3432 MHz3168 MHz1

Upper frequencyCenter frequencyLower frequencyBAND_ID

Symbol is based on shaped hierarchical sequences:The coded data (after differential encoding and repetition) is modulated using BPSK

Slide 12

Impulse radio: Harris

Transceiver architecture

t0 t1

f

f

Spectral Shaping within a frequency channel

• “delay and add” notch formation

• delay may be either a delay line or second impulse generator

Slide 13

Impulse radio: Thales / Cellonics

Transceiver architecture

MAC

PG

Non-coherent detector

Spreading & Modulation

Digital Block•Matched Filter•Signal

Acquisition•Tracking•RangingEtc.

<100kgates

1-bit ADCDATA

DATA

Digital PHY

LNA

BB amp

BPF

TRANSMITTER

RECEIVER

25MHz, 2.5MHzPRFDigital Matched FilterDespreading

Coded SequenceKasami (15, 63) and Gold

(7)

SpreadingOOKModulation3350±250MHz (10dB BW)RF Frequency

Specifications

Slide 14

Impulse Radio: Create-Net / BUPT(Beijing) / CUF / CAS

Transceiver architecture

Impulsive direct-sequence UWB

Slide 15

Raw bit rate: 1 MbpsSpreading code length: 16 chipsPulse repetition frequency (PRF): 16 MHz (pulse repetition interval = 62.5ns)

Impulse Radio: Tennessee Tech. Univ.

Transceiver architecture

Transmitter

Receiver

Slide 16

Impulse Radio: France Telecom R&D

Transceiver architecture

Pulse Generator

Clock

F < 100 MHzControl Logic

BaseBand signalRF Signal

PSDU Data

Pulse shaperPA (option)

x2 Lowpassfilter ThresholdBandpass

filter

Transmitter

Receiver

pulse-spacing = Tc ± TH

Pulse width = 1ns

Slide 17

Short CodeSpreading BPF

InformationBits A

Integrator(Long Code Despreader)

BPF

RecoveredBits

LNA

Tb*

BPSK Mod &

ChannelCoding

4 Mcps

4 GHz(50 ppm)

DifferentialDetector

Radio Channel

4 GHz(50 ppm)

Integrator(Short CodeDespreader)

ChannelDecoding

&Data

Detection

ADC

ModulatedLong CodeGenerator

ModulatedLong CodeGenerator

DifferentialEncoder

Impulse Radio: Wideband Access

Transceiver architecture

Receiver

Transmitter

BW: 1.0 GHz (3.5 – 4.5 GHz)Chip Rate: 1 GcpsADC operation at low rate (rather than chip rate) and Small Size ADC (1- 2 bit)

Slide 18

Impulse Radio: SandLinks

Transceiver architecture

BPF PulseGenerator

To AntennaBarker

Sequencegenerator

Timing andcontrol

Tx dataChannel Select

PowerAmplifier

FromAntenna

BPFDown

Conversion +Baseband

Correlator

I

QLNA

LO

Demodulation+

Acquisition

DecodingPacket

handling

Hardware

May be implemented inSoftware

Ranging

Receiver

Transmitter

8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 150.2

0

ns

Slide 19

Impulse Radio: California State University

Transceiver architecture

ROM, group 1

ROM, group 2

ROM, group 3

ROM, group 4

DACDA

CDACDAC

waveform transformer

waveform transformer

waveform transformer

Waveform transformer

data manipulatorS/P converter

encodinginterleavingencryption

input data

demodulatorData

De-manipulator

Pulsegenerator

SynchInformation

retriever

antenna LNA Data outdetector

location

Receiver

Transmitter

0 1 2 3 4 5 6 7 8 9 100

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Frequency( GHz.)

ampl

itude

+

+

+

t (ns)

0 4

Slide 20

Impulse Radio: Simon Fraser Univ. / Inha Univ. (ITRC)

Transceiver architecture

Receiver

Transmitter

M-ary Code Shift Keying/Binary PPM(MCSK/BPPM) Based Impulse Radio

Slide 21

Impulse Radio: KERI / UWB Forum / SSU / KWU

Transceiver architecture

Input BitSequence

DataRepetition

OOKModulation

Mo

deS

witc h

(/

/)Multipath

Combining

ReceivingData

Gathering

Output BitSequence

DecisionStage

UWB Transmitter

Operation Mode

UWB Receiver

Coarse Pulse Position Estimation

Timing Mode

ThresholdControl

NoiseMeasuring

Calibration Mode

ne

rgyD

ete cti on

Ti m

in gC

a libr at ion

Op

erati on

PulseGenerator

E

Slide 22

Impulse Radio: IIR (Singapore)

Transceiver architecture

Transmitter

Bit-to-Symbol

On-Offcontrol

Symbol-to-Chip

Binary data

From PPDU Pulse

Generator

ChipRepetition

BPF ( )2 LPF / integrator ADC

Sample Rate 1/Tc

SoftDespread

Receiver

32# Chip / symbol (Code length)

1 # Pulse / Chip Period

22 MHzPulse Rep. Freq.

4 bit / symbolinfo. bit / sym (Mandatory Mode)

22/32 MHz = 687.5 kHzSymbol Rate

{+1,-1} bipolar pulse train OR {1,0} bipolar pulse train + pulse jittering ORPeriodic On-Off Chaotic signaling

Modulation

22 Mcps **Chip rate

Slide 23

…………………………1 2 3 39 40

Symbol(160 ns)

…………………………...Quiet time( 300ns)

4 5 6 7 8 38

Non-inverted pulses are blue,Nulled pulses are orange,Inverted pulses are green.

Multiple chips make a symbol:

Impulse radio: TimeDomain

Transmit Signal

Impulse radioSingle band nominally from 3 to 5 Ghz.4 ns chip times40 chips per symbol300 ns quiet time between symbolsMax symbol integration = 64 (data)Max symbol integration = 256 (acquisition)

Slide 24

Impulse radio: NICT / Fujitsu / OKI

Transceiver architecture

Slide 25

DBO-CSK: Orthotron / Han-Yang Univ.

Transceiver architectureD/A

D/A

A/D

A/D

Tx/RxSw.

DBO-CSKMOD

DBO-CSKDEMOD

MACRanging Data

Baseband DigitalRF Analog

1z −

Chirp-Shift-Keying(CSK)

Generator

BinaryData

P/S

S/P SymbolMapper

Modulator

Scrambler FEC Encodingr=1, 1/2(option)

PRBSGEN.

SymbolRepetition

Seed

Chirp-Shift-Keying

8-ary DBO-CSK

Demodulator (Differential Detection)

RecoveredDataA/D

BasebandSignal

De-Scrambler

SelectLargest

De-Map P/S

DifferentialDetector

(Sub-Chirp)

De-Orthogonal

FECDecoding

TimeDe-

Spread

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

CSK Waveform

Slide 26

Chirp Spread-Spectrum: Nanotron

Transceiver architecture

Digital

Block

Digital

Block LPLP

LPLP

I

QLO

f = 2.412, 2.437 or 2.462 GHz

I/Q Modulator

fT = f ± 10 MHz

DDDLDDDL

Dig

ital B

lock

Dig

ital B

lock

fR = fLO± 10 MHz

Up

Down

RSSI

I/Q Demodulator

I

QLO

LPLP

LPLP

ADCADC

fLO = 2.412, 2.437 or 2.462GHz

1

1 Chirp pulse

2

2 Correlation pulse

3 Trigger signal with adaptive threshold

3

ADCADC

Transmitter

Receiver2 ary transmission

systemduration of 1 µs

Slide 27

Chaos DCSK: Samsung DM R&D

Transceiver architecture

DelayT/2

Threshold decision Integrator

/ 2( )

Tdt•∫

Direct Chaos Generator

DelayT/2

-1

RX

TX

Diplexer

User11100111110

User21101110110

User30100111010

Multi_path Channel

Slide 28

Chaotic Signal: ETRI / KAIST / HGU

Transceiver architecture

Transmitter[ ]1 2, , , Lc c c

d C b= ⋅

( )r tData ModulatorBi-phase PPM Channel

Data EncoderOrthogonalMulti-code

Data

PulseGenerator

[ ]1 2T

Lb b b b=[ ]1 2, , , Lc c c

Tb C d= ⋅

( )r t Data DecoderOrthogonalMulti-code

DataDeModulatorBi-phase PPM

Data

PulseGenerator

LocationDetector

Receiver

Data block( L bits )Ex. L=3

Orthogonal code set( Code Length : Ns )

Ex. Ns=4Modulation

Multi-coded symbol( Code rate : L/Ns )Ex. Code rate = 3/4

1 -3 1 1

PPM :

1-11

1-1-11-1-111-11-11

1-1-1111-1-1-11-11

⊕⊗⊗⊗

===

11-31=

Slide 29

Chaotic Signal: SAIT / IRE / SEM

Transceiver architecture

Modulation: OOKBandwidth: 0.5GHz & 2GHzPulse bin width, Tm: 400nsPulse emission time, Ts: 100ns

Slide 30

FM UWB: CSEM

Transceiver architecture

ReceiverTransmitter

FM-UWB uses a high modulation index FM signal

Modulated by a low-frequency triangular signal (fSUB)

An analog spread spectrum system

Bandwidth: BRF = 2(Df + fSUB)

Slide 31

Differentially BiDifferentially Bi--OrthogonalOrthogonalChirpChirp--ShiftShift--Keying (Keying (DBODBO--CSKCSK))

Kyung-Kuk LeeOrthotron Co., Ltd.

Slide 32

CONTENTS

1. INTRODUCTION2. M-ary DBO-CSK TECHNOLOGY3. GENERAL SOLUTION CRITERIA

3.1. Unit Manufacturing Cost/Complexity (UMC)3.2. General Definitions3.3. Signal Robustness3.4. Technical Feasibility3.5. Scalability

4. MAC PROTOCOL SUPPLEMENT4.1. MAC Enhancements and Modifications

5. PHY LAYER CRITERIA5.1. Channel models and payload data5.2. Size and Form Factor5.3. PHY-SAP Payload Bit Rate and Data Throughput5.4. Simultaneously Operating Piconets5.5. Signal Acquisition5.6. System Performance5.7. Ranging5.8. Link Budget5.9. Sensitivity5.10. Power Management Modes5.11. Power Consumption5.12. Antenna Practicality

6. Conclusion

Slide 33

1. INTRODUCTION■ Low Power Consumption:

- Digital Tx 0.9mW / Rx 1.13mW @ 500Kbps Data-rate

■ Signal Robustness:- Orthogonal / Quasi-Orthogonal Signal Set are deployed- Robustness: Applicable in Heavy Multi-path, SOP- Low Correlation of Signal with Existing Air-Interfaces

■ Feasibility: 2.4GHz, 5.2/5.7GHz Band- Many existing commercial RF Solutions

■ Ranging: Based on Chirp Signal (TOA/TDOA)- Precision: less then 1m @ Eb/No=24dB

■ Size & Form Factor: Smaller than SD-Memory size

■ Low Cost / Low Complexity: Tx +Rx Baseband Digital (58K gates)

■ Advanced Sleep/Wake-up Capability

Slide 34

2. M-ary DBO-CSK TECHNOLOGY

Chirp SignalChirp Signal

0( ) Re exp[( ) ] [ ( ) ( )]2

BWchirp s chirp

chirp

s t t t u t u t TTωω θ

⎡ ⎤= + + × − −⎢ ⎥

⎢ ⎥⎣ ⎦ ω

SωBWω

t

t

( )chirps t

0( ) Re exp[( ) ] ( )2

BWchirp s RC chirp

chirp

s t t t p t TTωω θ

⎡ ⎤= + + × −⎢ ⎥

⎢ ⎥⎣ ⎦

Linear Chirp: Rectangular Window

Linear Chirp: Raised-Cosine Window

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

-200 -150 -100 -50 0 50 100 150 200

0

0.2

0.4

0.6

0.8

1

Correlation Property of Chirp Signal

Am

plitu

de

Slide 35

2. M-ary DBO-CSK TECHNOLOGY

Chirp vs ImpulseChirp vs Impulse

Chirp Signal

t

t

Chirp

Correlation

Impulse Radio

t

t

Time-Hopping

Correlation

Slide 36

2. M-ary DBO-CSK TECHNOLOGY

Chirp vs ImpulseChirp vs Impulse

■ Similarities

■ Differences

Spread-Spectrum: BW >> Rb (De-spreading Gain)High Correlation Peak, Narrow Impulse/Cross-correlation width(Pulse-width of Impulse) = (Pulse-width of Cross-Correlation of Chirp) @ Same BWGreat Resolvability of Multi-path

Cross-correlation Property:- Chirp: Inherently very low side-lobe of cross-correlation- Impulse: Need very long code-sequence to realize low side-lobe of cross-correlation

Signal Voltage for Signal Power: ex. TX 0.1mW ( P = V2/2R, R = 50 ohm )- Chirp: low peak voltage ------------------------------ 0.1V (Sinusoid)- Half-Sinusoid Impulse: higher peak voltage --- 1.0V (duty-cycle 1:100)

PAPR:- Chirp: PAPR = 3dB (Theoretical Minimum value) easily achievable Eb- Impulse: PAPR = 13dB (ex. Same condition as above)

very high PAPR need high-voltage / long pulse sequence for Eb

Slide 37

3 bits/symbol

Bi-Orthogonal SymbolMapping Table (M = 8)

Bi-Orthogonal Code(01,02,03,04)

Binary(b0,b1,b2)

Decimal(m)

1 1 1 11 -1 1 -11 1 -1 -11 -1 -1 1

-1 -1 -1 -1-1 1 -1 1-1 -1 1 1-1 1 1 -1

0 0001 0012 0103 0114 1005 1016 1107 111

BiBi--Orthogonal ModulationOrthogonal Modulation

2. M-ary DBO-CSK TECHNOLOGY

Slide 38

49.4K / 145K

OO10KDeframer & Others

Rx

500 Kbps

Data-RateEstimated Complexity500Kbps / 250Kbps [gates]

BaseBand Digital250 Kbps

1.5K / 1.6K

56K152KTransceiverO

O

O

O

O

O

O

O

O

O

O

O

O56Differential Encoder

O

O

X

O

O

O

O

O

O

X

O

5K

95KFEC Decoder (r=1/2)

200Symbol Demapper

1KFramer & Others

Descrambler

Max Selector

Differential Detector

Chirp-pulse Modulator

Symbol Mapper

FEC Encoder (r=1/2)

Scrambler

154

100

39k

Common

290

13

100

154

Tx

3. GENERAL SOLUTION CRITERIA3.1. Unit Manufacturing Cost/Complexity (UMC)

Slide 39

3. GENERAL SOLUTION CRITERIA3.2. General Definitions

■ Payload bit rate and throughput- 500Kbps throughput: 293Kbps- 250Kbps throughput: 173.7Kbps

■ Error rate: see sub-section 5.6

■ Receiver sensitivity: see sub-section 5.11

■ Antenna gain: 0dBi

■ Band in use: - 2.4GHz ISM Band (10MHz Overlapping)- 5.2/5.7GHz Band (Non-overlapping)- 20MHz Bandwidth: Consists of 4 sub-chirp signals per Carrier

Slide 40

3. GENERAL SOLUTION CRITERIA3.3. Signal Robustness■ Co-existence / Interference Mitigation Technique

- Orthogonal / Quasi-Orthogonal Signal Set - High Spectral Processing Gain: Chirp- Near-Far Problem: FDM Channels (7ch @2.4GHz, 8ch @5.2GHz, 6ch @5.7GHz)

■ Interference Susceptibility- Low Cross-Correlation property with Existing Signal

■ Robustness: - Heavy Multi-path Environment- SOP

■ Low Sensitivity for Component Tolerance- Crystal : ± 40ppm

■ Mobility- Wide-band Chirp: Insensitive for Fading & Doppler Shift- Easily Maintaining Timing Sync. of Received Signal

Slide 41

3. GENERAL SOLUTION CRITERIA3.3. Signal Robustness

■ Ingress- High Processing Gain (10log(20/.5)=16dB)- Addition Processing Gain by DS-Spreading (Optional)- Low Cross-Correlation with Existing Air-Interfaces

■ Egress- Same Spectrum Mask with W-LAN @ 2.4GHz, 5.2GHz, 5.7GHz- Tx power control: 10mW / 1mW / 0.1mW (use Link Margin to reduce Interference)

Slide 42

3. GENERAL SOLUTION CRITERIA3.4. Technical Feasibility

D/A

D/A

A/D

A/D

Tx/RxSw.

DBO-CSKMOD

DBO-CSKDEMOD

MACRanging Data

Baseband DigitalRF Analog

A/D , D/A : 3~4 bits

BlockBlock--diagram of DBOdiagram of DBO--CSKCSK TransceiverTransceiver

Slide 43

3. GENERAL SOLUTION CRITERIA3.4. Technical Feasibility■ Manufacturability

- Baseband Digital Chip area: 0.75 / 1.64 mm2 (No FEC / FEC)(0.18um Technology)

■ Time-to-Market- 2005. 5. Proto-type DEMO (FPGA)- 2006. 1. Digital ASIC

■ Regulatory Impact- Availability of Spectrum: 2.4GHz, 5.2/5.7GHz Band

Globally Allowed to use (Unlicensed)- Spectrum Availability:

7 FDM CH. (2.4GHz) , 8 FDM CH. (5.2GHz) , 6 FDM CH. (5.7GHz)- Tx Power: 0.1mW / 1.0mW / 10mW optional class- Some Sensitive Frequency Band: Skip Tx Power for that Band (some SNR loss)

Slide 44fc = 2.412GHz , 2.422GHz , 2.432GHz , 2.442GHz , 2.452GHz , 2.462GHz , 2.472GHz

CSK Signals: 2.4GHz Band (20MHz BW)CSK Signals: 2.4GHz Band (20MHz BW)

-20 -10 fc 10 20 (MHz)

-50

-40

-30

-20

-10

0

Waveform Spectrum

3. GENERAL SOLUTION CRITERIA3.4. Technical Feasibility

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

Fbw = 7.0 MHzrolloff = 0.25;Fdiff = 6.3 MHz;Tc = 4.8usec

Same Spectrum with IEEE802.11bSame Spectrum with IEEE802.11b

Slide 45

3. GENERAL SOLUTION CRITERIA3.4. Technical Feasibility

88--ary DBOary DBO--CSK ModulatorCSK Modulator

1z −

Chirp-Shift-Keying(CSK)

Generator

BinaryData

P/S

S/P SymbolMapper

ModulatorDiffe

rentially

Bi-Orth

ogonal

Symbol

Scrambler FEC Encodingr=1, 1/2(option)

PRBSGEN.

SymbolRepetition

Seed

Chirp-Shift-Keying

8-ary DBO-CSK

1z −

Chirp-Shift-Keying(CSK)

Generator

BinaryData

P/S

S/P SymbolMapper

ModulatorDiffe

rentially

Bi-Orth

ogonal

Symbol

Scrambler FEC Encodingr=1, 1/2(option)

PRBSGEN.

SymbolRepetition

Seed

Chirp-Shift-Keying

8-ary DBO-CSK

Slide 46

3. GENERAL SOLUTION CRITERIA3.4. Technical Feasibility

88--ary DBOary DBO--CSK DemodulatorCSK Demodulator

Demodulator (Differential Detection)

RecoveredDataA/D

BasebandSignal

De-Scrambler

SelectLargest

De-Map P/S

DifferentialDetector

(Sub-Chirp)

De-Orthogonal

FECDecoding

TimeDe-

Spread

Demodulator (Coherent Detection)

RecoveredDataA/D

BasebandSignal

De-Scrambler

SelectLargest P/S

RakeReceiver

(Sub-Chirp)

De-Orthogonal

FECDecoding

TimeDe-

SpreadDiff.

DecodeDe-Map

Slide 47

3. GENERAL SOLUTION CRITERIA3.5. Scalability

■ Data-Rate: - 2 rates: 500Kbps / 250Kbps

■ RF Tx Power: - 3 classes: 0.1mW / 1.0mW / 10mW

■ Mobility Value:- Data: Link Margin >= 34.8dB @ 2.4GHz Band- Chirp is insensitive for Doppler Shift: very small Ranging error and BER degrade

-4

Chirp Index:

Doppler Shift:

Ex) 14 , 4.8 sec, 2.4 8.23 10

5

Ranging Error

: 8.20 /

:

f BW chirp

d c f

c f c chirp BW

BW chirp c

f T

f f v c T

T c f v f v T f

f MHz T f GHz d v

v

d

Km h d

µ

µ

µ

µ

• =

• = × = ×∆

• = ∆ × = × = × ×

= = = ⇒ ∆ = × ×

= ∆ =

-4 33 10 50 10 36 1.00 14 [ ]cm× × × =

Slide 48

4. MAC PROTOCOL SUPPLEMENT4.1. MAC Enhancements and Modifications

■ Supplement for Scalability- The proposed PHY has scalability for channelization- Scalability which is included in PHY may be added to

MAC for 15.4a PHY layer (Data-rate / Tx Power / Ranging)

■ Wake-up Mode for Power Consumption Consideration- Power consumption is of significant concern- Needing supplement to 15.4 MAC to support wake-up

mode for low-power consumption

Slide 49

5. PHY LAYER CRITERIA5.1. Channel models and payload data

■ Channel models and payload data- See sub-section 5.4 in this Document- Payload Data: 32bytes per Packet- Data-rate: 500Kbps / 250Kbps

Slide 50

5. PHY LAYER CRITERIA5.2. Size and Form Factor

SD Memory (32mm X 24 mm)

Ex)• Battery Capacity: 3V x 30mAh (324Joule)• Dimension: 10 x 2.5 (Dia. x Ht. mm)

SD Memory (32mm X 24 mm)

2.4 GHz

BasebandRFPattern Antenna

(24mm X 14mm)

Button CellButton CellBatteryBattery

5.1/5.7 GHz

Pattern Antenna(12mm X 9mm)

Baseband

RFButton CellButton Cell

BatteryBattery

Slide 51

5. PHY LAYER CRITERIA5.3. PHY-SAP Payload Bit Rate and Data Throughput

DATA Frame ACK Frame DATA Frame

TACK TLIFT588 / 1104usec 156 / 240usec

Payload: 32byte 5byte

874 / 1474 usec

TACK + TLIFT = 130usec

Payload Bit-rate:■ Data-rate: 500Kbps / 250Kbps per piconet■ Aggregated Data-rate: Max. 2Mbps (4 X 500Kbps) per FDM Channel■ FDM Channels: 7 CH. (2.4GHz), 8 CH. (5.2GHz), 6 CH. (5.7GHz)

Data Throughput:■ Payload bit-rate 500Kbps : Throughput 293 Kbps■ Payload bit-rate 250Kbps : Throughput 173.7 Kbps

Slide 52

5. PHY LAYER CRITERIA5.3. PHY-SAP Payload Bit Rate and Data Throughput

Data Frame:Payload bit-rate : 500Kbps (No FEC) / 250Kbps (FEC r=1/2)

Preamble DelimiterLength

+Rate

5Chirp 1Chirp 6Chirp 86chirp (500Kbps) or 172chirp(250Kbps)

MPDU

588 usec (1Mbps) or 1104 usec (250Kbps)(8 + 1)bit (32X8 +2) bit

ACK Frame:Payload bit-rate : 500Kbps (No FEC) / 250Kbps (FEC r=1/2)

Preamble DelimiterLength

+Rate

5Chirp 1Chirp 6Chirp 14chirp (500Kbps) or 28chirp(250Kbps)

MPDU

156 usec (500Kbps) or 240 usec (250Kbps)(8 + 1)bit (5X8 +2) bit

Slide 53

Multiple piconetMultiple piconet

5. PHY LAYER CRITERIA5.4. Simultaneously Operating Piconets

Waveform

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

0

1

I

II

III

IV

ω

ω

ω

ω

Freq. - Time

t

t

t

t

Slide 54Each of CSK Signal consists of 4 sub-chirp signals.

5. PHY LAYER CRITERIA5.4. Simultaneously Operating Piconets

Multiple piconetMultiple piconet

I

II

III

IV

ω

ω

ω

ω

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

-5000 0 50000

0.2

0.4

0.6

0.8

1

Correlation Power (For Preamble Detection)

Correlation Property between the piconetDoes not need Synchronization inter-piconet

t

CSK Signal : Quasi-Orthogonal Property

Slide 55Each of CSK Signal consists of 4 sub-chirp signals.

5. PHY LAYER CRITERIA5.4. Simultaneously Operating Piconets

I

II

III

IV

ω

ω

ω

ω

Multiple piconetMultiple piconet

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

-4000 -2000 0 2000 4000

0

0.5

1

Complex Amplitude (for Data Demod)

Correlation Property between piconetCSK Signal : Quasi-Orthogonal Property

Slide 56

5. PHY LAYER CRITERIA5.4. Simultaneously Operating Piconets

Multiple piconetMultiple piconet

I

II

III

IV

t

ω Duration of 2 Symbols (12 usec)

0.3usec 2.1usecd11 d12

0.6usec 1.8usecd21 d22

0.9usec 1.5usecd31 d32

1.2usec 1.2usecd41 d42

ωt

t

t

ω

ω

4.8 usec

SOP: Assigning Different Time-Gap between the Chirp-Shift-Keying SignalMinimize ISI for CM8 NLOS: Assign the Time-Gap between symbol more then 200nsec

Slide 57

5. PHY LAYER CRITERIA5.4. Simultaneously Operating Piconets

1 1.5 2 2.5 3 3.5 410-4

10-3

10-2

10-1

100

Dint/Dref

PE

R

System performance with 3 interf. piconet

AWGNCM8CM1CM5

0 0.5 1 1.5 2 2.5 310-4

10-3

10-2

10-1

100

Dint/Dref

PE

R

System Performance in 1 interf. piconet

AWGNCM8CM1CM5

0.5 1 1.5 2 2.5 3 3.510-4

10-3

10-2

10-1

100

Dint/Dref

PE

R

System performance with two interf. piconet

AWGNCM8CM1CM5

Available SOPs2.4GHz: 4[piconets/FDM Ch.] x 7[FDM Ch.] = 28 SOPs5.2GHz: 4[piconets/FDM Ch.] x 8[FDM Ch.] = 32 SOPs5.7GHz: 4[piconets/FDM Ch.] x 6[FDM Ch.] = 24 SOPs

Slide 58

5. PHY LAYER CRITERIA5.5. Signal Acquisition

Signal AcquisitionSignal Acquisition

DifferentialDetector

(T1)Symbol

De-MapperSelect

LargestData

A/D

DifferentialDetector

(T2)

Slide 59

5. PHY LAYER CRITERIA5.5. Signal Acquisition

Miss Detection Probability

1400 1500 1600 1700 1800 1900 2000 2100 2200

10-5

10-4

10-3

10-2

10-1

In AWGN, at FA=3.2x10-5, TxPower=10mW

Distance : meter

Pm

2 Chirp Symbols3 Chirp Symbols4 Chirp Symbols

Preamble Detection

Slide 60

5. PHY LAYER CRITERIA5.6. System Performance

Data Rate : 500kbps

10 12 14 16 18 20 2210-4

10-3

10-2

10-1

100

Eb/No

PE

RSystem Performance

AWGNCM8CM1CM5

Slide 61

5. PHY LAYER CRITERIA5.7. Ranging

Timing DetectionTiming Detection■ Coarse Timing Detection

- Peak of Differential Detection (Averaging over 4 or more Symbols)

■ Fine Timing Detection- Cross-Correlation of Sampled Input Signal- Fine Timing by Interpolation (Fraction of Sampling-Clock Resolution < 1nsec)- Averaging over 4 or more Symbols- Less than 1m Ranging Resolution @ Eb/No >= 24dB

Arbitrary Sampling Instant

Detected TimingDetected TimingPeak

Edge

Slide 62

1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 2 81 0

0

1 0 1

1 0 2

E b /N o (d B )

time

erro

r dev

iatio

n (n

sec)

5. PHY LAYER CRITERIA5.7. Ranging

Timing-error Variance (Chirp BW: 20MHz)

■ TDA / TDOA Based Ranging with Chirp Signal

■ Estimation Precision: < 1m @ Eb/No greater than 24dB

Slide 63

5. PHY LAYER CRITERIA5.8. Link Budget

dBm-94.5 -94.5 -94.5 Proposed Min. Rx Sensitivity Level

dB27.4 28.2 34.8 Link Margin (M=Pr-Pn-S-I) @ 30m

dB333Implementation Loss(I)

dB12.512.512.5Minimum Eb/No(S)

dBm-110.0 -110.0 -110.0 Average noise power per bit(Pn=N+Nf)

dB777Rx Noise Figure(Nf)

dBm-117.0 -117.0 -117.0 Average noise power per bit

dBm-67.1 -66.3 -59.7 Rx power(Pr = Pt+Gt+Gr-L1-L2(dB))

dBi000Rx antenna gain(Gr)

dB29.5 29.5 29.5 path loss at d m(L2=20log10(d))

m 303030distance

dB47.6 46.8 40.2 Path loss at 1meter(L1=20log10(4pifc'/c))

GHz5.75.20 2.44 fc' = sqrt(fminfmax) -10dB

dBi000Tx antenna gain(Gt)

dBm101010Average Tx Power(Pt)

mW101010Average Tx Power(Pt)

kbps500500500peak payload bit rate(Rb)

UNII(5.7GHz)UNII(5.2GHz)ISM(2.4GHz) Parameter

Slide 64

5. PHY LAYER CRITERIA5.9. Sensitivity

CM5

CM1

CM8

AWGN

-86.5dBm

-87dBm

-85.5dBm

-94.5dBm

Rx Sensitivity level(500kbps)

Bandwidth: 20MHz (2.4GHz Band)

Slide 65

5. PHY LAYER CRITERIA5.10. Power Management Modes

■ Low-power Mode with Advanced Wake-up– The proposed PHY has differentially bi-orthogonal detection

and correlatively independent chirp-pulse waveform for multiple piconet=> Low-power is achieved by advanced wake-up that the only

desired group of nodes are called and the other nodes canestimate wake-up time from sleep state

=> Reducing Duty-Cycle and Extending Battery-life– This is compliant to “power consumption considerations” of

802.15.4 standard, and the mode of operation for advanced wake-up may be added to this standard

Slide 66

5. PHY LAYER CRITERIA5.11. Power Consumption

■ RF: 140mW for Tx (@10mW RF Power), 35mW for Rx

■ Baseband (BB) Digital: 0.9mW for Tx , 1.13mW for Rx

■ RF part consume lot more power than Baseband Digital- Power Reduction of RF ASIC is Essential (C-MOS)

■ Idea for Operating Power Saving:- Use Max. Data-rate mode: shorter time for Tx Data- Sleeping: Longer Time- Save Power: by reducing active time of RF

■ Further Reduction of Power Consumption- Apply 0.13um / 0.09um Technology for ASIC (RF / Baseband)

Slide 67

5. PHY LAYER CRITERIA5.11. Power Consumption

Rx

Tx 141 mW141 mW56KTotal

37.5 mW5.24 mm2152K

36.1 mW4.35 mm2

0.52 mW0.06 mm21.6K0.48 mW0.04 mm21.5KTx

10 mW0.3 mm2-10 mW0.3 mm2-Common

130 mW1.7 mm2-130 mW1.7 mm2-Tx + D/A

5K

49.4K

-

Logic

5 uW

0.42 mW

2.08 mW

25 mW

Power

1.5 mm2145K0.71 mW0.63 mm2Rx

250Kbps (FEC: r=1/2)500Kbps (No FEC)

5 uW

0.42 mW

25 mW

Power

0.08 mm2

1.6 mm2

Die Area

Common

Rx + A/D

Deep Sleep

Baseband@ Sampling-rate:

40MHz

RF@ Tx Power:

10mW

0.08 mm25K

1.6 mm2-

Die AreaLogic

Target Library : 0.18 um Technology

■ Power Consumption for Average Throughput 1 Kbps (w/o FEC)- PTX : 141[mW] / 293 = 481 [uW]- PRX : 36.1[mW] /293 = 123 [uW]

■ Battery: 324[Joule] for Button Cell (10mm D. X 2.5mm H) / 12,000[Joules] for AA Alkaline Cell- (PTX + 50 X PRX)/51 = 130[uW] ----- (Assume TTX : TRX = 1:50 duty-cycle for sensor node)- Battery Life TB = 324/130e-6/3600/24 = 28.8 days Continuously (Button Cell)- Battery Life TB = 12000/130e-6/3600/24/365 = 2.93 years Continuously (AA Alkaline Cell)

Slide 68

5. PHY LAYER CRITERIA5.12. Antenna Practicality

■ Antenna Size- less than SD-Memory size: 24mm X 14mm @2.4GHz

12mm X 9mm @5.2/5.7GHz

■ Frequency / Impulse Response- Almost Flat Freq. Response: Narrow-band

■ Radiation Characteristics- Isotropic: 0dBi

Slide 69

6. Conclusion■ Low Power Consumption: Digital Baseband Tx 0.9mW, Rx 1.13mW

- Power Consumption is heavily depend on RF-chip.

■ Signal Robustness:- Orthogonal / Quasi-Orthogonal Signal Set - Robustness: Tolerance for Heavy Multi-path / SOP, - Low Correlation with Existing Air-Interfaces

■ Feasibility: 2.4GHz ISM Band- Existing commercial RF Solutions- 2.4GHz / 5GHz band is allowed for unlicensed operation- Low Voltage Operation: Low PAPR

■ Ranging: Based on Chirp Signal (TDA / TDOA)- Precision: less then 1m (Standard Deviation) @Eb/N0 = 24dB

■ Size & Form Factor: Less than SD-Memory size

■ Low Cost / Low Complexity: Tx +Rx Baseband Digital (56K gates)

■ Support Advanced Sleep / Wake-up Capability

■ Orthotron will pursue opportunities for future collaborations anOrthotron will pursue opportunities for future collaborations and mergingd merging