2006pesc zz presentation

7/28/2019 2006pesc Zz Presentation

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Topology and Analysis of aNew Resonant Gate Driver

Presented and Authored By:Presented and Authored By:

ZhiliangZhiliang ZhangZhang

CoCo--authors:authors:Zhihua Yang,Zhihua Yang, ShengShengYe and Dr. YanYe and Dr. Yan--Fei LiuFei Liu

QueenQueens Power Groups Power Group

www.QueensPowerGroup.comwww.QueensPowerGroup.com


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Outline

Introduction

Proposed Resonant Gate Driver andOperation

Loss Analysis and Optimization Design

Experimental Results

Conclusion


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Introduction




Conclusion


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Conventional MOSFET Driver

DischargePath

MOSFET Driver

Gate Loss

SGSggate fVQP =

MOSFET,or BJT

transistors

Power MOSFET

SwitchingLoss

Hard Switching Waveforms

sfallriseDDS

switching fttIV

P +

)(2


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Switching Loss: Common

Source Inductance

Common source inductance VD

iDL LD

LS

G

S

D

CGS

CGDCDS

gfs(vGS-Vth)

RG

VDrive

M1

iD

Equivalent circuit of MOSFET switchingtransition (turn-on)

Buck converter with parasitic inductors


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Switching Loss: Common

Source InductanceLs=0 Ls=2nH

VD=12V, IL=20A, fs=1MHz, MOSFET: IRF7821

Switching loss increases significantly due tocommon source inductance!

9ns 18ns

5

10

15

20

010 20 30 40 500

Time(ns)

iD (A)

vDS (V)

vGS (V)


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Resonant Gate Drive

TechniquesLimitations of voltage source driver:

No gate charge energy recovered

Low switching speed and high switching lossdue to common source inductance

Resonant gate driver techniques:9Many good circuits proposed since 1990s,

but generally unused

9Existing methods emphasize gate energysavings, but ignore potential switchingloss savings


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Introduction




Conclusion


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Proposed Dual Channel High-

Side and Low-Side Gate Driver

Key waveforms

+

-

Vin

Q1

Q2

LfCf

RLd

Vo

S1 S2

S3 S4

C1

Cg1

Cg2

D1

Lr

Cb

Vc

Resonant Gate Driver

iLr


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Before t0

Key waveforms

+

-

Vin

Q1

Q2

LfCf

RLd

Vo

S1 S2

S3 S4

C1

Cg1

Cg2

D1

Lr

Cb

Vc

iLr


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Turn-offQ2: [t0, t1]

Key waveforms

+

-

Vin

Q1

Q2

LfCf

RLd

Vo

S1

S2

S3 S4

C1

Cg1

Cg2

D1

Lr

Cb

Vc

iLr


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Turn-on Q1: [t1, t2]

Key waveforms

+

-

Vin

Q1

Q2

LfCf

RLd

Vo

S1

S2

S3 S4

C1

Cg1

Cg2

D1

Lr

Cb

Vc

iLr


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Introduction




Conclusion


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Driver Loss Analysis

The conduction loss ofS1-S4

)(2

_2)(2

_141_ 22 ondsRMSsondsRMSssscond RIRIP +=R

ds(on)is the on-resistance ofS

1-S

4

The resonant inductor loss

corecopperind PPP +=

The loss of MOSFET mesh resistance RG

sswpkLrGsswpkLrGRG ftIRftIRP += 2_2

21_2

1 22

tsw1 and tsw2 are the switching time, ILr_pk is the peak current of resonant inductor

The loss of gate charges of switches S1-S4

ssgssgGate fVQP = __4


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Vcc Selection of Resonant

Gate Driver

Vc=5V

Vc=12V

Vin=12V; Io=20A; fs=1MHz;

Q1: IRF7821(30V, RDS(on)=9m@VGS=6V); Q2: FNS7088(30V, RDS(on)=3.5m@VGS=6V);

S1-S4: FDN335N(20V N-channel, RDS(on)=0.07@VGS=4.5V); Lr=2.2uH.

Vc=12VPreferred

Control FET&Synchronous FET


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)()()( GswitchingGcircuitG IPIPIF +=

3. The Objective function is establishedby adding switching loss and theresonant gate driver loss together

IG

=1A

1. Switching loss Pswitching(IG) as functionof driven current IG is calculated

2. Total loss Pcircuit(IG) of the resonantgate drive circuit as function of drivencurrent IG is calculated

Gate Charge Current IG

Selection


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Conventional Driver vs.

Resonant Driver

Loss(W)

Cond

uctio

n

Turn

-on

Turn

-off

Gate/R

GD

cirut

Body

dio

de

Vin=12V; Vo=1.5V; Io=20A; fs=1MHz;

Control FET: IRF7821(30V, RDS(on)=9m@VGS=6V)

Syn FET: FNS7088 (30V, RDS(on)=3.5m@VGS=6V)


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Introduction




Conclusion


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Experimental Results: Fast

Switching Speed

Gate drive signal and drain-sourcevoltage (control FET)

Resonant inductor current and drain-source voltage (Synchronous FET)

Vin=12V; Io=20A; fs=1MHz; Control FET: IRF7821;Syn FET: FNS7088

Fast speed

No miller plateau


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Experimental Results:

Reduced Dead Time

Resonant gate driver

Vin=12V; Vo=1.5V; Io=20A; fs=1MHz; Control FET: IRF7821;Syn FET: FNS7088

Conventional gate driver

(TPS2832 TI)


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Experimental Results: Loss

Savings

Ploss(W)

4.5W Loss Reduction@Vo=1.5V/20A(15% of the output power)


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Introduction




Conclusion


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Conclusion

A New Resonant Driver Proposed9 Switching Loss Reduction9 Immunity to Common Source Inductance9 Gate Energy Recovery9 ZVS for Driver Switches9 High Cdv/dt Immunity (Low Impedance)

9 Reduced Body Diode Conduction Time

Loss Analysis and Design ProcedurePresented

4.5W Loss Reduction@Vo=1.5V/20A/1MHz(15% of outputpower)


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Thank You For Your TimeThank You For Your Time

Other Resonant Gate Drive Material at:Other Resonant Gate Drive Material at:

www.QueensPowerGroup.comwww.QueensPowerGroup.com

2006pesc zz presentation

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