2016 ELECTRONIC HIGHLIGHTS

Electronic group :

Multi-project:

- 4 electronic engineers: Daniel, Stéphane, Yannick

- 2 technical assistants: Gaby, Javier

CTA electronic engineer: Isaac

TT-PET microelectronic engineer: Pier Paolo

B-Mind software engineer (short mission): Olivier

Activities

Engineering activities: • PCB design (Schematics / Layout - Cadence) on

analog, digital, HF & EMC architectures

• Analog/Digital ASIC design (Cadence)

• FPGA Design (VHDL/Verilog , Xilinx/Altera)

• Analog & Digital Simulation (PSpice/modelsim…)

• Embedded µC programming (C/C++, real-time)

• PC programming (C++, C#, VB, SQL) for readout,

test benches & database

• “Mechatronics” approach with mechanical group

Workshop activities: • PCB prototypes manufacturing

• Boards assembly

• Cabling

• Bonding

• Testing & calibration

• Production programming

• Database parts creation & stock

December 2016 Electronics Highlights 2/10

Main characteristics: • VATA interface

• 2 Trigger inputs, 1 Trigger + 1 Busy output

• 12-bits 1-ch ADC

• ALTERA Cyclone V FPGA

• Unige USB3 firmware + software interface for readout

& slow control

HERD: Acquisition board

Highlights 2016 • FPGA Firmware done

• Hardware corrections

• VATAs & USB3 I/F works correctly

• PC software done by physicists based on

Unige C# library

• Board successfully used during test beam

in August

December 2016 Electronics Highlights 3/10

Following 2017 : 2nd version: • Improvement of the VATA interface

• faster 12-bits ADC implemented

• Improvement of the USB interface

• 2 ASIC interfaces : VATA + new SIPHRA

Cyclone

V FPGA

USB µC

VATA

I/F

NA61: 32-channel DRS4 Acquisition Board

December 2015 Electronics Highlights 4/10

Features: • 6U VME Form Factor with custom backplane

• 32 input channels with low-power analog Front-End stage

• 4 DRS4 chips

• 12-bit 8-channel ADC

• Altera Cyclone V FPGA

• USB 3.0 Microcontroller (lab tests)

• RJ45 LVDS Interface to high speed DDL Link

32-ch Analog

Front-End Stage

4x DRS4 12-bit

8-ch ADC FPGA

USB3 I/F

DDL link I/F

On-Board Voltage and Timing Calibration

USB 3.0

Connector

Cyclone V

FPGA

ADC

USB µC

DRS4

(4x)

DDL

link I/F

32-ch Analog

Front-End Stage

External Ref. Clock (DRS4 sampling)

2x 16-input

Connectors

External Timing

Calibration Connector

Trig In

Busy out

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

100 110 120 130 140 150

Am

pli

tud

e [

V]

Time [ns]

uncalibrated

U2

I/F

CTA: Hardware + firmware

December 2015 Electronic Highlights 5/10

Housekeeping board: • Monitor the environment inside the camera to assure the

camera electronics integrity:

• 4 x Temperature probes PT-100

• 4 x Humidity + Temperature sensors

• 2 x Atmospheric pressure sensors

• 16 x Cooling fans rotor locked signal monitoring

• SW programmable alarm conditions on minimum and

maximum sensors limits and logic combinations

• Provides power to the camera pointing LEDs

• Integrated CAN bus and safety PLC RS-422 interface

• Lightning surge protection implemented

• Fully calibrated

Others activities: • PDP Boards upgrade & launch for 2nd camera

production (mechanical improvement & lightning protection)

• Camera Shutter Driver based on CPLD with motor

current limiter & lightning protection (2 motors)

• CAN to UDP Ethernet gateway (embedded firmware for

Xilinx softcore µBlaze processor within Trigger Board FPGA)

FAN ctrl I/F

4 x PT-100 (SM58 shure I/F) 2 x Pressure sensor 4 x H+T sensor

Pointing leds

CAN

PLC Alarms µC

24V IN

PLC RS-422

Camera Shutter Driver Prototype

CPLD

PLC

I/F

2 Limit Switch I/F

2 Motorhead

I/F

Insulated power supply

Guitar sat’ limits

TT-PET: Readout ASIC

December 2015 Electronic Highlights 6/10

ASIC 3

4007 config. bits

ASIC Features: • Photo-current read

• Conversion to digital pulse

• Event timing acquisition

• Data I/F to central event-processing unit

Analog Channel: • BJT input transistor with Kate MOS feedback

• High gain/ Low noise : 95 mV/fC / 696.4 e-

• Peak time: 1.3 ns

• Small power consumption: 135 µW

• Small footprint, highly configurable

Digital logic: • Incoming data readout with/without trigger

• Daisy chain arbiter + common bus cmd read

• External registers program

• I/O limited for easier system integration

• Scalable architecture (# chips, datawords)

ASIC 2 ASIC 1

TOWER CONTROL

FPGA

DOUT / CLKOUT / TRIG

CLK-SYNC

ASIC N …

Scanner mock-up (Based on Elvis’ Mic)

Asic prototype Layout

System overview

Input bloc diagram

Baby-Mind : FEB FPGA hardware & firmware

December 2015 Electronic Highlights 7/10

VHDL Library

Hardware: • Improve analog stage (dynamic range)

• Improve analog power supplies (noise)

Firmware: • TDC (rising & falling) @ 2.5ns

• 96-ch 12-bits Lo-Gain + Hi-Gain Analog

• USB3 readout with VHDL Unige lib. for slow

control + 2Gb/s readout and chain mode

Tests: • Successfully tested during 2 beam tests

campaign in summer (4 FEB in //, 384-ch)

2017: • New hardware with VME format for mini-

crate integration

• Firmware upgrade for full FEB chain &

common clock synchronisation

• New overall cabling with 32-ch custom

connector on coaxial cables

• Full production (4000-ch, 55 FEB)

YMCA ASICs

Aria V.People

FPGA

12-bits

ADC

USB µC

Gigabit

chain

Application

Unige C# Library: USB3 readout software

December 2015 Electronic Highlights 8/10

App: - MainWindow - BoardTab - Menu - Scripting

Common USB3 projects library

Board: - BoardLink - Protocol - FirmwareUpdate - ReadoutThread - USB.Linux - USB.Win -

Software architecture (C# on Win7 & Linux using GTK)

4007 config. bits

Config: - Version manager - Config Data - Config Descriptor - Config Utils - JSON converter - XML converter -

Graphics: - BoardTab - Histogram - Lib Menus - Scripting -

Gui tools Scripting Command interpreter

- Settings - DaqTools - FPGATools - iTunes

JSON HW & GUI descriptor

Tools

Lib Features: • Independent of hardware boards

• Provides all config + protocol + GUI +

scripting tools

• Linux & Windows compatibility

• Based on GTK

Application; • Described hardware & GUI presentation

with JSON descriptor file

• Used all Lib functionalities

• No compilation nor code if no specific

features

• Add specific features if required (menu,

gui, scripting functions, settings)

Used on B-Mind & HERD readout

NIRVANA

Workshop

December 2015 Electronic Highlights 9/10

Machines:

• New :

• LPK PCB Plotter for in-house

PCB manufacturing

• 2017 planned :

• Stencil placer & SMD placement

semi-automatic workshop

Activities: • In-house PCB manufacturing

• Cabling & boards assembly (CTA, PET, B-Mind, HVCMOS…)

• Small board design & layout (prototypes, adapters, tests)

• Functional tests, production programming (CTA)

• Bonding (HVCMOS, PET)

• Components stock (database)

Reflow oven

Fine pitch SMD rework

HVCMOS bonding PET HF amplifier

Cable

printer

CTA camera cabling

New PCB Plotter

B-Mind 32-ch coax connector

CTA shutter driver PET bonding

Projects :

Baby Mind: New VME hardware, FPGA firmware & PC software finalization, 4000 coax. on cabling PCBs

Full production (55 FEB, 600 cabling PCBs, 4000 SiPM PCBs) for beam tests in June

NA61: 32-ch DRS4 acquisition board FPGA firmware with DDL I/F, Clock/trigger board tests

Full production (120 DRS4 boards)

CTA: 2nd camera production (132 preamplifiers + 132 slow control boards) + functional testers upgrade

Housekeeping board + shutter board installation, EMC & lightning tests & qualification

Trigger board FPGA firmware ?

HERD: New board for VATA/SIPHRA ASIC qualification

ATLAS: SLIM prototypes (Stave flex, End of Stave board, Module adapters with PSPP chip)

PET: TDC ASIC design

ASIC test boards, HF amplifier, bonding

Coming next in 2017

10/10 December 2015 Electronic Highlights

Season’s greetings

Joyeuses Fêtes