2.1 2.1 using a custom-built hdl for printed circuit b d cphdl.sourceforge.net/2.1/pubs/pcb west...
TRANSCRIPT
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USING A CUSTOM-BUILT HDL FOR PRINTED CIRCUIT BOARD DESIGN
CAPTURE Brent Nelson Brad Riching
Josh Mangelson Dept. of Electrical and Computer Engineering
Brigham Young University
PCB West Presentation September 2012
2.1 2.1
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Sponsorship
Sandia National Laboratories is a multi-
program laboratory managed and operated by Sandia Corporation, a wholly owned
subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National
Nuclear Security Administration under contract DE-AC04-94AL85000. SAND
Number : 2012-6638 C 2
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Who Are We?
• Dr. Brent Nelson (Professor) • Brad Riching (MS student) • Richard Black (BS student) • Joshua Mangelson (BS student)
– Dept. of Electrical and Computer Engineering – Brigham Young University
3
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Overview
• Why HDL’s for PCB design capture?
• PHDL – An HDL for PCB design capture – The language – The tool flow
• Examples of PHDL board designs
• Examples of 3rd party support tools and utilities
• Links to PHDL open source community
• Future Work
4
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MOTIVATION: HDL’S FOR PCB DESIGN CAPTURE
Part 1
5
2.1
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Graphical Schematic Entry
• Imitates manual drawing – Intuitive – Spatial information + human visual system è
understanding – Current industrial practice
• Would seem to be the best method ! QED…
6
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HDL’s for PCB Design
• Design capture – Capture designer’s intent – Define design
components and connectivity
– Currently done with schematic tools
• Physical design – Physical design rules – Electrical considerations
(voltage, current, capacitance, inductance)
– Best done using current layout tools & methods
7
netlist
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Schematic Scalability
8
Note: this entire page is mainly the symbol for a single 784 pin FPGA It is one of 20-30 `pages in the overall design.
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Drawing a Schematic Net
• subroutine drawSchematicNet() { foreach pin in net { 1. pan to page and area of pin 2. zoom in on pin 3. attach wire stub to pin 4. add textual name to wire stub 5. zoom back out 6. repeat }
• How many mouse clicks per pin? – 5? 10? 20? 30? (many)
• How many nets in a design?
• How do you do a design review? – From printed schematics… – From a schematic design tools…
9
So, just how again is this graphical approach helping me?
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Design Change Tracking
• Design changes between two versions? % diff a.sch b.sch Binary files a.sch and b.sch differ %"
10
That’s not very helpful…
Need a mechanism for comparing design versions and documenting individual design changes Source code control systems (SCCS’s) have done this for years for software
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Design Sharing
• Sharing a design amongst a team – Divide and conquer
• Design reuse – How do you reuse portions of a schematic
between designs?
11
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Schematic Tools: Proprietary Source
• Schematic design files: – Protected, binary formats – Specialized tools just to view source…
• Edit, manipulate, analyze?
• If you have the wrong version of proprietary CAD tool… – Cannot even open the schematic to view
• Discourages/prevents 3rd party tools 12
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INTRO TO PHDL Part 2
13
2.1
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What is PHDL?
14
Schematic Capture produces netlist
PCB Layout interprets netlist
Bill of Material,
other ancillary
data
netlist
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What is PHDL?
15
Schematic Capture produces netlist
PCB Layout interprets netlist
PHDL Source Code
PHDL compiler
Bill of Material,
other ancillary
data
netlist
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PHDL: A First Example
• Our example circuit:
16
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
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PHDL: A First Example
• Four types of devices
• Plus some wires
17
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
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Defining Devices
18
R?
M0805
1
2
value=120
device Resistor { attr REPREFIX= “R”; attr FOOTPRINT = “M0805”; attr LIBRARY = “complib”; attr VALUE= “120”; pin a = {1}; pin b = {2}; } // Comments are allowed like this. // Compiler will auto-assign full // refDes’s
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device SevenSeg { attr REFPREFIX = “LD”; attr FOOTPRINT = “SA08-21”; attr LIBRARY = "myLib"; // Multi-bit pins are allowed pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[2:0] anode = {4,12,17}; }
Defining Devices: Multi-Bit Pins
19
2
15
13
11
5
3
14
10
4
12
17
SA08-21
LD?
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Creating The Design
20
// Define the design and // give it a name design sevenSeg { // Define the wires net gnd, vcc; // Define a multi-bit wire net[1:8] segs, r2sw;
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
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// Define the design and // give it a name design sevenSeg { // Define the wires net gnd, vcc; // Define a multi-bit wire net[1:8] segs, r2sw;
Creating The Design: Nets
21
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
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Creating The Design: Nets
22
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
// Define the design and // give it a name design sevenSeg { // Define the wires net gnd, vcc; // Define a multi-bit wire net[1:8] segs, r2sw;
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Creating The Design: Multi-Bit Nets
23
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
// Define the design and // give it a name design sevenSeg { // Define the wires net gnd, vcc; // Define a multi-bit wire net[1:8] segs, r2sw;
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Creating The Design: Multi-Bit Nets
24
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
// Define the design and // give it a name design sevenSeg { // Define the wires net gnd, vcc; // Define a multi-bit wire net[1:8] segs, r2sw;
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Creating The Design: Instancing Devices
25
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
inst source of Battery { pos = vcc; neg = gnd; } // Create an instance of the // “Battery” device // Wire it up: // Port “pos” -> net “vcc” // Port “neg” -> net “gnd”
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26
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
inst segment of SevenSeg { segments = segs; anode = <vcc>; } // Instance the seven // segment chip // Tie pins segments[1:8] -> // net segs[1:8] // Tie all the “anode” pins // to “vcc”.
Creating The Design: Instancing Devices
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27
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
inst(1:8) swArray of Switch { combine(a) = r2sw; combine(b) = segs; }; // Make an array of 8 // “Switch” instances // The instances will be // numbered from 1 to 8 // For arrays, use (…)’s // For nets and pins, // use […]’s
Creating The Design: Instance Array
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inst(1:8) swArray of Switch { combine(a) = r2sw; combine(b) = segs; } // Take all the “a” pins, // combine them left to right // into a bus, and wire them // to the “r2sw” net // Thus, swArray(1:8).a -> r2sw[1:8]
Creating a Design: Wiring Up Pins
28
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
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inst(1:8) swArray of Switch { combine(a) = r2sw; combine(b) = segs; } // Take all the “a” pins, // combine them left to right // into a bus, and wire them // to the “r2sw” net // Thus, swArray(1:8).a -> r2sw[1:8]
Creating a Design: Wiring Up Pins
29
R1 120 S1
R2 120 S2
R3 120 S3
R4 120 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 120 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
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Creating a Design: Setting Inst Attributes
30
R1 100 S1
R2 100 S2
R3 100 S3
R4 100 S4
R5 120 S5
R6 120 S6
R7 120 S7
R8 75 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
inst(1:8) rArray of Resistor { this(1:4).VALUE = “100”; this(8).VALUE = “75”; combine(a) = r2sw; b = gnd; } // Set some “value” // attributes to “100”. // Set one “value” // attribute to “75”. // Remember, the Resistor // device has a default // “value” of “120”
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Creating a Design: Wiring Up Pins
31
R1 100 S1
R2 100 S2
R3 100 S3
R4 100 S4
R5 100 S5
R6 100 S6
R7 100 S7
R8 100 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
inst(1:8) rArray of Resistor { VALUE = “120”; combine(a) = r2sw; b = gnd; } // Take each “b” pin and // individually tie it to the “gnd” net.
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The Complete Example Design (a)
32
device Resistor { attr REFPREFIX = "R"; attr FOOTPRINT= "M0805"; attr LIBRARY = "complib"; attr VALUE = "120"; pin a = {1}; pin b = {2}; } device Switch { attr REFPREFIX = "SW"; attr FOOTPRINT= "MS243"; attr LIBRARY = "complib"; pin a = {1}; pin b = {2}; }
device Battery { attr REFPREFIX = "G"; attr FOOTPRINT= "1V60R"; attr LIBRARY = "complib"; attr VALUE = "9V"; pin pos = {2}; pin neg = {1}; } device SevenSeg { attr REFPREFIX = "LD"; attr FOOTPRINT= “SA08-21"; attr LIBRARY = “myLib"; pin[1:8] segments = {2,15,13,11,5,3,14,10}; pin[1:3] anode = {4,12,17}; }
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The Complete Example Design (b)
33
R1 100 S1
R2 100 S2
R3 100 S3
R4 100 S4
R5 100 S5
R6 100 S6
R7 100 S7
R8 75 S8
2 15 13 11
3
10 14
5
4 12 17
+
-‐
LD1
SA08-‐21
G1
design ssControl { net gnd, vcc; net[1:8] segs, r2sw; inst source of Battery { pos = vcc; neg = gnd; } inst segment of SevenSeg { segments = segs; anode = <vcc>; } inst(1:8) swArray of Switch { combine(a) = r2sw; combine(b)=segs; } inst(1:8) rArray of Resistor { this(1:7).VALUE = “100”; this(8).VALUE = “75”; combine(a) = r2sw; b = gnd; } }
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Compilation Flow
34
PHDL source
Output files
Command line switches
PHDL Compiler
• Netlist • Bill of Materials • Component List • Layout Directions • XML • Tool-specific Scripts
$java –jar phdlcomp.jar srcFolder [switches]
Eclipse flow: Compiler runs every time you save your design.
Command line flow
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A Netlist
35
!PADS-POWERPCB-V9.0-MILS! NETLIST FILE FROM PADS LOGIC V9.3 *PART* G1 complib@1V60R LD1 complib@MS243 R1 complib@M0805 R2 complib@M0805 R3 complib@M0805 R4 complib@M0805 R5 complib@M0805 R6 complib@M0805 R7 complib@M0805 R8 complib@M0805 SW1 complib@MS243 SW2 complib@MS243 SW3 complib@MS243 SW4 complib@MS243 SW5 complib@MS243 SW6 complib@MS243 SW7 complib@MS243 SW8 complib@MS243
! *CONNECTION* *SIGNAL* GND G1.1 R1.2 R1.2 R2.2 R2.2 R3.2 R3.2 R4.2 R4.2 R5.2 R5.2 R6.2 R6.2 R7.2 R7.2 R8.2 *SIGNAL* R2SW[1] SW1.1 R1.1 *SIGNAL* R2SW[2] SW2.1 R2.1 *SIGNAL* R2SW[3] SW3.1 R3.1 *SIGNAL* R2SW[4] SW4.1 R4.1 *SIGNAL* R2SW[5] SW5.1 R5.1 *SIGNAL* R2SW[6] SW6.1 R6.1 *SIGNAL* R2SW[7] SW7.1 R7.1 *SIGNAL* R2SW[8] SW8.1 R8.1
*SIGNAL* SEGS[1] LD1.2 SW1.2 *SIGNAL* SEGS[2] LD1.15 SW2.2 *SIGNAL* SEGS[3] LD1.13 SW3.2 *SIGNAL* SEGS[4] LD1.11 SW4.2 *SIGNAL* SEGS[5] LD1.5 SW5.2 *SIGNAL* SEGS[6] LD1.3 SW6.2 *SIGNAL* SEGS[7] LD1.14 SW7.2 *SIGNAL* SEGS[8] LD1.10 SW8.2 *SIGNAL* VCC G1.2 LD1.4 LD1.4 LD1.12 LD1.12 LD1.17 *END*
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A Bill of Materials
• comma-separated file – Import into Excel to view
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QUANTITY, NAME, REFDES, LIBRARY, FOOTPRINT, VALUE 1, Battery, G1, complib, 1V60R, 9V 1, SevenSeg, LD1, complib, MS243, 8, Switch, SW1; SW2; SW3; SW4; SW5; SW6; SW7; SW8, complib, MS243, 8, Resistor, R1; R2; R3; R4; R5; R6; R7; R8, complib, M0805, 100
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Targeted Design Flows
37
EAGLE PCB Mentor Graphics PADS
Others coming soon…
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PHDL: DIGGING A LITTLE DEEPER…
Part 3
38
2.1
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Array indexing • Can instantiate using any
indexing desired
• Uses notion of left-to-right ordering
39
net[1:8] segs; // Leftmost wire à “segs[1]” // Rightmost wire à“segs[8]” inst(1:8) swArray of Switch { … } // Leftmost Switch à “this(1)” // Rightmost Switch à “this(8)” <OR> inst(7:0) swArray of Switch { … } // Leftmost Switch à “this(7)” // Rightmost Switch à “this(0)”
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Wiring Up Ports and Nets (1)
40
R1
R2
R3
R4
R5
R6
R7
R8
net1[1]
net1[2]
net1[3]
net1[4]
net1[5]
net1[6]
net1[7]
net1[8]
gnd
net gnd; net[1:8] net1, net2; inst(1:8) res of Resistor { combine(b) = net1; }
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Wiring Up Ports and Nets (2)
41
R1
R2
R3
R4
R5
R6
R7
R8
net1[7]
net2[2]
net1[5]
net2[3]
net1[3]
net2[4]
net1[1]
net2[1]
gnd vcc
net gnd, vcc; net[1:8] net1, net2; inst(1:8) res of Resistor { this(1:4).a = gnd; this(5:8).a = vcc; combine(this(1,3,5,7).b) = net1[7,5,3,1]; combine(this(8,2,4,6).b) = net2[1:4] } // In all cases, indexing // is viewed left-to-right
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Wiring Up Ports and Nets (3)
42
R1
R2
R3
R4
R5
R6
R7
R8
n1
x2
x1
n2
net n1, n2, x1, x2; inst(1:8) res of Resistor { combine(this(1:4).b) = n1 & x2 & x1 & n2; } // The RHS of the above assignment // is a “concatenation”
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PHDL Packages (1)
• Declare devices to be in a package
• Must use package name when instantiating.
• Allows same device in multiple device library files without name collision.
43
package myParts { device Resistor { attr REFPREFIX = “R”; … } } design sevenSeg { inst(1:8) rArray of myParts.Resistor { … } }
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PHDL Packages (2)
• Declare devices to be in a package
• Import the package contents.
• Avoids having to use qualified names.
44
package myParts { device Resistor { attr REFPREFIX = “R”; … } } import myParts.*; design sevenSeg { inst(1:8) rArray of Resistor { … } }
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PHDL Subdesigns (1)
45
rc1
in out
gnd P1 open
Subdesigns have port definitions. Subdesigns can be instanced like a device but with ‘subinst’ keyword. Subdesigns can be array instanced just like devices.
subdesign rc { port gnd, in, out; inst res of Resistor { a = in; b = out; }
inst cap of Capacitor { pos = out; neg = gnd; } }
design myCircuit { net i, o, gnd, vcc; subinst rc1 of rc { in = i; out = o; gnd = gnd; } inst P1 of Connector { p[0:2] = i & gnd & o; p[3] = open; } }
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PHDL Subdesigns (2)
46
rc1
in out
gnd P1 open
You can reach down into hierarchy using “.” notation to change lower level attributes. No limit to levels deep you can go.
subdesign rc { port gnd, in, out; inst res of Resistor { a = in; b = out; }
inst cap of Capacitor { pos = out; neg = gnd; } }
design myCircuit { net i, o, gnd, vcc; subinst rc1 of rc { in = i; out = o; gnd = gnd; res.VALUE = ”66”; } inst P1 of Connector { p[0:2] = i & gnd & o; p[3] = open; } }
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rc1
PHDL Subdesigns (3)
47
rc1
in out
gnd P1 open
Can make array of subdesigns…
subdesign rc { port gnd, in, out; inst res of Resistor { a = in; b = out; }
inst cap of Capacitor { pos = out; neg = gnd; } }
design myCircuit { net[0:1] i, o; net gnd, vcc; subinst(0:1) rc1 of rc { combine(in) = i; combine(out) = o; gnd = gnd; this(0).res.VALUE = ”66”; this(1).res.VALUE = ”100”; } inst P1 of Connector { p[0:2] = i[0] & gnd & o[1]; p[3] = open; } }
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A REAL PHDL BOARD: FPGA-BASED MOTOR CONTROL
Part 4
48
2.1
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BYU Proof of Concept Board
FPGA-based motor controller (2-axes) – Spartan3 400K 144-pin QFP implements:
• 32-bit position, vel. and accel. registers per axis • Programmable PID filters, sampling intervals • Trapezoidal velocity profile generators • Packet router over RS232 to host PC application
– Supporting hardware • 500+ CPR encoder feedback resolution • PWM brushless and brushed motor drives • The usual JTAG, Flash ROM, GPIO, etc.
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Motor Controller Board
50
Final Layout
Design Entry: ~1200 lines of PHDL 30 device decls 672 nets
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Motor Controller Board
51
Back From Manufacturing
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Motor Controller Board Assembled
Top Bottom
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Motor Controller Board
FPGA / SRAM
Power Supply 12VDC IN: To 5V, 3.3V, 2.5V, 1.2V
RS232
JTAG
Motor Power 58VDC MAX
Brushless Drive (x2)
Brushed Drive (x2)
Encoder Feedback
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SOURCE CODE CONTROL SYSTEMS (SCCS)
Part 5
54
2.1
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Motivation
• SCCS provides a remote repository – Collaborate between users – Saves all design versions
• Document every design change • Compare versions
– Tag release file sets
• CVS and SVN are commonly used – Command line versions for Linux – GUI programs for Windows (ex: Tortoise)
55
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The Old Binary File Way
• PowerSupp.sch • PowerSupp_new.sch • PowerSupp_newer.sch • PowerSupp_june15.sch • PowerSupp_v1.3
• What changed between two versions? % diff a.sch b.sch Binary files a.sch and b.sch differ %"
56
Not very helpful… How do we know what really changed?
Each is a different version of the design. No enforced naming or numbering system. User must keep track of them.
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The SCCS Way (CVS)
57
"% cvs diff"cvs diff: Diffing ."Index: a.phdl"============================================="RCS file: /fpga2/cvsroot/users/nelson/test/a.phdl,v"retrieving revision 1.2"diff -r1.2 a.phdl"31c31"< "attr FOOTPRINT = "1V60R-5";"---"> "attr FOOTPRINT = "1V60R";"
"
This shows that line 31 has changed. Comparison between local copy and most recent archived version (v1.2). Can compare any two arbitrarily chosen versions.
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The SCCS Way (Eclipse IDE)
58
This shows that line 31 has changed.
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THE ECLIPSE PLUG-IN FOR PHDL
Part 6
59
2.1
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Eclipse PHDL Plug-In
60
The files in my project
The file being edited Syntax coloring helps understand structure and find simple errors (ex: no closing quote on a string)
An outline of the structure of the project
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Real-Time Syntax Checking (1)
61
Error mark shows up instantly Mouse hover gives popup error message
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Real-Time Syntax Checking (2)
62
When possible, IDE proposes “Quick Fixes”.
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Content Assist (1)
63
Key click brings up context-specific content suggestions
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Content Assist (2)
64
Template has been inserted. Tab between fields to fill it in.
In body of subinstance, will suggest what you can do based on what has been defined thus far in the project and insert template if selected.
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Content Interrogation
65
Hovering over a named element will give its definition CTRL-clicking it will take you to that definition, even if in another file
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Plug-In: Possible Features
• Click on a signal definition – Highlight every place in code it is wired
• Design hierarchy browsing
• Design visualization – Net extents – Localized connectivity
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Integration with SCCS (SVN)
67
Project navigator screen shows which files are out of date with repository.
Clicking takes you to repository synchronization screen
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SVN Synchronize Screen
68
List of files that have been modified Double click a file to bring up side-by- side comparison window
Click icons to check files into repository
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New vs. Old File Comparison
69
This shows that line 31 has changed.
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3RD PARTY TOOLS Part 7
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Example: FPGA Pin Generation (csv2phdl)
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library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity fpga is
port( clk : in std_logic; rst : in std_logic; -- RS232 serial ports rxd : in std_logic; txd : out std_logic; rxd_a : in std_logic; txd_a : out std_logic; -- 12-bit DAC sclk : out std_logic; sync : out std_logic; sdata : out std_logic data : out
std_logic_vector(7 downto 0) . . . );
end entity fpga;
Synthesis, PAR, csv2phdl
#fpga.ucf LOC “clk” = P52; LOC “rst” = P40: LOC “rxd” = P47; LOC “rxd_a” = P41; . . .
Location
Constraints
FPGA VHDL Design
device fpga is attr REFPREFIX = "U"; attr FOOTPRINT = "tq144"; attr LIBRARY = ”XILINX"; attr mfgr = "XILINX"; attr partNumber = "xc3s400-4tq144";
// User I/O pins. pin clk = {P52}; pin rst = {P40}; pin rxd = {P47}; pin rxd_a = {P41}; pin txd = {P46}; pin txd_a = {P44}; pin sclk = {P86}; pin sdata = {P87}; pin sync = {P85}; pin[7:0] data = {P23,P21,P20,P18...}; . . .
end;
PHDL Device Declaration
Thanks to Pete Dudley…
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Example: Automatic Device Generation (DeviceGen)
• Eagle device files are in XML format – 3rd party Java GUI program – Easily browse, select, convert to PHDL
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Name of Eagle library
Browsable list of devices and packages in library
List of selected devices and packages for PHDL device generation
Click to generate PHDL device declarations
Thanks to Richard Black…
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PHDL IS OPEN SOURCE AND AVAILABLE
Part 8
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phdl.sourceforge.net
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phdl.sourceforge.net
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Acknowledgements
• Sandia National Laboratories – Supported the work – Provided technical direction and management – Chuck Graham and Wes Landaker
• Pete Dudley – proposed PHDL
– Formerly of Sandia, now of hdlguy.com, an FPGA & PCB board design consultancy
– Authored the csv2phdl tool
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FUTURE WORK Part 8
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Future Tasks
• Tool & library integration • Hierarchical refdes generation
– Provide natural grouping mechanism • Connectivity ERC • Design visualization tools
– Hierarchy browsing – Cross-probing – Graphical viewing
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