hdl lab manual

HDL LAB MANUAL DEPT OF E &CE

R.Y.M.E.C 1

INDEX

SL.NO EXPERIMENT TITLE PAGE

NO

PART-A

1. Write the HDL code to realize all logic gates.

2

2. Write the HDL code for the following combinational designs.

a.Write the HDL code to realize 2 to 4 Decoder.

4

b.Write the HDL code to realize 8 to 3 Encoder(with and without

priority).

6

c.Write the HDL code to realize 8 to 1 Multiplexer.

10

d.Write the HDL code to realize 4-bit Binary to Gray converter.

12

e. Write the HDL code to realize 1 to 8 Demultiplexer.

14

f. Write the HDL code to realize 1-bit and 4-bit comparator.

16

3. Write the HDL code to describe the function of Full Adder using three

modeling styles.

20

4. ALU.

26

5. Write the HDL codes for the following flip flops:SR, JK, D, T.

28

6. Design 4 bit binary, BCD counters(Synchronous reset and Asynchronous

reset) and “any sequence counters”.

36

PART-B

1. write HDL code to generate different waveforms(Sine, Square,

Triangle, Ramp) using DAC to change frequency and amplitude.

45

2. Write the HDL code to display numerical digits using Hex keypad input

data (Keymatrix).

51

3. write HDL code to control speed, direction of DC and stepper motor.

54

4. Test counter for interfacing programs.

57

CPLD pin assignments.

58

Execution Procedure.

59


R.Y.M.E.C 2

PART-A

Experiment No. 1

Aim: Write VHDL and verilog codes to realize all the logic gates.

VHDL Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity gates is

port ( ain, bin : in std_logic;

op_not, op_and, op_or : out std_logic;

op_nand, op_nor : out std_logic;

op_xor, op_xnor: out std_logic );

end gates;

architecture logic_gates of gates is

begin

op_not<= not ain;

op_and<= ain and bin;

op_or<= ain or bin;

op_nand<= ain nand bin;

op_nor<= ain nor bin;

op_xor<= ain xor bin;

op_xnor<= ain xnor bin;

end logic_gates;


R.Y.M.E.C 3

Verilog Code

module (ain, bin, op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor);

input ain, bin;

output op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor;

assign op_or = ain|bin;

assign op_and = ain & bin;

assign op_not = ~ ain

assign op_xor = (ain ^ bin);

assign op_xnor = ~ (ain ^ bin);

assign op_nand = ~ (ain & bin);

assign op_nor =~ (ain | bin);

endmodule;


R.Y.M.E.C 4

Experiment No. 2

Aim: Write VHDL and verilog codes for the following combinational designs.

2 to 4 decoder.

a.VHDL code for 2 to 4 decoder.

library IEEE;


entity DECODER is

Port ( DIN : in std_logic_vector(1 downto 0);

DOUT : out std_logic_vector(3 downto 0));

end DECODER;

architecture Behavioral of DECODER is

begin

process(DIN)

begin

case DIN is

when "00" => DOUT <= "0001";

when "01" => DOUT <= "0010";

when "10" => DOUT <= "0100";

when "11" => DOUT <= "1000";

when others => null;

end case;

end process;

end Behavioral;


R.Y.M.E.C 5

a.Verilog Code for 2 to 4 decoder.

module decode_24(DIN,DOUT);

input [1:0] DIN;

output [3:0] DOUT;

reg [3:0] DOUT;

always @(DIN)

begin

case (DIN)

2'b00 : DOUT=4'b0001;

2'b01 : DOUT=4'b0010;

2'b10 : DOUT=4'b0100;

default: DOUT=4'b1000;

endcase

end

endmodule


R.Y.M.E.C 6

b.VHDL code for 8 to 3 encoder with priority.

library IEEE;


entity ENWP is

Port ( DIN : in std_logic_VECTOR(7 DOWNTO 0);

DOUT : out std_logic_VECTOR(2 DOWNTO 0));

end ENWP;

architecture ENWP_ARCH of ENWP is

begin

PROCESS(DIN)

BEGIN

CASE DIN IS

WHEN "-------1" => DOUT<="000";

WHEN "------10" => DOUT<="001";

WHEN "-----100" => DOUT<="010";

WHEN "----1000" => DOUT<="011";

WHEN "---10000" => DOUT<="100";

WHEN "--100000" => DOUT<="101";

WHEN "-1000000" => DOUT<="110";

WHEN "10000000" => DOUT<="111";

WHEN OTHERS => DOUT<="ZZZ";

END CASE;

END PROCESS;

end ENWP_ARCH;


R.Y.M.E.C 7

b.Verilog code for 8 to 3 encoder with priority.

module ENCODE (DIN, DOUT);

input [7:0] DIN;

output [2:0] DOUT;

reg [2:0] DOUT;

always @ ( DIN )

begin

casex ( DIN )

8'b00000001 : DOUT = 3'b000;

8'b0000001x : DOUT = 3'b001;

8'b000001xx : DOUT = 3'b010;

8'b00001xxx : DOUT = 3'b011;

8'b0001xxxx : DOUT = 3'b100;

8'b001xxxxx : DOUT = 3'b101;

8'b01xxxxxx : DOUT = 3'b110;

8'b1xxxxxxx : DOUT = 3'b111;

endcase

end

endmodule


R.Y.M.E.C 8

b. VHDL code for 8 to 3 encoder without priority.

library IEEE;


entity encoder_83_wop is Port ( DIN : in std_logic_vector(7 downto 0);

DOUT : out std_logic_vector(2 downto 0));

end encoder_83_wop;

architecture Behavioral of encoder_83wop is

begin

process(DIN)

begin

case DIN is

when "00000001" => DOUT <= "000";

when "00000010" => DOUT <= "001";

when "00000100" => DOUT <= "010";

when "00001000" => DOUT <= "011";

when "00010000" => DOUT <= "100";

when "00100000" => DOUT <= "101";

when "01000000" => DOUT <= "110";

when "10000000" => DOUT <= "111";

when others => NULL;

end case;

end process;

end Behavioral;


R.Y.M.E.C 9

b.Verilog code for 8 to 3 encoder without priority.

module ENCODE(DIN,DOUT);

input [7:0] DIN;

output [2:0] DOUT;

reg [2:0] DOUT;

always @(DIN)

begin

case (DIN)

8'b00000001 : DOUT = 3'b000;

8'b00000010 : DOUT = 3'b001;

8'b00000100 : DOUT = 3'b010;

8'b00001000 : DOUT = 3'b011;

8'b00010000 : DOUT = 3'b100;

8'b00100000 : DOUT = 3'b101;

8'b01000000 : DOUT = 3'b110;

8'b10000000 : DOUT = 3'b111;

endcase

end

endmodule


R.Y.M.E.C 10

c. VHDL code for 8 to 1 Multiplexer.

library IEEE;


entity mux_81 is

Port ( inp : in std_logic_vector(7 downto 0);

sel : in std_logic_vector(2 downto 0);

outp: out std_logic);

end mux_81;

architecture mux_arch of mux_81 is

begin

process (inp,sel)

begin

case sel is

when "000" => outp <= inp(0);

when "001" => outp <= inp(1);

when "010" => outp <= inp(2);

when "011" => outp <= inp(3);

when "100" => outp <= inp(4);

when "101" => outp <= inp(5);

when "110" => outp <= inp(6);

when others => outp <= inp(7);

end case;

end process;

end mux_arch;


R.Y.M.E.C 11

c. Verilog code for 8 to 1 Multiplexer.

module mux_81(inp,sel,outp);

input [7:0] inp;

input [2:0] sel;

output outp;

reg outp;

always @ (sel,inp)

begin

case(sel)

3'b000 : outp = inp[0];

3'b001 : outp = inp[1];

3'b010 : outp = inp[2];

3'b011 : outp = inp[3];

3'b100 : outp = inp[4];

3'b101 : outp = inp[5];

3'b110 : outp = inp[6];

default : outp = inp[7];

endcase

end

endmodule


R.Y.M.E.C 12

d.VHDL code for 4-bit Binary to Gray code converter.

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin_to_gry is

Port ( b3,b2,b1,b0 : in std_logic;

g3,g2,g1,g0 : out std_logic);

end bin_to_gry;

architecture Behavioral of bin_to_gry is

begin

g3<=b3;

g2<=b2 xor b3;

g1<=b1 xor b2;

g0<=b0 xor b1;

end Behavioral;


R.Y.M.E.C 13

d.Verilog code for 4-bit Binary to Gray code converter.

module bin_to_gry(b,g);

input [3:0]b;

output [3:0]g;

assign g[3]=b[3];

assign g[2]=b[3]^b[2];



end module


R.Y.M.E.C 14

e. VHDL code for 1 to 8 Demultiplexer.

library IEEE;




-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dmux_18 is

Port ( din : in std_logic;

sel : in std_logic_vector(2 downto 0);

dout : out std_logic_vector(7 downto 0));

end dmux_18;

architecture Behavioral of dmux_18 is

begin

process (din,sel)

begin

case sel is

when "000" => dout(0)<=din;







when others => dout(7)<=din;

end case;

end process;

end Behavioral;


R.Y.M.E.C 15

e. Verilog code for 1 to 8 Demultiplexer.

module dmux_18(din,sel,dout);

input din;

input [2:0] sel;

output [7:0] dout;

reg [7:0] dout;

always @(sel,din)

begin

case (sel)

3'b000 : dout[0]=din;

3'b001 : dout[1]=din;

3'b010 : dout[2]=din;

3'b011 : dout[3]=din;

3'b100 : dout[4]=din;

3'b101 : dout[5]=din;

3'b110 : dout[6]=din;

default : dout[7]=din;

endcase

end

endmodule


R.Y.M.E.C 16

f. VHDL code for 1 bit comparator.

library IEEE;






--library UNISIM;


entity comparator is

Port ( a,b : in std_logic;

lt, gt,eq:out std_logic);

end comparator;

architecture comp_arch of comparator is

begin

eq <= (a xnor b);

lt <= (not a)and b;

gt <= a and (not b);

end comp_arch;


R.Y.M.E.C 17

f. Verilog code for 1 bit comparator.

module comp(a,b,gt,lt,eq);

input a,b;

output gt,lt,eq;

reg gt,lt,eq;

always @(a,b)

begin

eq = ~(a ^ b);

lt = (~a) & b;

gt = a & (~b);

end

endmodule


R.Y.M.E.C 18

g. VHDL code for 4 bit comparator.

library IEEE;






--library UNISIM;


entity comparator is

Port ( a,b : in std_logic_vector(3 downto 0);

x,y,z : out std_logic);

end comparator;

architecture Behavioral of comparator is

begin

process (a,b)

begin

x<='0';

y<='0';

z<='0';

if(a<b)then

x<='1';

elsif (a=b)then

y<='1';

elsif (a>b)then

z<='1';

end if;

end process;

end Behavioral;


R.Y.M.E.C 19

g. Verilog code for 4 bit comparator.

module comparator(a,b,x,y,z);

input [3:0] a,b;

output x,y,z;

reg x,y,z;

always @ (a,b)

begin

x = 1'b0;

y = 1'b0;

z = 1'b0;

if ( a<b)

x = 1'b1;

else if (a==b)

y = 1'b1;

else if (a>b)

z = 1'b1;

end

endmodule


R.Y.M.E.C 20

Experiment No.3

Aim: To write a VHDL and Verilog code to describe the functions of a Full adder

using three modeling styles.

Data flow model

Behavioral model

Structural model

a.VHDL Code for Full adder using Data Flow model.

library IEEE;


entity FA is

Port ( A,B,CIN : in std_logic;

COUT,SUM : out std_logic);

end FA;

architecture FA_DTFL of FA is

begin

SUM <= (A xor B xor CIN);

COUT <= (A and B) or (B and CIN) or (A and CIN);

end FA_DTFL;


R.Y.M.E.C 21

a.Verilog Code for Full adder using Data Flow model.

module FA_DF (A,B,CIN,COUT,SUM);

input A,B,CIN;

output COUT,SUM;

assign SUM = (A ^ B ^ CIN);

assign COUT = (A & B) | (B & CIN) | (A & CIN);

endmodule


R.Y.M.E.C 22

b.VHDL code for full adder using Behavioral model.

library IEEE;


entity FA is

Port (A,B,CIN : in std_logic;

COUT,SUM : out std_logic);

end FA;

architecture FA_BEHAVE of FA is

begin

process(A,B,CIN)

begin

SUM <= (A xor B xor CIN);

COUT <= (A and B) or (B and CIN) or (A and CIN);

end process;

end FA_BEHAVE;


R.Y.M.E.C 23

b.Verilog code for full adder using Behavioral model.

module FA_BEHAVE (A,B,CIN,COUT,SUM);

input A,B,CIN;

output SUM, COUT;

reg SUM,COUT;

always @(A,B,CIN)

begin

SUM = (A ^ B ^ CIN);

COUT = (A & B) | (B & CIN) | (A & CIN);

end;

endmodule


R.Y.M.E.C 24

c.VHDL code for Full adder using structural model.

library IEEE;




entity FULL_ADD is

Port (A,B,CIN: in std_logic;

SUM,COUT: out std_logic);

end FULL_ADD;

architecture STRUCT_ARCH of FULL_ADD is

component HALF_ADD is

port(A,B: in std_logic;

S,C: out std_logic);

end component;

component OR21 is

port(A,B: in std_logic;

C: out std_logic);

end component;

signal S1,C1,C2 : std_logic;

begin

H1: HALF_ADD port map (A,B,S1,C1);

H2: HALF_ADD port map (S1,CIN,SUM,C2);

O1: OR21 port map (C1,C2,COUT);

end STRUCT_ARCH;

-- COMPONENT HALF_ADD

library IEEE;




entity HALF_ADD is

port (A,B: in std_logic;

S,C: out std_logic);

end HALF_ADD;

architecture HALF_ADD_ARCH of HALF_ADD is

begin

S <= A xor B;

C <= A and B;

end HALF_ADD_ARCH;


R.Y.M.E.C 25

-- COMPONENT OR21

library IEEE;




entity OR21 is

port (A, B : in std_logic;

C : out std_logic);

end OR21;

architecture OR21_ARCH of OR21 is

begin

C <= A or B;

end OR21_ARCH;


R.Y.M.E.C 26

c.Verilog code for Full adder using structural model.

module FA_STR (A,B,CIN,SUM,COUT);

input A, B, CIN;

output SUM, COUT;

wire S1,C1,C2;

HA H1(A,B,S1,C1);

HA H2(S1,CIN,SUM,C2);

OR21 O1(C1,C2,COUT);

endmodule

// COMPONENT HA

module HA(X,Y,S,C);

input X;

input Y;

output S;

output C;

assign S= X ^ Y;

assign C= X & Y;

endmodule

//COMPONENT OR21

module OR21(I1,I2,I3);

input I1;

input I2;

output I3;

assign I3 = I1 | I2;

endmodule


R.Y.M.E.C 27

Experiment No.4

Aim: To write a VHDL code to implement a ALU function.


R.Y.M.E.C 28

VHDL code for ALU

library IEEE;






--library UNISIM;


entity alu is

Port (a : in std_logic_vector(3 downto 0);

b : in std_logic_vector(3 downto 0);

opcode : in std_logic_vector(3 downto 0);

y : out std_logic_vector(3 downto 0));

end alu;

architecture Behavioral of alu is

begin

process(a,b,opcode)

begin

case opcode is

when "0000"=>y<=a;

when "0001"=>y<=a+1;

when "0010"=>y<=a-1;

when "0011"=>y<=b;

when "0100"=>y<=b+1;

when "1000"=>y<=not a;

when "1001"=>y<=not b;

when "1010"=>y<=a and b;

when "1011"=>y<=a or b;

when "1100"=>y<=a nand b;

when "1101"=>y<=a nor b;

when "1110"=>y<=a xor b;

when others=>y<=a xnor b;

end case;

end process;

end Behavioral;


R.Y.M.E.C 29

Experiment No. 5

Aim: Develop the HDL code for the following flip-flops SR, D, T, JK.

VHDL code for SR flip flop.

library IEEE;






--library UNISIM;


entity srff is

Port (sr : in std_logic_vector(1 downto 0);

q : buffer std_logic;

clk: in std_logic);

end srff;

architecture Behavioral of srff is

begin

process (clk)

begin

if (rising_edge (clk))then

case sr is

when "00"=>q<=q;

when "01"=>q<='0';

when "10"=>q<='1';

when others=>q<='Z';

end case;

end if;

end process;


R.Y.M.E.C 30

Verilog code for SR flip flop.

module srff(sr, clk, q);

input clk;

output q;

reg q;

always @(clk)

begin

case(sr)

2’b00: q=q;

2’b01: q=0’

2’b10: q=1;

2’b11: q=”Z”;

endcase

end

endmodule


R.Y.M.E.C 31

VHDL code for D flip flop.

library IEEE;




library UNISIM;

use UNISIM.VComponents.all;

--din is switch i/p

--dout and ndout are o/ps routed to o/p leds

--row is the o/p and pulse is the push botton switch i/p

entity d_ff is

Port (d : in std_logic;

q : out std_logic;

qb : out std_logic;

pulse : in std_logic;

row : out std_logic);

end d_ff;

architecture Behavioral of d_ff is

--local signal declaration

signal rowtemp: std_logic:='0';

signal bpulse : std_logic;

begin

u1: ibuf port map( i => pulse, o => bpulse);

process(bpulse)

begin

row <= rowtemp;

if (bpulse'event and bpulse='1') then

if (rowtemp = '0') then

q <= d;

qb <= not d;

end if;

end if;

end process;

end Behavioral;


R.Y.M.E.C 32

Verilog code for D flip flop.

module dflip_flop(din,pulse,dout,ndout,row);

input din;

input pulse;

output dout;

output ndout;

output row;

reg dout,ndout,row;

reg key_temp = 1'b0;

always @(negedge pulse)

begin

row = key_temp;

dout = din;

ndout = ~ din;

end

endmodule


R.Y.M.E.C 33

VHDL code for JK flip flop.

library IEEE;




library UNISIM;


entity jk_ff is

Port ( jk : in std_logic;

Clk : in std_logic;

q,qb : out std_logic );

end jkff;

architecture jkff_arch of jkff is

begin

process(clk)

variable temp1, temp2:std_logic;

begin

if(rising_edge(clk)

case jk is

when “00”=>temp1:=temp1;

when “01”=>temp1:=’0’;

when “10”=>temp1:=’1’;

when others=> null;

end case;

q<=temp1;

temp2:=not temp1;

qb<=temp2;

endif;

end process;

end jkff_arch;


R.Y.M.E.C 34

Verilog code for JK Flip flop.

module jk_ff(pulse,j,k,q,qbar,row);

input j;

input k;

output q;

output qbar;

input pulse;

output row;

reg q=1'b0, qbar=1'b1;

reg row;

reg key_temp = 1'b0;


begin

row = key_temp;

if(j == 1'b0)

if(k == 1'b0)

begin q = q; qbar = qbar; end

if(j == 1'b0)

if(k == 1'b1)

begin q = 1'b0; qbar = 1'b1; end

if(j == 1'b1)

if(k == 1'b0)

begin q = 1'b1; qbar = 1'b0; end

if(j == 1'b1)

if(k == 1'b1)

begin q = ~q; qbar = ~q; end

end

endmodule


R.Y.M.E.C 35

VHDL code for T flip flop.

library IEEE;




library UNISIM;


entity t_ff is

Port (t : in std_logic;

pulse:in std_logic;

q : out std_logic;

qb : out std_logic;

row : out std_logic);

end t_ff;

architecture Behavioral of t_ff is

signal row_temp : std_logic := '0';

signal bpulse : std_logic;

begin

u1: ibuf port map(i=>pulse, o=>bpulse);

process(bpulse, t)

variable temp : std_logic:='0';

begin

row <= row_temp;

if bpulse'event and bpulse='0' then

if row_temp = '0' then

if t = '1' then

temp := not temp;

end if;

end if;

end if;

q <= temp;

qb <= not temp;

end process;

end Behavioral;


R.Y.M.E.C 36

Verilog code for T flip flop.

module t_ff(t,pulse,dout,ndout,row);

input t;

input pulse;

output dout;

output ndout;

output row;

reg row;

reg row_temp = 1'b0;

reg temp_dout = 1'b0;

assign dout = temp_dout;

assign ndout = ~temp_dout;


begin

row = row_temp;

if(t)

temp_dout = ~temp_dout;

end

endmodule


R.Y.M.E.C 37

Experiment No 6.

Aim: Design 4 bit binary, BCD counters(Synchronous reset and Asynchronous

reset) and “any sequence counters”.

BCD asynchronous reset up-counter

library IEEE;






--library UNISIM;


entity bcd_async_up is

Port ( clk,rn : in std_logic;

q : out integer range 0 to 9);

end bcd_async_up;

architecture Behavioral of bcd_async_up is

signal count:integer range 0 to 9:=0;

begin

process(clk,rn)

begin

if(rn='1')then

count<=0;

elsif(rising_edge(clk))then

count<=count+1;

end if;

end process;

q<=count;

end Behavioral;


R.Y.M.E.C 38

BCD asynchronous reset down-counter

library IEEE;






--library UNISIM;


entity bcd_async_dwn is



end bcd_async_dwn;

architecture Behavioral of bcd_async_dwn is


begin

process(clk,rn)

begin

if(rn='1')then

count<=9;


count<=count-1;

end if;

end process;

q<=count;

end Behavioral;


R.Y.M.E.C 39

BCD synchronous reset up-counter




--library UNISIM;


entity bcd_sync_up is



end bcd_sync_up;

architecture Behavioral of bcd_async_up is


begin

process(clk,rn)

begin

if(rising_edge(clk))then

if(rn='1')then

count<=0;

else

count<=count+1;

end if;

end if;

end process;

q<=count;

end Behavioral;


R.Y.M.E.C 40

Binary asynchronous reset up-counter

library IEEE;






--library UNISIM;


entity binary_async_up is

Port ( clk : in std_logic;

rn : in std_logic;

q : out std_logic_vector (3 downto 0));

end binary_async_up;

architecture Behavioral of binary_async_up is

signal count:std_logic_vector (3 downto 0):="0000";

begin

process(clk,rn)

begin

if(rn='1')then

count<="0000";

elsif(rising_edge(clk)) then

count<=count+1;

end if;

end process;

q<=count;

end Behavioral;


R.Y.M.E.C 41

Binary asynchronous reset down-counter

library IEEE;






--library UNISIM;


entity bin_async_dwn is

port ( clk,rn : in std_logic;

q : out std_logic_vector(3 downto 0));

end bin_async_dwn;

architecture Behavioral of bin_async_dwn is

signal count:std_logic_vector(3 downto 0):="1111";

begin

process(clk,rn)

begin

if(rn='1')then

count<="1111";


count<=count-1;

end if;

end process;

q<=count;

end Behavioral;


R.Y.M.E.C 42

Binary synchronous reset up-counter

library IEEE;






--library UNISIM;


entity binary_sync_up is


rn : in std_logic;

q : out std_logic_vector (3 downto 0));

end binary_sync_up;

architecture Behavioral of binary_sync_up is

signal count:std_logic_vector (3 downto 0):="0000";

begin

process(clk,rn)

begin

if(rising_edge(clk)) then

if(rn='1') then

count<="0000";

else

count<=count+1;

end if;

end if;

end process;

q<=count;

end Behavioral;


R.Y.M.E.C 43

Binary synchronous reset down-counter

library IEEE;






--library UNISIM;


entity bin_sync_dwn is



end bin_sync_dwn;

architecture Behavioral of bin_sync_dwn is

signal count:std_logic_vector(3 downto 0):="1111";

begin

process(clk,rn)

begin


if(rn='1')then

count<="1111";

else

count<=count-1;

end if;

end if;

end process;

q<=count;

end Behavioral;


R.Y.M.E.C 44

VHDL code for Any Sequence counter

library IEEE;






--library UNISIM;


entity any_seq_cnt is



end any_seq_cnt;

architecture Behavioral of any_seq_cnt is

begin

process(clk)

variable b: std_logic_vector(3 downto 0):="0000";

variable g: std_logic_vector(3 downto 0);

begin


g(3):=b(3);

g(2):=b(3) xor b(2);

g(1):=b(2) xor b(1);

g(0):=b(1) xor b(0);

q<=g;

b:=b+"0001";

end if;

end process;

end Behavioral;


R.Y.M.E.C 45

Verilog code for Any Sequence counter

module asc(clk, b, q);

input clk;

wire [3:0] b;

output[3:0] q;

assign b= ”0000”;

always @(posedge(clk))

begin

q[3]= b[3];

q[2]= b[3]^b[2];

q[1]= b[2]^b[1];

q[0]= b[1]^b[0];

b= b+”0001”;

end

endmodule


R.Y.M.E.C 46

PARTB

INTERFACING PROGRAMS

1. Aim:Write VHDL code to generate different waveforms(Sine, Square, Triangle, Ramp) using DAC to change frequency and amplitude.

a. DAC RAMP:

--digital to analog converter(generattion of ramp)

library IEEE;




entity dacramp is


douta : out std_logic_vector(7 downto 0);

doutb : out std_logic_vector(7 downto 0));

end dacramp;

architecture Behavioral of dacramp is

signal bclk:std_logic;

signal temp:std_logic_vector(7 downto 0);

component testcnt

port(clk: in std_logic;

one: out std_logic);

end component;

begin

U1:testcnt port map(clk=>clk, one=>bclk);

process(bclk,temp)

begin

if bclk'event and bclk = '1' then

temp<=temp+1;

end if;

douta <= temp;

doutb <= temp;

end process;

end Behavioral;


R.Y.M.E.C 47

b. DAC SQUARE:

--digital to analog converter(squarewave generation)

library IEEE;




entity dacsquare is




end dacsquare;

architecture Behavioral of dacsquare is


signal bclk: std_logic;

signal temp: std_logic_vector( 7 downto 0):="00000000";

--sub component declaration of test count

component testcnt



end component;

begin

--port mapping of test count

U1:testcnt port map( clk => clk, one => bclk);

process(temp,bclk)

begin


temp <= not temp;

end if;

douta <= temp;

doutb <= temp;

end process;

end Behavioral;


R.Y.M.E.C 48

C. DAC SINEWAVE

--digital to analog converter(generattion of sinewave)

library IEEE;




entity dac is




end dac;

architecture Behavioral of dac is



signal temp: std_logic_vector( 7 downto 0):="00000000";

signal count:std_logic_vector(5 downto 0):= "000000";


component testcnt



end component;

begin

--port mapping of test count

u1:testcnt port map( clk => clk, one => bclk);

douta <= temp;

doutb <= temp;

pp1:process(bclk)

begin


count <= count + '1';

if count = "100100" then

count <= "000000";

end if;

end if;

end process pp1;

--assigning values to count

pp2: process(count)

begin

if count = "000000" then

temp <= "10000000";

elsif count = "000001" then

temp <= "10010110";


temp <= "10101011";


temp <= "11000000";


temp <= "11010010";


temp <= "11100010";


temp <= "11101111";


R.Y.M.E.C 49


temp <= "11111000"; --


temp <= "11111110";


temp <= "11111111";


temp <= "11111110";


temp <= "11111000";


temp <= "11101111";


temp <= "11100010";


temp <= "11010010";


temp <= "11000000";


temp <= "10101011";


temp <= "10010110";


temp <= "10000000";


temp <= "01101010";


temp <= "01010100";


temp <= "01000000";


temp <= "00101110"; --


temp <= "00011110";


temp <= "00010001";


temp <= "00001000";


temp <= "00000010";


temp <= "00000000";


temp <= "00000010";


temp <= "00001000";


temp <= "00010001";


temp <= "00011110";


temp <= "00101110";


temp <= "01000000";


temp <= "01010100";


temp <= "01101010";


temp <= "10000000";

end if;


R.Y.M.E.C 50

end process pp2;

end Behavioral;


R.Y.M.E.C 51

d. DAC TRIANGLE:

--digital to analog converter(triangularwave generation)

library IEEE;




entity triangle is

port(clk:in std_logic;

douta,doutb:out std_logic_vector(7 downto 0));

end triangle;

architecture Behavioral of triangle is

signal temp:std_logic_vector(7 downto 0):="00000000";

signal bclk:std_logic;

signal flag:std_logic:='0';

component div

port(clk:in std_logic;

one:out std_logic);

end component;

begin

U1:div port map(clk=>clk, one=>bclk);

douta<=temp;

doutb<=temp;

process(bclk)

begin

if(rising_edge(bclk))then

if(flag='0')then

temp<=temp+10;

if(temp="11110000")then

flag<='1';

end if;

else

temp<=temp-10;

if(temp="00001010")then

flag<='0';

end if;

end if;

end if;

end process;

end Behavioral;


R.Y.M.E.C 52

2. KEYMATRIX:

--keymatrix

library IEEE;




library UNISIM;


--key0,1,2,3 keymatrix i/p

--en1,2,3,4 are enable signals of 7 seg display

--disp connects to 7 seg display lines

--reset is swich i/p

entity keymatrix is

Port ( key0 : in std_logic;

key1 : in std_logic;



en1 : out std_logic;




disp : out std_logic_vector(7 downto 0);

row : out bit_vector(3 downto 0);

clk : in std_logic;

reset : in std_logic);

end keymatrix;

architecture Behavioral of keymatrix is

--local signals

signal temp : std_logic:='1';

signal bkey0: std_logic;




signal bclk : std_logic;

signal bclk1: std_logic;

signal rowtemp: bit_vector(3 downto 0):="1110";

signal disptemp: std_logic_vector(3 downto 0);

--sub component declaration of ibuf

component ibuf

port( i: in std_logic;

o: out std_logic);

end component;


component testcnt

port ( clk: in std_logic;


end component;

--component instantiation

begin

u1:ibuf port map( i => key0, o => bkey0);




u5:testcnt port map( clk => clk, one => bclk);

u6:testcnt port map( clk => bclk, one => bclk1);

en1 <= '0';

en2 <= '1';

en3 <= '1';

en4 <= '1';


R.Y.M.E.C 53

pp1:process(bkey0,bkey1,bkey2,bkey3,reset,bclk1)

begin

--if reset ==1 display f on display

if reset = '1' then

disptemp <= "0000";

--else display the corrsponding pressed switch position

else

if bclk1'event and bclk1 = '1' then

row <= rowtemp;

if rowtemp = "1101" then

if bkey0 = '0' then

disptemp <= "0000";

elsif bkey1 = '0' then

disptemp <= "0001";


disptemp <= "0010";


disptemp <= "0011";

end if;

end if;


if bkey0 = '0' then

disptemp <= "0100";


disptemp <= "0101";


disptemp <= "0110";


disptemp <= "0111";

end if;

end if;


if bkey0 = '0' then

disptemp <= "1000";


disptemp <= "1001";


disptemp <= "1010";


disptemp <= "1011";

end if;

end if;


if bkey0 = '0' then

disptemp <= "1100";


disptemp <= "1101";


disptemp <= "1110";


disptemp <= "1111";


R.Y.M.E.C 54

end if;

end if;

rowtemp <= rowtemp rol 1;

end if;

end if;

end process pp1;

--to display on 7 seg

pp2:process(disptemp)

begin

if disptemp = "0000" then

disp <= "10001110";

elsif disptemp = "0001" then

disp <= "10000011";


disp <= "11111000";


disp <= "10110000";


disp <= "10000110";


disp <= "10001000";


disp <= "10000010";


disp <= "10100100";


disp <= "10100001";


disp <= "10010000";


disp <= "10010010";


disp <= "11111001";


disp <= "11000110";


disp <= "10000000";


disp <= "10011001";


disp <= "11000000";

end if;

end process pp2;

end Behavioral;


R.Y.M.E.C 55

3. Aim: To write VHDL code to control speed, direction of DC and stepper motor

a. STEPPER MOTOR:

library IEEE;






--library UNISIM;


entity stepper_motor_final is

Port ( clock : in std_logic;

cntrl : in std_logic;

dout : out bit_vector(3 downto 0)

);

end stepper_motor_final;

architecture Behavioral of stepper_motor_final is


signal temp:bit_vector( 3 downto 0):= "0111";





component testcnt is



end component;

--component instantiation

begin

--port mapping of test cnt

u1: testcnt port map( clk=> clock, one => bclk);

u2: testcnt port map( clk=> bclk, one => bclk1);

u3: testcnt port map( clk=> bclk1, one => bclk2);

pp1:process( bclk2)

begin

if bclk2'event and bclk2 = '1' then

if cntrl = '1' then

temp <= temp rol 1 ; --anticlockwise rotation

else

temp <= temp ror 1; --clockwise rotation

end if;

end if;

end process pp1;

dout<=temp;

end Behavioral;


R.Y.M.E.C 56

b. DC MOTOR:

library IEEE;






--library UNISIM;


entity dc_motor is

Port ( psw : in std_logic_vector(2 downto 0);

pdcm : out std_logic;

clk : in std_logic);

end dc_motor;

architecture behavioral of dc_motor is

signal sclkdiv : std_logic_vector(11 downto 0):= "000000000000";

signal p100k :std_logic;

component testcnt is

port(clk :in std_logic;

one :out std_logic);

end component;

begin

u1: testcnt

port map(clk=>clk,one=>p100k); --10M/100=100k

-- count upto 3000

process(p100k)

begin

if( rising_edge(clk)) then

sclkdiv <= sclkdiv+1;

end if;

if(sclkdiv = "101110111000") then

sclkdiv <= "000000000000";

end if;

end process;

process(psw,sclkdiv)

variable vdcm : bit;

begin

if(sclkdiv = "000000000000") then

vdcm := '1';

end if;

-- 1f4,320,44c,578,6a4,7d0,8fc,9c4, to vary the speeed of a dc motor

if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';

elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';







end if;

if(vdcm = '1') then pdcm <= '1';

else pdcm <= '0';

end if;


R.Y.M.E.C 57

end process;

end behavioral;


R.Y.M.E.C 58

4. TESTCOUNT:

library IEEE;






--library UNISIM;


entity testcnt is


one : out std_logic);

end testcnt;

architecture Behavioral of testcnt is

signal cnt : std_logic_vector(7 downto 0):="00000000";

signal check: std_logic:='0';

signal t: std_logic:='0';

begin

tenm:process(clk)

begin

if (clk'event and clk ='1') then

cnt <= cnt + '1';

if cnt = "0011001" then

check <= not check;

cnt <= "00000000";

end if;

end if;

end process tenm;

onek:process(check)

begin

if check'event and check = '1'then

t <= not t;

one <= t;

end if;

end process onek;

end Behavioral;


R.Y.M.E.C 59

CPLD pin assignments

signal (output led) pin no.

opled-1 p26

opled-2 p32

opled-3 p34

opled-4 p36

opled-5 p39

opled-6 p41

opled-7 p44

opled-8 p46

opled-9 p48

opled-10 p51

NOTE : ts -- toggle switch (input switch)

opled – output led (output display)

signal (toggle switch) pin. no

ts-1 p31

ts-2 p33

ts-3 p35

ts-4 p37

ts-5 p40

ts-6 p43

ts-7 p45

ts-8 p 47

ts-9 p50

ts-10 p52

ts-11 p54

ts-12 p56


R.Y.M.E.C 60

ISE Quick Start Tutorial

Getting Started

Starting the ISE Software

For Windows users, start ISE from the Start menu by selecting:

Start _Programs _Xilinx ISE 7_ Project Navigator

The ISE Project Navigator opens. The Project Navigator lets you manage the sources

and processes in your ISE project. All of the tasks in the Quick Start Tutorial

are managed from within Project Navigator.

Stopping and Restarting a Session

At any point during this tutorial you can stop your session and continue at a

later time.

To stop the session:

Save all source files you have opened in other applications.

Exit the software (ISE and other applications).

The current status of the ISE projectis maintained when exiting the software.

To restartyour session, startthe ISE software again. ISE displays the contentsand

state of your projectwith the last saved changes.

Accessing Help

At any time during the tutorial, you can access online help for additional

information about a variety of topics and procedures in the ISE software as well

as related tools.

To open Help you may do either of the following:

Press F1to view Help for the specific tool or function that you have

selected or highlighted.

Launch the ISE Help Contents from the Help menu. It contains information

about creating and maintaining your complete design flow in ISE.

Creating a New Project in ISE

In this section, you will create a new ISE project. A project is a collection of

all files necessary to create and to download a design to a selected FPGA or CPLD

device.

To create a new project for this tutorial:

1. Select File > New Project.The New ProjectWizard appears. 2. First, enter a location (directory path) for the new project. 3. Type tutorial in the Project Name field. When you type tutorial in the

Project Name field, a tutorial subdirectory is created automatically in the

directory path you selected.

4. Select HDL from the Top~Level Module Type list, indicating that the top~level file in your project will be HDL, rather than Schematic or EDIF.

5. Click Next to move to the project properties page. 6. Fill in the properties in the table as shown below. Device Family: XC9500 CPLDs

Device: xc9572

Package: PC84

Speed Grade: -15 Top~Level Module Type: HDL Synthesis Tool: XST (VHDL/Verilog)

Simulator: ModelSim


R.Y.M.E.C 61

Generated Simulation Language: VHDL or Verilog, depending on the

language you want to use when running behavioral simulation.

When the table is complete, your project properties should look like the following:

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be created.

Creating an HDL Source In this section, you will create a top-level HDL file for your design.

Determine the language that you wish to use for the tutorial. Then, continue either

to the “Creating a VHDL Source” section below.


R.Y.M.E.C 62

This simple AND Gate design has two inputs: A and B. This design has one output called C

1. Click New Source in the New Project Wizard to add one new source to your project.

2. Select VHDL Module as the source type in the New Source dialog box.

3. Type in the file name andgate.

4. Verify that the Add to project checkbox is selected.

5. Click Next.

6. Define the ports for your VHDL source.

In the Port Name column, type the port names on three separate rows: A,B and C.

In the Direction column, indicate whether each port is an input, output, or

inout. For A and B, select in from the list. For C, select out from the list.

7. Click Next in the Define VHDL Source dialog box.

8. Click Finish in the New Source Information dialog box to complete the new source

file template.

9. Click Next in the New Project Wizard.

10. Click Next again.

11. Click Finish in the New Project Information dialog box.

ISE creates and displays the new project in the Sources in Project window and

adds the andgate.vhd file to the project.

12. Double-click on the andgate.vhd file in the Sources in Project window to open

the VHDL file in the ISE Text Editor.

The andgate.vhd file contains:

Header information.

Library declaration and use statements.

Entity declaration for the counter and an empty architecture statement.

13. In the header section, fill in the following fields:

Design Name: andgate.vhd

Project Name: andgate

Target Device: xc9572- PC84

Description: This is the top level HDL file for an up/down counter.

Dependencies: None

Note: It is good design practice to fill in the header section in all source files.

14. Below the statement, enter the following line: C<= A and B


R.Y.M.E.C 63

Save the file by selecting File > Save.

Checking the Syntax of the New Counter Module

When the source files are complete, the next step is to check the syntax of the

design. Syntax errors and types can be found using this step.

1. Select the counter design source in the ISE Sources window to display the related processes in the Processes for Source window.

2. Click the “+” next to the Synthesize-XST process to expand the hierarchy. 3. Double-click the Check Syntax process.

When an ISE process completes, you will see a status indicator next to the

process name.

If the process completed successfully, a green check mark appears.

If there were errors and the process failed, a red X appears.

A yellow exclamation point means that the process completed successfuly,

but some warnings occurred.

An orange question mark means the process is out of date and should be run

again.

4. Look in the Console tab of the Transcript window and read the output and status messages produced by any process that you run.

Caution! You must correct any errors found in your source files. If

you continue without valid syntax, you will not be able to simulate

or synthesize your design.

Simulation

1. Double click Launch ModelSim Simulator in the Process View window.

2. Right Click ‘a’ to open a context menu.


R.Y.M.E.C 64

3. Select Force or Clock to add the signal.

4. Define the Clock or Force signal to load appropriate signal.

5. Run the simulation by clicking the Run icon in the Main or Wave window


R.Y.M.E.C 65

6. Waveform can be observed in the wave window.

7. Click the Run -All icon on the Main or Wave window toolbar. The simulation

continues running until you execute a break command.

8. Click the Break icon. The simulation stops running.

9. To restart the simulation, click the Restart icon to reload the design elements

and reset the simulation time to zero. The Restart dialog that appears gives

you options on what to retain during the restart

Click the restart button in the restart dialog box.


R.Y.M.E.C 66

Assigning Pin Location

1. Double-click the Assign Package Pins process found in the User Constraints

process group. ISE runs the Synthesis and Translate steps and automatically

creates a User Constraints File (UCF). You will be prompted with the following

message.


R.Y.M.E.C 67

2. Click Yes to add the UCF file to your project. The counter .ucf file is added to

your project and is visible in the Sources in Project window. The Xilinx

Editor opens automatically.

3. Now the Xilinx Pinout and Area Constraints Editor (PACE) opens.

4. You can see your I/O Pins listed in the Design Object List window. Enter a pin

location for each pin in the Loc column as specified below:

A: p90

B: p91

C: p53

5. Click on the Package View tab at the bottom of the window to see the pins you just added. Put your mouse over grid number to verify the pin assignment.

HDL LAB MANUAL DEPT OF E&CE

R.Y.M.E.C 67

67 R.Y.M.E.C

R.Y.M.E.C

6. Select File _ Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK.

7. Close PACE

Creating Configuration Data

The final phase in the software flow is to generate a program file and configure the device.

Generating a Program File

The Program File is a encoded file that is the equivalent of the design in a form that can

downloaded into the CPLD device

1. Double Click the Generate Programming File process located near the bottom of the Processes for Source window. The Program File is created. It is written into a file called

andgate.jed. This is the actual configuration data.

R.Y.M.E.C 69


Configuring the Device

iMPACT is used to configure your FPGA or CPLD device. This is the last

step in the design process. This section provides simple instructions for

configuring a Spartan-3 xc3s200 device connected to your PC.

Note: Your board must be connected to your PC before proceeding. If the

device on your board does not match the device assigned to the project,

you will get errors. Please refer to the iMPACT Help for more

information.To access the help, select Help > Help Topics.

To configure the device:

1. Click the “+” sign to expand the Generate Programming File processes.

1. Double-click the Configure Device (iMPACT) process. iMPACT opens and the Configure Devices dialog box is displayed.

2. In the Configure Devices dialog box, verify that Boundary-Scan Mode is selected and click Next.

3. Verify that Automatically connect to cable and identify Boundary-Scan chain is selected and click Finish.

R.Y.M.E.C 69


4. If you get a message saying that there was one device found, click OK

to continue.

5. The iMPACT will now show the detected device, right click the device and select New Configuration File.

6. The Assign New Configuration File dialog box appears. Assign a configuration file to each device in the JTAG chain. Select the

andgate.jed file and click Open.

7. Right-click on the counter device image, and select Program... to open the Program Options dialog box.

8. Click OK to program the device. ISE programs the device and displays Programming Succeeded if the operation was successful.

10. Close iMPACT without saving.


R.Y.M.E.C 70

.

HDL LAB IV SEMESTER, 2009-10 Dept of E&CE

R.Y.M.E.C, Bellary 74

hdl lab manual

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