hdl lab final

8/11/2019 Hdl Lab Final

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Experiment No: 1 LOGIC GATES

AIM:

To write a VHDL programs for Logic gates and simulate them by using !L!N "#$i %oft

ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&

use !EEE#%TD'L()!*'-.!TH#-LL&

use !EEE#%TD'L()!*'/N%!)NED#-LL&

entity gates is

0ort a : in %TD'L()!*&

b : in %TD'L()!*&

c2d2e2f2g2h2i : out %TD'L()!*3&

end gates&

architecture 4eha5ioral of gates is

begin

processa2b3

begin

c67a and b&

d67a or b&

e67not a&

f67a nand b&

g67a nor b&

h67a xor b&

i67a xnor b&

end process&end 4eha5ioral&


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BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:


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OUTPUT WAVEFORMS (AFTER SIMULATION):

TRUTH TABLE:

a b c=a.b d=ab !=a" #=(a.b)"

$=(ab)"

%=a &' b =a*b

+ + + , , , + + ,

+ , + , , , + , +

, + + , + , + , +

, , , + + + , + ,

PROCEDURE:

1#%tart the ilinx !%E software by Double clic8ing on the !con or

%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0roect Na5igator

$#*reate a new proect by %electing ;ile < New 0roect###

=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#

,# The next step in creating the new source is to add the beha5ioral description for the program#

@#0lace the cursor ust below the begin statement within the program architecture#


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+# %a5e the file by selecting ;ile 9 %a5e#

A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#

C#Verify the ;unctionality using 4eha5ioral %imulation#

"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of

the program module#

1# %a5e the wa5eform#

RESULT:

The VHDL programs for Logic gates are written and simulated by using L!N"#$i 5ersion and the

(utputs are 5erified#


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Experiment No: $a3 HALF ADDER

AIM:

To write a VHDL program for Half adder and simulate them by using !L!N "#$i %oft

ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&use !EEE#%TD'L()!*'11+,#-LL&



entity half is

0ort a2b : in %TD'L()!*&

s2c : out %TD'L()!*3&

end half&

architecture 4eha5ioral of half is

begin

processa2b3

begin

s67a xor b&

c67a and b&

end process&

end 4eha5ioral&

BLOCK DIAGRAM:


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TRUTH TABLE:

a b - c

+ + + +

+ , , +

, + , +

, , + ,


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PROCEDURE:











the program module#


RESULT:

The VHDL program for Half adder is written and simulated by using L!N"#$i 5ersion and the


Experiment No: $b3 FULL ADDER


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AIM:

To write a VHDL program for ;ull adder and simulate them by using !L!N "#$i %oft

ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&


use !EEE#%TD'L()!*'/N%!)NED#-LL&entity full is

0ort a2b2cin : in %TD'L()!*&

s2cout : out %TD'L()!*3&

end full&

architecture 4eha5ioral of full is

begin

processa2b2cin3

begin

ifcin73 then

s67a xor b&

c67a and b&

else

s67a xnor b&

c67a or b&

end if&

end process&

end 4eha5ioral&

BLOCK DIAGRAM:


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TRUTH TABLE:

a b c - c'/0

+ + + + +

+ + , , +

+ , + , +

+ , , + ,, + + , +

, + , + ,

, , + + ,

, , , , ,

PROCEDURE:


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the program module#


RESULT:

The VHDL program for full adder is written and simulated by using L!N"#$i 5ersion and the


Experiment No: $c3 CARR1 LOOK AHEAD ADDER

AIM:


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To write a VHDL program for *arry loo8 ahead adder and simulate them by using !L!N

"#$i %oft ware#

SOFTWARE:

1#!L!N "#$i$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity adder is

0ort a2b : in %TD'L()!*'VE*T(. = downto 3&

cin : in %TD'L()!*&

s : out %TD'L()!*'VE*T(. = downto 3&

cout : out %TD'L()!*3&

end adder&

architecture 4eha5ioral of adder is

%!)N-L c: %TD'L()!*'VE*T(. , D(BNT( 3&

%!)N-L p: %TD'L()!*'VE*T(. = D(BNT( 3&

%!)N-L g: %TD'L()!*'VE*T(. = D(BNT( 3&

4E)!N

)1: ;(. i !N T( = )ENE.-TE

pi3 67 ai3 (. bi3&

gi3 67 ai3 -ND bi3&

si3 67 pi3 (. ci3&

END )ENE.-TE&

c3 67 cin&


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PROCEDURE:



$#*reate a new proect by %electing ;ile < New 0roect###=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#







the program module#


RESULT:

The VHDL program for *arry loo8 a head adder is written and simulated by using L!N"#$i

5ersion and the (utputs are 5erified#

Experiment No: $d3 RIPPLE ADDER


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AIM:

To write a VHDL program for .ipple adder and simulate them by using !L!N "#$i %oft

ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity adder is

0ort a2b : in %TD'L()!*'VE*T(. = downto 3&

cin : in %TD'L()!*&

s : out %TD'L()!*'VE*T(. = downto 3&

cout : out %TD'L()!*3&

end adder&

architecture 4eha5ioral of adder is

%!)N-L c: %TD'L()!*'VE*T(. , D(BNT( 3&

begin

processa2b2cin2c3

begin

c367cin&

;(. i !N T( = loop

si367ai3 xor bi3 xor ci3&

ciF1367ai3 and bi33 or ci3 and ai3 xor bi333&

end loop&

cout 67 c,3&

end process&

end 4eha5ioral&


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BLOCK DIAGRAM:



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PROCEDURE:











the program module#


RESULT:

The VHDL program for .ipple adder is written and simulated by using L!N"#$i 5ersion and the



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Experiment No: =a3 2 TO 3 DECODER

AIM:

To write a VHDL program for $ to , Decoder and simulate it by using !L!N"#$i %oftware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&use !EEE#%TD'L()!*'-.!TH#-LL&


entity dc1 is

0ort en : in %TD'L()!*&

x : in %TD'L()!*'VE*T(. 1 downto 3&

y : out %TD'L()!*'VE*T(. = downto 33&

end dc1&

architecture 4eha5ioral of dc1 is

begin

processen2x3

begin

if en7GG then y67&

else

case x is

when 7


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BLOCK DIAGRAM:




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TRUTH TABLE:

! 4, 4+ 15 12 1, 1+

+ & & + + + +

, + + + + + ,

, + , + + , +

, , + + , + +

, , , , + + +

PROCEDURE:











the program module#


RESULT:

The VHDL program for $ to , Decoder is written and simulated by using L!N"#$i 5ersion and

the (utputs are 5erified#


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Experiment No:=b3 5 TO 6 DECODER

AIM:

To write a VHDL program for = to C Decoder and simulate it by using !L!N"#$i %oft

ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity dc1 is

0ort en : in %TD'L()!*&

x : in %TD'L()!*'VE*T(. $ downto 3&

y : out %TD'L()!*'VE*T(. A downto 33&end dc1&

architecture 4eha5ioral of dc1 is

begin

processen2x3

begin

if en7GG then y67&

else

case x is

when 7


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when 17


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TRUTH TABLE:

! 42 4, 4+ 17 18 19 13 15 12 1, 1++ & & & + + + + + + + +

, + + + + + + + + + + ,

, + + , + + + + + + , +

, + , + + + + + + , + +

, + , , + + + + , + + +

, , + + + + + , + + + +

, , + , + + , + + + + +

, , , + + , + + + + + +

, , , , , + + + + + + +

PROCEDURE:1#%tart the ilinx !%E software by Double clic8ing on the !con or








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the program module#


RESULT:

The VHDL program for = to C Decoder is written and simulated by using L!N"#$i 5ersion and the

(utput is 5erified#

Experiment No: =c3 7SEGMENT DECODER

AIM:

To write a VHDL program for AI%egment Decoder and simulate it by using !L!N"#$i %oft

ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



ENT!TJ 4*D$LED !%

0(.T D:!N %TD'L()!*'VE*T(.= D(BNT( 3&

(:(/T %TD'L()!*'VE*T(.+ D(BNT( 33&

END 4*D$LED&

-.*H!TE*T/.E .TL (; 4*D$LED !%

4E)!N


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0.(*E%% D3

4E)!N

*-%E D !%

BHEN 7


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TRUTH TABLE:

D5 D2 D, D+ O8 O9 O3 O5 O2 O, O+

+ + + + , , , , , , +

+ + + , , , + + + + +

+ + , + , , + , , + ,

+ + , , , , , , + + ,

+ , + + + , , + + , ,

+ , + , , + , , + , ,

+ , , + & + , , , , ,

, , , , , , , + + + +


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, + + + , , , , , , ,

, + + , , , , & + , ,

, + , + & & & & & & &

, + , , & & & & & & &

, , + + & & & & & & &

, , + , & & & & & & &, , , + & & & & & & &

, , , , & & & & & & &

PROCEDURE:











the program module#


RESULT:

The VHDL program for AI%egment Decoder is written and simulated by using L!N"#$i 5ersion

and the (utput is 5erified#

Experiment No: ,b3 64, MULTIPLE4ER

AIM:

To write a VHDL program for C1 Kultiplexer and simulate it by using !L!N"#$i %oft ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:library !EEE&


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use !EEE#%TD'L()!*'11+,#-LL&



entity mul1 is

0ort sel : in %TD'L()!*'VE*T(. $ downto 3&

x : in %TD'L()!*'VE*T(. A downto 3&

y : out %TD'L()!*3&

end mul1&

architecture 4eha5ioral of mul1 is

begin

processsel2x3

begin

case sel is

when 7


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TRUTH TABLE:

-!;2 -!;, -!;+ 47 48 49 43 45 42 4, 4+ 1+ + + + + + + + + + , 4+


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+ + , + + + + + + , + 4,

+ , + + + + + + , + + 42

+ , , + + + + , + + + 45

, + + + + + , + + + + 43

, + , + + , + + + + + 49

, , + + , + + + + + + 48, , , , + + + + + + + 47

PROCEDURE:











the program module#


RESULT:

The VHDL program for C1 Kultiplexer is written and simulated by using L!N"#$i 5ersion and

the (utput is 5erified#

Experiment No: ,a3 34, MULTIPLE4ER

AIM:

To write a VHDL program for ,1 Kultiplexer and simulate it by using !L!N"#$i %oft ware#


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SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity mul1 is

0ort sel : in %TD'L()!*'VE*T(. 1 downto 3&

x : in %TD'L()!*'VE*T(. , downto 3&

y : out %TD'L()!*3&

end mul1&


begin

processsel2x3

begin

case sel is

when 7


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BLOCK DIAGRAM:



TRUTH TABLE:


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-!;, -!;+ 45 42 4, 4+ 1

+ + + + + , 4+

+ , + + , + 4,

, + + , + + 42

, , , + + + 45

PROCEDURE:











the program module#


RESULT:

The VHDL program for ,1 Kultiplexer is written and simulated by using L!N"#$i 5ersion andthe (utput is 5erified#

Experiment No: ,c3 ,84, MULTIPLE4ER


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AIM:

To write a VHDL program for 1+1 Kultiplexer and simulate it by using !L!N"#$i %oft ware#

SOFTWARE:

1#!L!N "#$i$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity mul1 is

0ort sel : in %TD'L()!*'VE*T(. = downto 3&

x : in %TD'L()!*'VE*T(. 1@ downto 3&

y : out %TD'L()!*3&

end mul1&


begin

processsel2x3

begin

case sel is

when 7


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when 1117


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TRUTH TABLE:

-!;5 -!;2 -!;, -!;+ *reating a VHDL %ource? section below#







the program module#


RESULT:

The VHDL programs for 1, DeImultiplexer is written and simulated by using L!N"#$i 5ersion



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Experiment No: @b3 ,46 DEMULTIPLE4ER

AIM:

To write a VHDL program for 1C DeIKultiplexer and simulate it by using !L!N"#$i %oft ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&


use !EEE#%TD'L()!*'/N%!)NED#-LL&entity dem1 is

0ort sel : in %TD'L()!*'VE*T(. $ downto 3&

x : in %TD'L()!*&

y : out %TD'L()!*'VE*T(. A downto 33&

end dem1&

architecture 4eha5ioral of dem1 is

begin

processx2sel3

begin

y67&

case sel is

when 7


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BLOCK DIAGRAM:




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TRUTH TABLE:

-!;2 -!;, -!;+ 4 17 18 19 13 15 12 1, 1+

+ + + A + + + + + + + A

+ + , A + + + + + + A +

+ , + A + + + + + A + +

+ , , A + + + + A + + +

, + + A + + + A + + + +

, + , A + + A + + + + +

, , + A + A + + + + + +

, , , A A + + + + + + +

PROCEDURE:











the program module#


RESULT:

The VHDL programs for 1C DeImultiplexer is written and simulated by using L!N"#$i 5ersionand the (utput is 5erified#


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Experiment No: @a3 ,4,8 DEMULTIPLE4ER

AIM:

To write a VHDL program for 11+ DeIKultiplexer and simulate it by using !L!N"#$i %oft ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity dem is

0ort sel : in %TD'L()!*'VE*T(. = downto 3&

x : in %TD'L()!*&

y : out %TD'L()!*'VE*T(. 1@ downto 33&

end dem&

architecture 4eha5ioral of dem is

begin

processx2sel3

begin

y67&

case sel is

when 7


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when 117


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TRUTH TABLE:

-!;

5

-!;

2

-!;

,

-!;

+

4 1

,9

1

,3

1

,5

1

,2

1

,,

1

,+

1

1

6

1

7

1

8

1

9

1

3

1

5

1

2

1

,

1+

+ + + + A + + + + + + + + + + + + + + + A

+ + + , A + + + + + + + + + + +

+

+ + A +

+ + , + A + + + + + + + + + + + + + A + +

+ + , , A + + + + + + + + + + + + A + + +

+ , + + A + + + + + + + + + + + A + + + +

+ , + , A + + + + + + + + + + A + + + + +

+ , , + A + + + + + + + + + A + + + + + +

+ , , , A + + + + + + + + A + + + + + + +

, + + + A + + + + + + + A + + + + + + + +

, + + , A + + + + + + A + + + + + + + + +

, + , + A + + + + + A + + + + + + + + + +

, + , , A + + + + A + + + + + + + + + + +

, , + + A + + + A + + + + + + + + + + + +

, , + , A + + A + + + + + + + + + + + + +

, , , + A + A + + + + + + + + + + + + + +

, , , , A A + + + + + + + + + + + + + + +

PROCEDURE:







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the program module#


RESULT:

The VHDL programs for 11+ DeImultiplexer is written and simulated by using L!N"#$i 5ersion



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Experiment No: +a3 DFLIPFLOP

AIM:

To write a VHDL program for DI;L!0 ;L(0 and simulate it by using !L!N"#$i %oftware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&


use !EEE#%TD'L()!*'/N%!)NED#-LL&entity dff1 is

0ort cl8 : in %TD'L()!*&

d : in %TD'L()!*&

1 : out %TD'L()!*&

$ : out %TD'L()!*3&

end dff1&

architecture 4eha5ioral of dff1 is

begin

processd2cl83

begin

ifd7GGand cl87G1G3 then

167GG&

$67G1G&

else ifd7G1G and cl87G1G3 then

167G1G&

$67GG&

end if&

end if&

end process&

end 4eha5ioral&


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BLOCK DIAGRAM:




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TRUTH TABLE:

cl8 d M1 M$

/ /

1 1

1 1 1

M M

PROCEDURE:











the program module#


RESULT:

The VHDL program for DI;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the

(utput is 5erified#


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Experiment No: +b3 >KFLIPFLOP

AIM:

To write a VHDL program for OI;L!0 ;L(0 and simulate it by using !L!N"#$i %oftware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity O;L!0;L(01 is

0ort : in std'logic&

O : in std'logic&

*LO : in std'logic&

M : inout std'logic&

MN : inout std'logic3&

end O;L!0;L(01&

architecture 4eha5ioral of O;L!0;L(01 isbegin

process*LO22O3

begin

if *LO7G1G and *LOGe5ent3 then

if7GG and O7GG3 then

M 67M&

MN 67MN&

elsif7GG and O7G1G3 then

M 67 G1G&

MN 67 GG& elsif7G1G and O7GG3 then

M 67 GG&

MN 67 G1G&

elsif7G1G and O7G1G3 then

M 67 N(T M&

MN 67 N(T MN&

end if&

end if&

end process&

end 4eha5ioral&


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BLOCK DIAGRAM:




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TRUTH TABLE:

O MnF1

Mn

1

1 1

1 1 Mn

PROCEDURE:











the program module#


RESULT:

The VHDL program for OI;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the

(utput is 5erified#


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Experiment No: +c3 TFLIPFLOP

AIM:

To write a VHDL program for TI;L!0 ;L(0 and simulate it by using !L!N"#$i %oftware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#all&

entity tff is

portcl8: in std'logic&

reset: in std'logic&

t: in std'logic&

: out std'logic3&

end tff&

architecture beha5e of tff is

signal 'reg: std'logic&

signal 'next: std'logic&

begin

processcl83

begin

if reset 7 G1G3 then

'reg 67 GG&

elsif cl8Ge5ent and cl8 7 G1G3 then

'reg 67 'next&

end if&

end process&

'next 67 'reg when t 7 GG else

not'reg3&

67 'reg&

end beha5e&


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BLOCK DIAGRAM:




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TRUTH TABLE:

T M M

1

1 1

PROCEDURE:











the program module#


RESULT:

The VHDL program for TI;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the

(utput is 5erified#


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Experiment No: +d3 RSFLIPFLOP

AIM:

To write a VHDL program for .%I;L!0 ;L(0 and simulate it by using !L!N"#$i%oftware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library ieee&

use ieee#std'logic'11+,#all&

entity beoy'rsff is

ports2r2cl8:in std'logic&212P:inout std'logic3&

end beoy'rsff&

architecture arc of beoy'rsff is

begin

processcl83

begin

if cl87G1G then

P67s or not r3 and 3&

67P after @ns&

167not P after @ns&

end if&

end process&

end arc&

BLOCK DIAGRAM:


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TRUTH TABLE:

% . MnF1

Mn

1 1 1


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1 1

PROCEDURE:











the program module#


RESULT:

The VHDL program for .%I;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the

(utput is 5erified#


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Experiment No: A 3BIT COMPARATOR

AIM:

To write a VHDL program for ,I4it *omparator and simulate it by using !L!N"#$i

%oftware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity compare is

0ort -24 : in %TD'L()!*'VE*T(. = downto 3&

EM2NE2)T2)E2LT2LE : out %TD'L()!*3&

end compare&

architecture 4eha5ioral of compare is

begin

process-243

begin

EM67GG&NE67GG&)T67GG&)E67GG&LT67GG&LE67GG&

if - 7 4 then EM67G1G&end if&

if - Q7 4 then NE67G1G&end if&

if - < 4 then )T67G1G&end if&

if -


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BLOCK DIAGRAM:



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TRUTH TABLE:

COMPARING INPUTS OUTPUTSA5?B5 A2?B2 A,?B, A+?B+ A@B AB A=B

A5@B5 4 4 4 , + +

A5B5 4 4 4 + , +

A5=B5 A2@B2 4 4 , + +

A5=B5 A2B2 4 4 + , +

A5=B5 A2=B2 A,@B, 4 , + +

A5=B5 A2=B2 A,B, 4 + , +

A5=B5 A2=B2 A,=B, A+@B+ , + +

A5=B5 A2=B2 A,=B, A+B+ + , +

A5=B5 A2=B2 A,=B, A+=B+ + + ,

PROCEDURE:







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the program module#


RESULT:

The VHDL program for ,I4it comparator is written and simulated by using L!N"#$i 5ersion and

the (utput is 5erified#

Experiment No: Ca3 DECADE COUNTER

AIM:

To write a VHDL program for Decade *ounter and simulate it by using !L!N"#$i

%oft ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity *ounter is

port cl8: in %TD'L()!*&

reset: in %TD'L()!*&

: out %TD'L()!* 'VE*T(.= downto 3 3&

end *ounter&

architecture 4eha5ioural of *ounter is

begin

processcl82reset3

5ariable temp: std'logic'5ector= downto 3&

begin

if reset7G1G thentemp:7&


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else

if cl87G1G then

if temp6" then

temp:7tempF1&

elsetemp:7&

end if&

end if&

67temp&

end if&

end process&

end 4eha5ioural&

BLOCK DIAGRAM:


64/112



TRUTH TABLE:

*(/NT

(/T0/T%

MD M* M4 M-

1 1

$ 1

= 1 1


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, 1

@ 1 1

+ 1 1

A 1 1 1

C 1

" 1 1

PROCEDURE:




=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section

below#

,# The next step in creating the new source is to add the beha5ioral description for the

program#





"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the

functionality of the program module#1# %a5e the wa5eform#

RESULT:

The VHDL program for Decade *ounter is written and simulated by using L!N"#$i

5ersion and the (utput is 5erified#

Experiment No: Cb3 S1NCHRONOUS COUNTER

AIM:

To write a VHDL program for %ynchronous *ounter and simulate it by using !L!N "#$i

%oft ware#

SOFTWARE:

1#!L!N "#$i


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$#!%E %imulator

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&



entity count1 is

0ort *L(*O : in %TD'L()!*&

D!.E*T!(N : in %TD'L()!*&

*(/NT : out %TD'L()!*'VE*T(. = downto 33&

end count1&

architecture 4eha5ioral of count1 issignal count'int : std'logic'5ector= downto 3 :7 &

begin

process *L(*O3

begin

if *L(*O7G1G and *L(*OGe5ent then

if count'int 6 1111 then

count'int 67 count'int F 1&

else

count'int67&end if&

end if&

end process&

*(/NT 67 count'int&

end 4eha5ioral&

BLOCK DIAGRAM:


67/112



TRUTH TABLE:

*(/NT

(/T0/T%

MD M* M4 M-

1 1

$ 1

= 1 1, 1


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@ 1 1

+ 1 1

A 1 1 1

C 1

" 1 1

1 1 1 11 1 1 1

1$ 1 1

1= 1 1 1

1, 1 1 1

1@ 1 1 1 1

PROCEDURE:











the program module#


RESULT:

The VHDL program for %ynchronous *ounter is written and simulated by using L!N"#$i 5ersion


Experiment No: "a3 SHIFT REGISTERS

AIM:

To write a VHDL program for %hift .egister and simulate it by using !L!N "#$i %oft ware#

SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&


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use !EEE#%TD'L()!*'11+,#-LL&



entity shift is

0ort *2%! : in %TD'L()!*&

%( : out %TD'L()!*3&

end shift&

architecture 4eha5ioral of shift is

signal tmp: std'logic'5ectorA downto 3&

begin

process *3

begin

if *Ge5ent and *7G1G3 then

for i in to + loop

tmpiF13 67 tmpi3&

end loop&

tmp3 67 %!&

end if&

end process&

%( 67 tmpA3&

end 4eha5ioral&

BLOCK DIAGRAM:


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PROCEDURE:1#%tart the ilinx !%E software by Double clic8ing on the !con or


71/112










the program module#


RESULT:

The VHDL program for %hift .egister is written and simulated by using L!N"#$i 5ersion and the

(utput is 5erified#

Experiment No: "b3 UNIVERSAL SHIFT REGISTERS

AIM:

To write a VHDL program for /ni5ersal %hift .egister and simulate it by using !L!N "#$i %oft

ware#


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SOFTWARE:

1#!L!N "#$i

$#!%E %imulator

PROGRAM:

library !EEE&use !EEE#%TD'L()!*'11+,#-LL&



entity uni51 is

0ort D : in %TD'L()!*'VE*T(. = downto 3&

*LO2.%T : in %TD'L()!*&

%!.2%!L : in %TD'L()!*&

% : in %TD'L()!*'VE*T(. 1 downto 3&

M : out %TD'L()!*'VE*T(. = downto 33&end uni51&

architecture 4eha5ioral of uni51 is

begin

process*LO2 .%T3 is

5ariable .E) : std'logic'5ector= downto 3&

begin

if .%T 7 GG3 then

.E) :7 others 7< GG3&

elsif rising'edgecl83 then

case % is

when 11 7*reating a VHDL %ource? section below#



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the program module#


RESULT:

The VHDL program for -rithmetic and Logic /nit is written and simulated by using L!N"#$i

5ersion and the (utput is 5erified#

Experiment No: 11 MEAL1 MACHINE


83/112

AIM:

To write a VHDL program for Kealy machine and simulate it by using !L!N "#$i %oft

ware#

PROGRAM:

library !EEE&

use !EEE#%TD'L()!*'11+,#-LL&

entity mealy is

0ort rst2cl82w : in %TD'L()!*&

P : out %TD'L()!*3&

end mealy&

architecture beha5ioral of Kealy is type state'type is a2b2c3&

signal y'present2y'next:state'type&

begin

processw2y'present3

begin

case y'present is

when a7*reating a VHDL %ource? section below#




98/112





the program module#


RESULT:

The VHDL program for .(K is written and simulated by using L!N"#$i 5ersion and the (utput is

5erified#


99/112

Experiment No: 1+ VERILOG PROGRAMS

AIM:

To write a Verilog code for all programs and 5erify them by using !L!N "#$i %oft ware#

,. LOGIC GATES:

module logica2b2 c2d2e2f2g2h2i3&

input a2b&

output c2d2e2f2g2h2i&

assign c7 a R b&

assign d7 a S b&

assign e7 a&

assign f7 a R b3&

assign g7 a S b3&

assign h7 a U b&

assign i7 a U b3&

endmodule

2(a).HALF ADDER:

module halfa2b2 s2cout3&

input a2b&

output s2cout&

xor x1s2a2b3&

and x$cout2a2b3&

endmodule

2(b).FULL ADDER:

module fullx2y2cin2 s2cout3&

input x2y2cin&

output s2cout&

wire P12P$2P=2P,2P@&

xor x1P12x2y3&


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xor x$s2P12cin3&

and x=P$2x2y3&

and x,P=2y2cin3&

and x@P,2cin2x3&

or x+P@2P$2P=3&

or xAcout2P@2P,3&

endmodule

2(c).RIPPLE ADDER:

module ripa2b2 co2 sum2 cout13&

input =:W a2b&

input co&

output =:W sum&

output cout1&

wire c12c$2c=2c,&

full x1aW2bW2co2sumW2c13&

full x$a1W2b1W2c12sum1W2c$3&

full x=a$W2b$W2c$2sum$W2c=3&

full x,a=W2b=W2c=2sum=W2c,3&

assign cout17c,&

endmodule

module fullx2y2cin2 s2cout3&

input x2y2cin&

output s2cout&

wire P12P$2P=2P,2P@&

xor x1P12x2y3&

xor x$s2P12cin3&

and x=P$2x2y3&


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and x,P=2y2cin3&

and x@P,2cin2x3&

or x+P@2P$2P=3&

or xAcout2P@2P,3&

endmodule

5(a).2 TO 3 DECODER:module decoder$i2 en2 y3&

input 1:W i&

input en&

output :=W y&

reg :,W y&

always Xen or i or y3

begin

ifen3

casei3

:y7,Gb1&

1:y7,Gb1&

$:y7,Gb1&

=:y7,Gb1&

default:y7,Gb&

endcase

else

y7,Gb&

end

endmodule


102/112

5(b).5 TO 6 DECODER:

module decoder$i2 en2 y3&

input $:W i&

input en&

output :AW y&

reg :AW y&

always Xen or i or y3

begin

ifen3

casei3

:y7CGb1&

1:y7CGb1&

$:y7CGb1&

=:y7CGb1&

,:y7CGb1&

@:y7CGb1&

+:y7CGb1&

A:y7CGb1&

default:y7CGb&

endcase

else

y7CGb&end

endmodule

5(c).SEVEN SEGMENT DECODER:

module se5en'segmenta2b2c2d2en2 y3&

input a2b2c2d2en&

output +:W y&


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reg +:W y&

always Xa or b or c or d or en or y3

begin

ifen3

caseYd2c2b2aZ3

:y7AGb111111&

1:y7AGb11&

$:y7AGb11111&

=:y7AGb11111&

,:y7AGb1111&

@:y7AGb11111&

+:y7AGb11111&

A:y7AGb111&

C:y7AGb1111111&

":y7AGb11111&

default y7AGbx&

endcase

else

y7AGb&

end

endmodule

3(a).34, MULTIPLE4ER:

module muxa2b2c2d2 s2 J3&

input a2b2c2d&

input 1:W s&

output J&

reg J&

always X a or b or c or d or s or J3


104/112

begin

cases3

$Gb: J7a&

$Gb1: J7b&

$Gb1: J7c&

$Gb11: J7d&

default:J7$Gbx&

endcase

end

endmodule

3(b).64, MULTIPLE4ER:

module muxCa2b2c2d2e2f2g2h2 s2 y3&

input a2b2c2d2e2f2g2h&

input $:W s&

output y&

reg y&

always X a or b or c or d or e or f or g or h or s or y3

begin

cases3

=Gb: y7a&

=Gb1: y7b&

=Gb1: y7c&

=Gb11: y7d&

=Gb1: y7e&

=Gb11: y7f&=Gb11: y7g&

=Gb111: y7h&

default:y7=Gbx&

endcase

end

endmodule


105/112

3(c).,84, MULTIPLE4ER:

module muxCa2b2c2d2e2f2g2h2i2282l2m2n2o2p2 s2 y3&

input a2b2c2d2e2f2g2h2i2282l2m2n2o2p&

input =:W s&

output y&

reg y&

always X a or b or c or d or e or f or g or h or i or or 8 or l or m or n or o or p or s or y3

begin

cases3

,Gb: y7a&

,Gb1: y7b&

,Gb1: y7c&

,Gb11: y7d&

,Gb1: y7e&

,Gb11: y7f&

,Gb11: y7g&

,Gb111: y7h&

,Gb1: y7i&

,Gb11: y7&

,Gb11: y78&

,Gb111: y7l&

,Gb11: y7m&

,Gb111: y7n&

,Gb111: y7o&

,Gb1111: y7p&

default:y7,Gbx&

endcase

end

endmodule


106/112

9(a).,43 DE MULTIPLE4ER:

module demuxx2 sel2 y3&

input x&

input :1Wsel&

output :=W y&

reg:=W y&

always Xx or sel or y3

begin

y7,Gb&

casesel3

:yW7x&

1:y1W7x&

$:y$W7x&

=:y=W7x&

default :y7,Gb&

endcase

end

endmodule

9(b).,46 DE MULTIPLE4ER:


input x&

input :$Wsel&

output :AW y&

reg:AW y&


begin

y7CGb&

casesel3

:yW7x&

1:y1W7x&

$:y$W7x&


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=:y=W7x&

,:y,W7x&

@:y@W7x&

+:y+W7x&

A:yAW7x&

default :y7CGb&

endcase

end

endmodule

9(c).,4,8 DE MULTIPLE4ER:


input x&

input :=Wsel&

output :1@W y&

reg:1@W y&


begin

y71@Gb&

casesel3

:yW7x&

1:y1W7x&

$:y$W7x&

=:y=W7x&

,:y,W7x&

@:y@W7x&

+:y+W7x&

A:yAW7x&

C:yCW7x&

":y"W7x&1:y1W7x&


108/112

11:y11W7x&

1$:y1$W7x&

1=:y1=W7x&

1,:y1,W7x&

1@:y1@W7x&

default :y71@Gb&

endcase

end

endmodule

8.3BIT COMPARATOR:

module compare-242-)42-L42-E43&

input :=W-24&

output -)42-L42-E4&

reg -)42-L42-E4&always X- or 4 or -)4 or -L4 or -E43

begin

-)471Gb&-L471Gb&-E471Gb&

if-7743

begin -)471Gb&-L471Gb&-E471Gb1&end

else if -


109/112

7.PRIORIT1 ENCODER:

module encoderE!'L2!'L2-'L2E('L2)%'L3&

input E!'L&

input A:W!'L&

output $:W-'L&

output E('L2)%'L&

reg A:W!&

reg $:W-2-'L&

reg E!2E('L2E(2)%'L2)%&

integer &

always XE!'L or E! or !'L or ! or - or E( or )%3

begin

E!7E!'L&!7!'L&

E('L7E(&)%'L7)%&-7-&

E(71&)%7&-7&

begin

if E!773 E(7&

else for 7&67A&7F13

if !W7713

begin )%71&E(7&-7&end

end

end

endmodule


110/112

DFLIPFLOP:

module d'flipflopcl82d2 2n3&

input cl82d&

output 2n&

reg 2n&

always Xposedge cl83

begin

67 d&

n 67 [d&

end

endmodule

>K FLIPFLOP:

module 8'flipflopcl82282 2n3&

input cl8228&

output 2n&

reg 2n&


begin

if 77 R 8 77 3

begin

67 &

n 67 n&

endelse if 77 R 8 77 13

begin

67 1Gb&

n 67 1Gb1&

end

else if 77 1 R 8 77 3

begin

67 1Gb1&

n 67 1Gb&


111/112

end

else if 77 1 R 8 77 13

begin

67 [&

n 67 [n&

end

else

begin

671Gbx&

n 671Gbx&

end

end

endmodule

RSFLIPFLOP:

module rsflipflops2r2cl82 2n3&

input s2r2cl8&

output 2n&

reg 2n&


begin

ifs77 R r 77 3

begin 67 &

n 67 n&

end

else ifs771 R r773

begin

671Gb1&

n 671Gb&

end

else ifs77 R r7713


112/112

begin

671Gb&

n 671Gb1&

end

else ifs771 R r7713

begin

671Gbx&

n 671Gbx&

end

else

begin

671Gb&

n 671Gb&

end

end

endmodule

T FLIPFLOP:

module t'flipflopcl82t2reset2 3&

input cl82t2reset&

output &

hdl lab final

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