232 lecture 4 decoders multiplexers

CENG-232

Logic Design

CENG-232

Logic Design

Lecture 4

Decoders, Encoders, Multiplexers

Spring 2015 Spring 2015 -- UluUluçç SaranlSaranlıı

[email protected]@ceng.metu.edu.tr

Spring 2015232 - Logic Design

DecodersDecoders

� Next, we’ll look at some commonly used circuits: decoders and multiplexers.

� These serve as examples of the circuit analysis and design techniques.

� They can be used to implement arbitrary functions.

� We are introduced to abstraction and modularity as hardware design principles.

� We’ll often use decoders and multiplexers as building blocks in designing more complex hardware.


What is a Decoder?What is a Decoder?

� In older days, the (good) printers used to be like typewriters:

� To print “A”, a wheel turned, brought the “A” key up, which then

was struck on the paper.

� Letters are encoded as 8 bit codes inside the computer.

� When the particular combination of bits that encodes “A” is

detected, we want to activate the output line corresponding to A

� How to do this “detection” : Decoder

� General idea: given a k bit input,

� Detect which of the 2k combinations is represented

� Produce 2k outputs, only one of which is “1”.


What does a decoder do?What does a decoder do?� A n-to-2n decoder takes an n-bit input and produces 2n outputs. The

n inputs represent a binary number that determines which of the 2n

outputs is uniquely true.

� A 2-to-4 decoder operates according to the following truth table.

� The 2-bit input is called S1 S0, and the four outputs are Q0-Q3.

� If the input is the binary number i, then output Qi is uniquely true.

� For instance, if the input S1 S0 = 10 (decimal 2), then output Q2 is true, and Q0, Q1, Q3 are all false.

� This circuit “decodes” a binary number into a “one-of-four” code.

S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1


How can you build a 2How can you build a 2--toto--4 decoder?4 decoder?

� Follow the design procedures!

� We have a truth table, so we can write equations for each of the four outputs (Q0-Q3), based on the two inputs (S0-S1).

� In this case there’s not much to be simplified.

S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Q0 = S1’ S0’Q1 = S1’ S0

Q2 = S1 S0’Q3 = S1 S0


A picture of a 2A picture of a 2--toto--4 decoder4 decoder

S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Q0 = S1’ S0’Q1 = S1’ S0

Q2 = S1 S0’Q3 = S1 S0


Enable inputsEnable inputs

� Many devices have an additional enable input, which is used to “activate” or “deactivate” the device.

� For a decoder,

� EN=1 activates the decoder, so it behaves as specified

earlier. Exactly one of the outputs will be 1.

� EN=0 “deactivates” the decoder. By convention, that

means all of the decoder’s outputs are 0.

� We can include this additional input in the decoder’s truth table: EN S1 S0 Q0 Q1 Q2 Q3

0 0 0 0 0 0 0

0 0 1 0 0 0 0

0 1 0 0 0 0 0

0 1 1 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1


An aside: abbreviated truth tablesAn aside: abbreviated truth tables

� In this table, note that whenever EN=0, the outputs are always 0, regardless of

inputs S1 and S0.

� We can abbreviate the table by writing x’s in the input columns for S1 and S0.

EN S1 S0 Q0 Q1 Q2 Q3

0 0 0 0 0 0 0

0 0 1 0 0 0 0

0 1 0 0 0 0 0

0 1 1 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1


0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1


Blocks and AbstractionBlocks and Abstraction

� Decoders are common enough that we want to encapsulate them and treat them as an individual entity.

� Block diagrams for 2-to-4 decoders are shown here. The names of the inputs and outputs, not their order,

is what matters.

Q0 = S1’ S0’Q1 = S1’ S0Q2 = S1 S0’Q3 = S1 S0


DecoderDecoder

� A decoder block provides abstraction:

� You can use the decoder as long as you know its truth table or equations, without knowing exactly what’s inside.

� It makes diagrams simpler by hiding the internal circuitry.

� It simplifies hardware reuse. You don’t have to keep

rebuilding the decoder from scratch every time you need it.

� These blocks are like functions in programming!


A 3A 3--toto--8 decoder8 decoder� Larger decoders are similar. Here is a 3-to-8 decoder.

� The block symbol is on the right.

� A truth table (without EN) is below.

� Output equations are at the bottom right.

� Again, only one output is true for any input combination.

Q0 = S2’ S1’ S0’

Q1 = S2’ S1’ S0

Q2 = S2’ S1 S0’

Q3 = S2’ S1 S0

Q4 = S2 S1’ S0’

Q5 = S2 S1’ S0

Q6 = S2 S1 S0’

Q7 = S2 S1 S0


So what good is a decoder?So what good is a decoder?� Do the truth table and equations look familiar?

� Decoders are sometimes called mintermgenerators.

� For each of the input combinations, exactly

one output is true.

� Each output equation contains all of the input

variables.

� These properties hold for all sizes of decoders.

� This means that you can implement arbitrary functions with decoders.

� If you have a sum of minterms equation for a

function, you can easily use a decoder (a

minterm generator) to implement that function.

S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Q0 = S1’ S0’Q1 = S1’ S0Q2 = S1 S0’Q3 = S1 S0


Design example: Design example: ““AdditionAddition””

� Let’s make a circuit that adds three 1-bit inputs X, Y and Z.

� We will need two bits to represent the total; let’s call them C

and S, for “carry” and “sum” Note that C and S are two separate functions of the same inputs X, Y and Z.

� Here is a truth table and sum-of-minterms equations for C and

S.

X Y Z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1 1 + 1 + 1 = 11

0 + 1 + 1 = 10C(X,Y,Z) = Σ m(3,5,6,7)

S(X,Y,Z) = Σ m(1,2,4,7)


DecoderDecoder--based based ““AdderAdder””

� Here, two 3-to-8 decoders implement C and S as sums of minterms.

C (X,Y,Z) = Σ m(3,5,6,7)

S (X,Y,Z) = Σ m(1,2,4,7)


Using just one decoderUsing just one decoder

� Since the two functions C and S both have the same inputs, we could use just one decoder instead of two.

C (X,Y,Z) = Σ m(3,5,6,7)

S (X,Y,Z) = Σ m(1,2,4,7)


Building a 3Building a 3--toto--8 decoder8 decoder� You could build a 3-to-8 decoder directly from the truth table and

equations below, just like how we built the 2-to-4 decoder.

� Another way to design a decoder is to break it into smaller pieces.

� Notice some patterns in the table below:

� When S2 = 0, outputs Q0-Q3 are generated as in a 2-to-4 decoder.

� When S2 = 1, outputs Q4-Q7 are generated as in a 2-to-4 decoder.

S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Q0 = S2’ S1’ S0’ = m0

Q1 = S2’ S1’ S0 = m1

Q2 = S2’ S1 S0’ = m2

Q3 = S2’ S1 S0 = m3

Q4 = S2 S1’ S0’ = m4

Q5 = S2 S1’ S0 = m5

Q6 = S2 S1 S0’ = m6

Q7 = S2 S1 S0 = m7


Decoder ExpansionDecoder Expansion

� You can use enable inputs to string decoders together. Here’s a 3-to-8 decoder

constructed from two 2-to-4 decoders:

S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1


ModularityModularity

� Be careful not to confuse the “inner” inputs and outputs of the

2-to-4 decoders with the “outer” inputs and outputs of the 3-to-

8 decoder (which are in boldface).

� This is similar to having several functions in a program which

all use a formal parameter “x”

� You could verify that this circuit is a 3-to-8 decoder, by using

equations for the 2-to-4 decoders to derive equations for the 3-

to-8.


A variation of the standard decoderA variation of the standard decoder

� The decoders we’ve seen so far are active-high decoders.

� An active-low decoder is the same thing, but with an inverted

EN input and inverted outputs.

EN’ S1’ S0’ Q0’ Q1’ Q2’ Q3’

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

1 x x 1 1 1 1


0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1


Separated at birth?Separated at birth?

� Active-high decoders generate minterms, as we’ve already seen.

� The output equations for an active-low decoder are mysteriously similar, yet somehow different.

� It turns out that active-low decoders generate maxterms.

Q3 = S1 S0Q2 = S1 S0’Q1 = S1’ S0Q0 = S1’ S0’

Q3’ = (S1 S0)’ = S1’ + S0’Q2’ = (S1 S0’)’ = S1’ + S0Q1’ = (S1’ S0)’ = S1 + S0’Q0’ = (S1’ S0’)’ = S1 + S0


Product of Product of maxtermsmaxterms formform� Every function can be written as a unique product of maxterms:

� Only AND (product) operations occur at the “outermost” level.

� Each term must be maxterm.

� If you have a truth table for a function, you can write a product of maxterms expression by picking out the rows of the table where the function output is 0.

x y z f(x,y,z) f’(x,y,z)

0 0 0 1 0

0 0 1 1 0

0 1 0 1 0

0 1 1 1 0

1 0 0 0 1

1 0 1 0 1

1 1 0 1 0

1 1 1 0 1

f = M4 M5 M7

= ∏M(4,5,7)= (x’ + y + z)(x’ + y + z’)(x’ + y’ + z’)

f’ = M0 M1 M2 M3 M6

= ∏M(0,1,2,3,6)= (x + y + z)(x + y + z’)(x + y’ + z)

(x + y’ + z’)(x’ + y’ + z)

f’ contains all the maxterms not in f.


ActiveActive--low decoder examplelow decoder example

� So we can use active-low decoders to implement arbitrary

functions too, but as a product of maxterms.

� For example, here is an implementation of the function from the previous page

� f (x,y,z) = ΠM (4,5,7), using an active-low decoder.

� The “ground” symbol connected to EN represents logical 0, so

this decoder is always enabled.

� Remember that you need an AND gate for a product of sums.


Converting between standard formsConverting between standard forms

� We can easily convert a sum of minterms to a product of

maxterms.

� The easy way is to replace minterms with maxterms, using maxterm numbers that don’t appear in the sum of minterms:

� The same thing works for converting in the opposite direction,

from a product of maxterms to a sum of minterms.

f = Σm(0,1,2,3,6)

f’ = Σm(4,5,7) -- f’ contains all the minterms not in f

= m4 + m5 + m7

(f’)’ = (m4 + m5 + m7)’ -- complementing both sides

f = m4’ m5’ m7’ -- DeMorgan’s law

= M4 M5 M7 -- from the previous page

= ∏M(4,5,7)

F = ΣΣΣΣm(0,1,2,3,6)

= ∏∏∏∏M(4,5,7)


SummarySummary

� A n-to-2n decoder generates the minterms of an n-variable function.

� As such, decoders can be used to implement arbitrary

functions.

� Later on we’ll see other uses for decoders too.

� Some variations of the basic decoder include:

� Adding an enable input.

� Using active-low inputs and outputs to generate maxterms.

� We also talked about:

� Applying our circuit analysis and design techniques to

understand and work with decoders.

� Using block symbols to encapsulate common circuits.

� Building larger decoders from smaller ones.


Multiplexers / Multiplexers / DemultiplexersDemultiplexers

Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.


In the good old times In the good old times ……

� Multiplexers, or “muxes”, are used to choose between

resources.

� A real-life example: in the old days before networking, several computers could share one printer through the use of a switch.


MultiplexersMultiplexers� A 2n-to-1 multiplexer sends one of 2n input lines to a single output

line.

� A multiplexer has two sets of inputs:

� 2n data input lines

� S select lines, to pick one of the 2n data inputs

� The mux output is a single bit, which is one of the 2n data inputs.

� The simplest example is a 2-to-1 mux:

� The select bit S controls which of the data bits D0-D1 is chosen:

� If S=0, then D0 is the output (Q=D0).

� If S=1, then D1 is the output (Q=D1).

Q = S’ D0 + S D1


More truth table abbreviationsMore truth table abbreviations

� Here is a full truth table for this 2-to-1 mux, based on the equation on the right:

� Another kind of abbreviated truth

table.

� Input variables appear in the output.

� This table implies that when S=0, the

output Q=D0, and when S=1 the output Q=D1.

� This is a pretty close match to the equation.

S D1 D0 Q0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Q = S’ D0 + S D1

S Q0 D01 D1


A 4A 4--toto--1 multiplexer1 multiplexer

� Here is a block diagram and abbreviated truth table for a 4-to-1 mux.

EN’ S1 S0 Q0 0 0 D00 0 1 D10 1 0 D20 1 1 D31 x x 1

Q = S1’ S0’ D0 + S1’ S0 D1 + S1 S0’ D2 + S1 S0 D3


Functions with multiplexersFunctions with multiplexers

� Muxes can be used to implement arbitrary

functions.

� One way to implement a function of n

variables is to use an n-to-1 mux:

� For each minterm mi of the function,

connect 1 to mux data input Di. Each input

corresponds to one row of the truth table.

� Connect the function’s input variables to the mux select (S) inputs. These are used

to indicate a particular input combination.

� For example, let’s look at

f (x,y,z) = ΣΣΣΣm (1,2,6,7).


A more efficient wayA more efficient way� We can actually implement f(x,y,z) = �m(1,2,6,7) with

just a 4-to-1 mux, instead of an 8-to-1.

� Step 1: Find the truth table for the function, and group the rows into pairs. Within each pair of rows, x and y are the same, so f is a function of z only.

� When xy=00, f=z

� When xy=01, f=z’

� When xy=10, f=0

� When xy=11, f=1

� Step 2: Connect the first two input variables of the truth table (here, x and y) to the select bits S1 S0 of the 4-to-1 mux.

� Step 3: Connect the equations above for f(z) to the data inputs D0-D3.


Example: Multiplexer Example: Multiplexer ““adderadder””

� Let’s implement the adder carry function, C (X,Y,Z), with

muxes.

� There are three inputs, so we’ll need a 4-to-1 mux.

� The basic setup is to connect two of the input variables

(usually the first two in the truth table) to the mux select inputs.

X Y Z C0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1 With S1=X and S0=Y, then

Q = X’Y’D0 + X’YD1 + XY’D2 + XYD3

Equation for the multiplexer


MultiplexerMultiplexer--based carrybased carry

� We can set the multiplexer data inputs D0-D3, by fixing X and

Y and finding equations for C in terms of just Z.

X Y Z C0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

CC = X= X’’ YY’’ DD00 + X+ X’’ Y DY D11 + X Y+ X Y’’ DD22 + X Y D+ X Y D33

= X= X’’ YY’’ 00 + X+ X’’ Y ZY Z + X Y+ X Y’’ ZZ + X Y 1+ X Y 1

= X= X’’ Y ZY Z + X Y+ X Y’’ ZZ + XY+ XY

= = ΣΣΣΣm(3,5,6,7)m(3,5,6,7)

When XY=00, C=0

When XY=01, C=Z

When XY=10, C=Z

When XY=11, C=1


MultiplexerMultiplexer--based sumbased sum

� Here’s the same thing, but for the sum function S(X,Y,Z).

X Y Z S0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1

S = X’ Y’ D0 + X’ Y D1 + X Y’ D2 + X Y D3

= X’ Y’ Z + X’ Y Z’ + X Y’ Z’ + X Y Z= Σm(1,2,4,7)

When XY=00, S=Z

When XY=01, S=Z’

When XY=10, S=Z’

When XY=11, S=Z


SummarySummary

� A 2n-to-1 multiplexer routes one of 2n input lines to a single output line.

� Just like decoders,

� Muxes are common enough to be supplied as stand-

alone devices for use in modular designs.

� Muxes can implement arbitrary functions.

� We saw some variations of the standard multiplexer:

� Smaller muxes can be combined to produce larger ones.

� We can add active-low or active-high enable inputs.

� As always, we use truth tables and Boolean algebra to analyze things.


Binary AdditionBinary Addition

The following slides are adapted from David Culler’s slides used at Electrical Engineering and Computer Sciences, University of California,

Berkeley


Binary Addition: Half AdderBinary Addition: Half Adder

Ai

Bi

0 1

0

1

0 1

1 0

Sum = Ai Bi + Ai Bi

= Ai + Bi

Ai

Bi

0 1

0

1

0 0

10

Carry = Ai . Bi


HalfHalf--adder Schematicadder Schematic


Full AdderFull Adder


FullFull--AdderAdder

SS = CI = CI xorxor A A xorxor BB

CCOO = B CI + A CI + A B = CI (A + B) + A B= B CI + A CI + A B = CI (A + B) + A B


Ripple Carry AdderRipple Carry Adder

+

A3 B3

S3

+

A2 B2

S2

+

A1 B1

S1

+

A0 B0

S0C1C2C3


Full Adder from Half AddersFull Adder from Half Adders

A B + CI (A xor B) = A B + B CI + A CI

Half Adder

A

B

Half Adder

A + B

CI

A + B + CIS S

COCOCI (A + B)A B

S

CO


Delay in the Ripple Carry AdderDelay in the Ripple Carry AdderCritical delay: the propagation of carry from low to high order stages

A

A

B

B

CI CO

@0

@0

@0

@0

@N

@1

@1

@N+1

@N+2

latearrivingsignal

two gate delaysto compute CO

4 stageadder

final sum andcarry

A 0

B 0

C 0

S 0 @2

A 1

B 1

C 1 @2

S 1 @3

A 2

B 2

C 2 @4

S 2 @5

A 3

B 3

C 3 @6

S 3 @7

C 4 @8

0

1

2

3


Ripple Carry TimingRipple Carry TimingCritical delay: the propagation of carry from low to high order stages

1111 + 0001worst case

addition

T0: Inputs to the adder are valid

T2: Stage 0 carry out (C1)




2 delays to compute sum

but last carry not readyuntil 6 delays later

T0 T2 T4 T6 T8

S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid


What really happens with carriesWhat really happens with carries

FA

c0

a0b0

s0c1

c2c3c4c5c6c7

s7 s6

A B Cout S

0 0 0 Cin

0 1 Cin ~Cin

1 0 Cin ~Cin

1 1 1 Cin

Carry action

kill

Propagate

propagate

generate

Carry Generate Gi = Ai Bi must generate carry when A = B = 1

Carry Propagate Pi = Ai xor Bi carry in will equal carry out here

Ai

Bi

Gi

Ai

Bi

Pi

All generates and propagates in parallel at first stage. No ripple.


Carry Look Ahead LogicCarry Look Ahead Logic

Carry Generate Gi = Ai Bi must generate carry when A = B = 1

Carry Propagate Pi = Ai xor Bi carry in will equal carry out here

Si = Ai xor Bi xor Ci = Pi xor Ci

Ci+1 = Ai Bi + Ai Ci + Bi Ci

= Ai Bi + Ci (Ai + Bi)

= Ai Bi + Ci (Ai xor Bi)

= Gi + Ci Pi

Sum and Carry can be reexpressed in terms of generate/propagate:

Gi

Ci

Pi

Ci

PiSi

Ci+1


All Carries in ParallelAll Carries in Parallel

Reexpress the carry logic for each of the bits:

C1 = G0 + P0 C0

C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0

C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0

C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

Each of the carry equations can be implemented in a two-level logic network

Variables are the adder inputs and carry in to stage 0!


CLA ImplementationCLA Implementation

Adder with Propagate and Generate Outputs

Increasingly complex logic

Pi @ 1 gate delay

Ci Si @ 2 gate delays

Bi

Ai

Gi @ 1 gate delay

C0C0

C0

C0P0P0

P0

P0

G0G0

G0

G0

C1

P1

P1

P1

P1

P1

P1G1

G1

G1

C2P2

P2

P2

P2

P2

P2

G2

G2

C3

P3

P3

P3

P3

G3

C4


Programmable Logic Devices (Programmable Logic Devices (PLDsPLDs))

� PLD is a re-configurable IC built with large numbers of gates connected through electronic fuses to implement arbitrary circuits.

� Programmable Logic Array (PLA)

� Programmable Array Logic (PAL)

� Programmable ROM (read-only memory)

� FPGA


ReadRead--Only MemoriesOnly Memories

� Two dimensional array of 1s and 0s

� entry (row) is called a "word"

� width of row = word-size

� index is called an "address"

� address is input

� selected word is output

decoder

0 n-1

Address

2 -1n

0

1 1 1 1

word[i] = 0011

word[j] = 1010

bit lines (normally pulled to 1 through resistor – selectively connected to 0

by word line controlled switches)

j

i

Internal Organization

word lines (only one is active – decoder is

just right for this)

Example:

10-line address x 8 data ROM210 words x 8 ROM 1024 words x 8 ROM

1k x 8 ROM


A B C F0 F1 F2 F3

0 0 0 0 0 1 00 0 1 1 1 1 00 1 0 0 1 0 00 1 1 0 0 0 11 0 0 1 0 1 11 0 1 1 0 0 01 1 0 0 0 0 11 1 1 0 1 0 0

Truth Table

F0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'

Block Diagram

ROM

8 words x 4 bits/word

address outputs

A B C F0 F1 F2 F3

ROMs and Combinational LogicROMs and Combinational Logic

� Combinational logic implementation (two-level canonical form) using a ROM


ROM StructureROM Structure

n address lines

• • •

inputs

Decoder 2n word

lines

• • •

outputs

Memory

Array

(2n words

by m bits)

m data lines


• • •

inputs

AND

array

• • •

outputs

OR

arrayproduct

terms

Programmable Logic ArraysProgrammable Logic Arrays

� Pre-fabricated building block of many AND/OR gates

� Actually NOR or NAND

� “Personalized” by making or breaking connections among

gates

� Programmable array block diagram for sum of products form


Example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

personality matrix1 = uncomplemented in term0 = complemented in term– = does not participate

1 = term connected to output0 = no connection to output

input side:

output side:

product inputs outputs

term A B C F0 F1 F2 F3

AB 1 1 – 0 1 1 0

B'C – 0 1 0 0 0 1

AC' 1 – 0 0 1 0 0

B'C' – 0 0 1 0 1 0

A 1 – – 1 0 0 1reuse of terms

Enabling ConceptEnabling Concept

� Shared product terms among outputs


Before ProgrammingBefore Programming

� All possible connections available before "programming"


A B C

F1 F2 F3F0

AB

B'C

AC'

B'C'

A

After ProgrammingAfter Programming

� Unwanted connections are "blown"

� Fuse (normally connected, break unwanted ones)

� Anti-fuse (normally disconnected, make wanted connections)


Notation for implementing

F0 = A B + A' B'

F1 = C D' + C' D

AB+A'B' CD'+C'D

AB

A'B'

CD'

C'D

A B C D

Alternate Representation for High Alternate Representation for High

FanFan--in Structuresin Structures

� Short-hand notation -- don't have to draw all the wires

� Signifies a connection is present and perpendicular signal is an input to gate


A B C F1 F2 F3 F4 F5 F60 0 0 0 0 1 1 0 00 0 1 0 1 0 1 1 10 1 0 0 1 0 1 1 10 1 1 0 1 0 1 0 01 0 0 0 1 0 1 1 11 0 1 0 1 0 1 0 01 1 0 0 1 0 1 0 01 1 1 1 1 0 0 1 1

A'B'C'

A'B'C

A'BC'

A'BC

AB'C'

AB'C

ABC'

ABC

A B C

F1 F2 F3 F4 F5 F6

full decoder as for memory address

bits stored in memory

Programmable Logic Array ExampleProgrammable Logic Array Example� Multiple functions of A, B, C

� F1 = A B C

� F2 = A + B + C

� F3 = A' B' C'

� F4 = A' + B' + C'

� F5 = A xor B xor C

� F6 = A xnor B xnor C


a given column of the OR array has access to only a subset of

the possible product terms

PALsPALs and and PLAsPLAs

� Programmable logic array (PLA)

� what we've seen so far

� unconstrained fully-general AND and OR arrays

� Programmable array logic (PAL)

� constrained topology of the OR array

� innovation by Monolithic Memories

� faster and smaller OR plane


0 1 X 0

0 1 X 0

0 0 X X

0 0 X X

D

A

B

C

Minimized Functions:

W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'

A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –

0 0 X 1

0 1 X 1

0 1 X X

0 1 X X

D

A

B

C

K-map for W K-map for X

0 1 X 0

0 1 X 0

1 1 X X

1 1 X X

D

A

B

C

K-map for Y

PALsPALs and and PLAsPLAs: design example: design example

� BCD to Gray code converter

K-map for Z

0 0 X 1

1 0 X 0

0 1 X X

1 0 X X

D

A

B

C



� Code converter: programmed PLA

not a particularly goodcandidate for PAL/PLAimplementation since no terms are shared among outputs

however, much more compact and regular implementation when compared with discrete AND and OR gates

A B C D

W X Y Z

A

BD

BC

BC'

B

C

A'B'C'D

BCD

AD'

BCD'

minimized functions:

W = A + B D + B CX = B C'

Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'


4 product terms

per each OR gate

A

BD

BC

0

BC'

0

0

0

B

C

0

0

A'B'C'D

BCD

AD'

B'CD'W X Y Z

A B C D


� Code converter:

� programmed PAL


EQ NE LT GT

A'B'C'D'

A'BC'D

ABCD

AB'CD'

AC'

A'C

B'D

BD'

A'B'D

B'CD

ABC

BC'D'

A B C D

PALsPALs and and PLAsPLAs: Another Design : Another Design

ExampleExample

� Magnitude comparator

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

D

A

B

C

0 1 1 1

1 0 1 1

1 1 0 1

1 1 1 0

D

A

B

C

0 0 0 0

1 0 0 0

1 1 0 1

1 1 0 0

D

A

B

C

0 1 1 1

0 0 1 1

0 0 0 0

0 0 1 0

D

A

B

C

K-map for EQ K-map for NE

K-map for GTK-map for LT

LT = A'B'D +A'C+B'CD GT =B C'D'+AC'+ABD'

EQ =A'B'C'D'+ A'BC'D +ABCD+AB'CD’

NE =AC'+ B’D +BD’+A'C

232 lecture 4 decoders multiplexers

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