Peak detectors (or envelope detec-tors) are commonly found in mod-ern communication receivers

mainly as a building block of automaticgain control (AGC) loops. The mainfunction of the peak detectors is todetect the peak value of an input signaland track the peak over time. A positivepeak detector is to follow the maximum

value of an input signal and a negativepeak detector (or valley detector) is totrace the minimum value of the inputsignal. Figure 1 illustrates ideal peakdetector outputs from both peak detec-tors. In this article, we present some ofpeak detector topologies and their appli-cations in multistandard wirelessreceivers.

PEAK DETECTOR TOPOLOGIESThe simplest positive peak detector is adiode-capacitor circuit as shown in Figure 2(a) and its negative counterpartwith the diode reversed is in Figure 2(b)[1]. In the positive peak detector circuitin Figure 2(a), while the input voltageVin is larger than the output peak volt-age Vpeak plus the diode voltage drop,the peak point of an input signalcharges up the hold capacitor C andVpeak follows Vin. While Vin is smallerthan the output peak voltage Vpeak andthe diode is reverse biased, the capacitorholds the value. Thus, this circuit can-not precisely track the input peak volt-age because the output peak voltage isalways less than the actual peak voltageby the diode voltage drop, and the cir-cuit is insensitive to the peak less thanthe diode voltage drop. Therefore, thiscircuit is not suitable for detecting smallsignals. Furthermore, the diode voltagedrop is dependent on temperature andcurrent, which makes the circuit moreinaccurate. Another drawback of thissimple circuit is that the inputimpedance is variable and very low dur-ing forward biased condition. In addi-tion, peak detectors have two majorproblems: droop and slew rate. Thedroop is a slow discharge from the holdcapacitor through the leakage and thepath provided by the following stage,and it makes the output peak voltagedeviate from the true peak value. It isbetter to reduce the droop for accuracy.The slew rate is about the speed ofcharging the hold capacitor. It is betterto increase the slew rate for speed. Toincrease the speed of the peak detectorfor tracing a fast input waveform, the

■ 6 IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 20068755-3996/06/$20.00 ©2006 IEEE

CHIPThe

Peak Detectors for Multistandard Wireless Receivers

Seok-Bae Park, James E. Wilson, and Mohammed Ismail

1. Ideal peak detector outputs.

Positive Peak

v

Negative Peak

Input Signal

t

2. Diode-capacitor peak detectors. (a) Positive peak detector (b) Negative peak detector.

Vin VpeakD C

Vin VpeakD

C

(a) (b)

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7 ■IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 2006

value of the hold capacitor should bereduced. However, the smaller capacitorwill cause the larger droop because itcan discharge quickly. Therefore, thereis a trade-off between low droop rate andhigh slew rate in peak detector design.To improve performance, this basic peakdetector topology can be modified inmany ways [1].

A more practical positive peakdetector topology using op-amp isshown in Figure 3 [1]. By feeding backthe Vpeak to the op-amp negative input,the diode voltage drop problem can befixed because the loop around A1 isclosed through the diode D and theVpeak can closely trace Vin while Vin islarger than Vpeak. On the other hand,while the Vin is less than Vpeak, the out-put of A1 goes to negative saturationwith the loop open and the capacitor isholding the peak value. The outputpeak voltage is connected to a buffer(A2 ) to isolate Vpeak from the nextstage. In this circuit, additionalunwanted charging from the op-ampinput bias currents can contribute tothe droop so that MOSFET inputdevices should be utilized in both A1

and A2. Also, finite op-amp slew rate islimiting the speed. In a monolithicpeak detector, the A1 must be carefullydesigned to avoid a possible stabilityproblem in a closed loop condition.

In integrated peak detector circuits,a diode can be implemented simply as adiode-connected MOS transistor [2],[3]. Or, a source follower [4], [5] can beemployed to perform the diode func-tion. Figure 4 shows a positive peakdetector using a source follower. Abuffer could follow the peak detectorfor isolation. While Vin exceeds Vpeak,M1 is on, which charges the capacitorC. While Vin goes below Vpeak, M1 is offand the capacitor holds the output peakvoltage. A very small current source Ib

is included to discharge the capacitorfor better tracking. A resistor can beused instead of a current source. So,the droop rate is controlled by thecapacitance as well as the currentsource. That is, the droop rate(dVpeak/dt) is given by Ib/C since I = C(dVpeak/dt) across the capacitor. Indesigning an AGC loop, this droop rate

should be carefully determined to meetthe AGC settling requirement. In addi-tion, parasitic capacitors should beconsidered to see if the leakage currentcan affect the droop rate. A low drooprate peak detector could dischargeslowly while the envelope of an inputsignal keeps decreasing faster below theprevious peak voltage, in which casethe Vpeak cannot follow the Vin fastenough. Thus, we need to reset thepeak detector periodically so that it canquickly follow the next input peak

point. A reset mechanism can be imple-mented with a simple NMOS switchacross the hold capacitor C which zerosthe output instantly.

Interestingly, a diode can bereplaced with a current mirror [6], [7].As shown in Figure 5, a positive peakdetector is constructed with a differen-tial amplifier (M1 ∼ M4) and a currentmirror (M5 and M6). If the Vin is largerthan the Vpeak , the excess current isflowing through M5 which is alsocopied to M6 and charging the hold

3. Positive peak detector using op-amp.

VinVpeak

VoutA1

D

+

− A2+

−

C

4. Positive peak detector using source follower.

Vin

Vpeak

A

C lb

M1

+

−

5. Positive peak detector using current mirror.

M3 M4M5 M6

M1 M2

Clb1 lb2

Vin

Vpeak

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capacitor C. The small current sourceIb2 is for discharging. We can controlthe droop rate of the peak detector byadjusting the values of capacitance andthe current source.

In designing a peak detector, the val-ues of the hold capacitor and the currentsource are optimized to accurately detectthe peak of a certain input signal. There-fore, it is difficult to make a peak detec-tor work for a wide range of inputfrequencies. In order to design a peakdetector for multistandard wirelessreceivers, we need to make the peakdetector process a broader range of inputsignals. Figure 6 shows one realization ofa peak detector for multistandardreceivers which is a differential versionof the positive peak detector using cur-rent mirror in Figure 5. Both positive

and negative differential input signalsare fed to two identical positive peakdetectors, and a hold capacitor and acurrent source are shared. The single-ended output peak voltage is thus themaximum of the two peak voltages.Here, to make it work for more than onewireless standard, the capacitor C can bemade variable by using switches. Figure7 shows the simulation results of the dif-ferential peak detector with two capaci-tors connected with switches andswitching current source Ib2. Figure 7(a)is the result with 2 MHz input signal andFigure 7(b) is with 20 MHz input signal.Those input signals are amplitude-mod-ulated with modulation frequency 20KHz and modulation index 1. By switch-ing the hold capacitor and the currentsource simultaneously, the peak detector

can efficiently detect the two input sig-nals with different frequencies.

APPLICATIONA peak detector is a key building blockin a received signal strength indicator(RSSI). The RSSI is required for anautomatic gain control (AGC) loop inwireless communication receivers. TheRSSI detects the peak of an input signalnormally at the input of a variable gainamplifier (VGA) and compares it with acertain threshold voltage to produce adigital level output. Using the RSSI output,the AGC controls the gain setting of lownoise amplifiers a n d V G A s . Figure 8shows a simple one bit RSSI architec-ture consisting of a peak detector and acomparator. The final RSSI output iseither 0 V or VDD. The peak detector was

■ 8 IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 2006

7. Simulation results of differential peak detector in Figure 6. (a) With 2 MHz input signal. (b) With 20 MHz input signal.

1.90: VT("/vpeak")

Vpeak

Vpeak

1.80

1.70

1.60

(v)

1.50

1.40

1.30

1.20

1.80

1.70

1.60

(v) 1.50

1.40

1.30

1.200.0 2.0u 4.0u 6.0u 8.0u

Time (s)

(a)

10u 12u 14u 16u 0.0 200n 400n 600n 800n

Time (s)

(b)

1.0u 1.2u 1.4u 1.6u

-: VT("/vinn")-: VT("/vinp"): VT("/vinn")

: VT("/vinp"): VT("/vpeak")

6. Differential positive peak detector.

Vin+

Vpeak

C

M3 M4 M5 M6 M11 M12 M9

M7 M8

M10

M1M2

lb1 lb2 lb1

Vin−

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9 ■IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 2006

implemented with a differential peakdetector shown in Figure 6. In the peakdetector, a reset switch (which was notdrawn in the figure) was also includedacross the hold capacitor C to quicklyrespond to the variation of the peak. Acomparator with hysteresis wasdesigned to improve immunity to thenoise at the peak detector output. Thesupply voltage was 3.3 V. The simulationresult of the RSSI is shown in Figure 9.The reset switch was on for 384.6 nsfrom 30 µsec to cut the slow decay.

REFERENCES[1] A.J. Peyton and V. Walsh, Analog Electronics

with Op Amps: A Source Book of PracticalCircuits. Cambridge, U.K.: Cambridge Univ.Press, 1993.

[2] R.G. Meyer and W.D. Mack, “Monolithic AGCloop for a 160 Mb/s transimpedance amplifi-er,” IEEE J. Solid-State Circuits, vol. 31, no. 9,pp. 1331–1335, Sept. 1996.

[3] H.-C. Chow and I.-H. Wang, “High perfor-mance automatic gain control circuit using aS/H peak detector for ASK receiver,” in Proc.Int. Conf. Electronics, Circuits, Systems,Sept. 2002, vol. 2, pp. 429–432.

[4] E.A. Crain and M.H. Perrott, “A 3.125 Gb/s

limit amplifier in CMOS with 42 dB gain and1 µs offset compensation,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 443–451,Feb. 2006.

[5] R.J. Baker, H.W. Li, and D.E. Boyce, CMOS:Circuit Design, Layout, and Simulation. NewYork: Wiley, 1998.

[6] S.A. Sanielevici, K.R. Cioffi, B. Ahrari, P.S.Stephenson, D.L. Skoglund, and M. Zargari, “A900 MHz transceiver chipset for two-way pag-ing applications,” IEEE J. Solid-State Circuits,vol. 33, no. 12, pp. 2160–2168, Dec. 1998.

[7] H.-Y. Cheung, K.S. Cheung, and J. Lau, “Alow power monolithic AGC with automaticDC offset cancellation for direct conversionhybrid CDMA transceiver used in telemeter-ing,” in Proc. IEEE Int. Symp. Circuits Sys-tems, May 2001, vol. 4, pp. 390–393.

Seok-Bae Park is with Firstpass Tech-nologies, Inc., Dublin, Ohio. James E. Wilson and Mohammed Ismail arewith Analog VLSI Lab., Ohio State Uni-versity, Columbus, Ohio and FirstpassTechnologies, Inc., Dublin, Ohio. E-mail: sbmpark@ieee.org.

9. Simulation result of RSSI in Figure 8.

4.0

3.0

: VT("/rssi_reset")

: VT("/I86/vpeak_I")

× : VT("/rssi_out")

: VT("/inp") Vpeak

Vrssi_out

Vref

Vreset2.0

2.0

1.0

1.0

0.0

4.0

3.0

2.0

1.0

−1.0

0.0

0.0 10u 20u

Time (s)

30u 40u

0.0

(v)

(v)

(v)

: VT("/vref")

: VT("/inn")

8. Simple RSSI architecture.

Vpeak

Vref

0 or 1Peak Detector ComparatorVin

−

Vin+

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