241-208 ch51 chapter 5 combinational logic by taweesak reungpeerakul
TRANSCRIPT
241-208 CH5 1
Chapter 5
Combinational Logic
By Taweesak Reungpeerakul
241-208 CH5 2
Contents Basic Combinational Logic Circuits Implement SOP and POS using Basic
Logic Gates Universal Property of NAND and NOR Combinational Logic using NAND and
NOR Operation with Pulse Waveforms Digital System Application
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5.1 Basic Combinational Logic Circuit
A
Out
B
C
InputsA B C AB AC BC
OUT0 0 0 0 0 0 00 0 1 0 0 0 00 1 0 0 0 0 00 1 1 0 0 1 11 0 0 0 0 0 01 0 1 0 1 0 11 1 0 1 0 0 11 1 1 1 1 1 1
BC
AB
AC
AB+AC+BC
Actually AND-OR is a form of SOP expression !
Aims: Able to analyze&apply AND-OR,AND-OR-INV, XOR, XNOR circuits
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AND-OR-INV Logic
Invert AND-OR in SOP AND-OR-INV in POSProve ??
AB+AC+BC =(A+B)(A+C)(B+C)
A
Out
B
C
A
Out
B
C
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XOR
OUT = AB + AB
A
Out
B
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XNOR
OUT = AB + AB = AB + AB
A
Out
B
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5.2 Implementing Combinational Logic
Ex#1: OUT = ABC+DE Ex#2: OUT = A(BC+DE)
A
Out
B
E
C
D
A
Out
B
E
C
D
Aims: Able to implement a logic circuit from a Boolean expression and truth table and also able to minimize logic circuit.
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From Truth Table
Truth TableA B C OUT0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 01 0 1 11 1 0 01 1 1 0
A
Out
BC
If you should SOP form then just considering outputs “1s”
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Example
Truth TableA B C OUT0 0 0 10 0 1 10 1 0 00 1 1 01 0 0 01 0 1 11 1 0 01 1 1 1
A
Out
BC
TableLogic Circuit Karnaugh Map Simplified Circuit
BCA 0100 1011
1
0 1
11
1
Minimize, don’t forget to use K-Map !!
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5.3 Universal Property of NAND&NOR
INV, OR, AND, and NOR created by using NAND gates A
BAB
A
A+B
B
A
A+B
B
INV
NOR
AND
OR
Aims: implement OMV, OR, AND, and NOR using NAND or vice versa
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Universal Property of NOR
INV, OR, AND, and NAND created by using NOR gates
INV
NAND
AND
OR
AB
A
B
A
B
A+B
A
AB
B
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5.4 Combinational Logic using NAND & NOR
NAND; OUT = AB+CD = AB+CD = (AB)(CD)
A
OUT
B
CD
A
OUT
B
CD
A
OUT
B
CD
Aims: implement logic function using NAND/NOR gates
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Dual Symbols of NAND, i.e. NAND+Negative-OR
Always use the gate symbols in such a way that every connection between a gate output and a gate input is either bubble-to-bubble or nonbubble-to-nonbubble.
A
OUT
B
C
A
OUTB
CABC AB+C
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Example: implemented by NAND
Ex1: ABC+DE
A
OUT
B
D
E
C
Ex2: ABC+D+E
A
OUT
BC
DE
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Combinational Logic using NOR
NOR; (A+B)(C+D)
= (A+B)(C+D) = (A+B)+(C+D)
A
OUT
B
CD
A
OUT
B
CD
A
OUT
B
CD
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Dual Symbols
(A+B)+C
(A+B)C
A
OUT
B
C
A
OUT
B
C
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5.5 Operation with Pulse Waveforms
A
B
OUT
D
C
A
OutB
A
B
OUT
D
C
C
D
Logic circuit Timing diagram
Aims: analyze combination logic circuits with pulse waveform inputs. develop a timing diagram for any given combination logic circuit with specified inputs
Determine the output waveform ?
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Develop logic circuit from waveforms
A
B
OUT
C
AOut
B
C
Not in the form of NAND gates only yet !Transform….. (use dual symbols)
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5.6 Digital System Application
Motor drive
interface
Logic Control
s1
s4
s3
s2
M1
M4
M3
M2
From switches
MOTORS
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Truth TableS1 S2 S3 S4 M1 M2 M3
M40 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 0 0 00 1 0 0 0 0 0 00 1 0 1 0 0 0 00 1 1 0 0 0 0 00 1 1 1 0 0 0 01 0 0 0 1 0 0 01 0 0 1 1 0 0 11 0 1 0 1 0 1 01 0 1 1 0 0 0 01 1 0 0 1 1 0 01 1 0 1 0 0 0 01 1 1 0 1 1 1 01 1 1 1 0 0 0 0
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S1S2
00
10
11
01
00 01 11 10S3S4
Develop logic circuit from Truth Table
S1
OUT
S3
S2
S4
1
11
1
1
For Motor M1
S1S4
S1S2S3