25706cp 25 ghz latched comparator data...

1/31/05 25706CP_DS_1.1 Inphi Proprietary of 15

25706CP 25 GHz Latched Comparator Data Sheet

Applications

• Broadband test and measurement equipment • High speed line receivers and signal regeneration • Oscilloscope and logic analyzer front ends • Threshold and/or peak detectors • Window comparators • High speed triggers

Features

• Supports clock rates up to 25 GHz • Hysteresis <5 mV • 100 ps propagation delay input to output (Clk-Q) • Output amplitude 1.2 Vpp differential • Low power consumption: 550 mW typ. • Supports single-ended and differential operation • Fast rise and fall times: 15 ps typ. • Single –3.3 V power supply • Deterministic Jitter: 2.0 ps p-p typ. • Available in LGA package or die • Random Jitter 0.2 ps RMS typ. • Evaluation board available

Description The 25706CP is an exceptionally fast latched voltage comparator with very low thermal hysteresis that operates with clock rates from DC to 25 GHz. The part is nominally positive-edge triggered; however, by reversing the positive and negative clock connections, a negative-edge triggered application can be accommodated. All differential analog inputs and differential clock inputs are DC coupled on-chip and terminated with resistors to ground. The differential data outputs should be terminated off chip with 50 Ω resistors to ground.

The 25706CP operates from a single -3.3 V power supply and is available in a ceramic land grid array (LGA) package or in die form. The packaged part is also available on an evaluation board with SMA connectors. For customers requiring a comparator that operates from a +3.3 V power supply Inphi offers the 25707CP.

Block Diagram

IN+

IN-

CLKINp

OUTp

OUTn

CLKINn

25706CPLatchClk In

In Out

VEE

GND

IN+

IN-

CLKINp

OUTp

OUTn

CLKINn

25706CPLatchClk In

In Out

VEE

GND


Absolute Maximum Ratings

• Stresses beyond those listed here may cause permanent damage to the device. • These are stress ratings only. Functional operation of the device at these or any other conditions beyond

those indicated in the “Operating Conditions” and “Electrical Specifications” of this datasheet is not implied. • Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameter Symbol Conditions Min Typ Max Unit

Power Supply Voltage VEE –3.6 --- +0.5 V

Analog and Clock Input Signals IN+, IN-, CLKIN –2 --- +0.6 V

Output Signals DOUT –3.5 --- +1 V

Operating Temperature (Junction) – Die TJ --- --- +175 °C

Operating Temperature (Case) – Packaged TC --- --- +125 °C

Shipping/Storage Temperature TSTORE --- --- +125 °C

Humidity RH 0 --- 100 %

VEE, GND >1000 --- --- V

Outputs >200 --- --- V ESD protection (HBM)1 VESD

Clock & analog inputs >100 --- --- V Notes:

1 As per JESD22-A114-B. ESD testing has not been completed.

Operating Conditions

• Important Note: Unused I/O should be terminated with 50 Ω to GND for all specifications to be met.


Power Supply Voltage VEE ± 5% Tolerance –3.465 –3.300 –3.135 V

Power Supply Current IEE --- 167 255 mA

On-Chip Power Dissipation PD --- 550 800 mW

Operating Temperature (Junction) – Die TJ +15 --- +125 °C

Operating Temperature (Case) – Packaged TC –5 --- +85 °C


DC Electrical Specifications

WARNING – To prevent damage to the part: • DC power must be turned off prior to connecting or disconnecting any cables.

• Electrical specifications guaranteed when the part is operated within the specified operating conditions


Analog Input Specification

Input High Level VIH GND referenced -0.5 --- 0.5 V

Input Low Level VIL GND referenced -0.8 --- 0.0 V

Differential peak-to-peak --- --- 1200 Input Amplitude1 VINpp

Single ended peak-to-peak --- --- 1000 mVpp

Input Offset Voltage2 VOS --- ±1.5 ±6 mV

VOS Temperature Coefficient ∆VOS/∆T --- 3 --- µV/°C

DC input resistance RIN Input to GND 55 62.5 70 Ω

Hysteresis (DC) Measured with DC input and 100 MHz clock 5 6 mV

Clock Specification

Input High Level VIH GND referenced –0.5 --- 0.5 V

Input Low Level VIL GND referenced –0.8 --- 0 V

Differential peak-to-peak 300 --- 1200 Input Amplitude1 VCLKpp

Single ended peak-to-peak 300 --- 1000 mVpp

DC input resistance RCLKIN Input to GND 45 50 55 Ω

Output Specification3

Data Output Amplitude DOUT Differential peak-to-peak 1000 1200 1400 mVpp

Output High Voltage VOH DC coupled, GND referenced -85 -55 0 mV

Output Common Mode VOCM DC coupled, GND referenced -425 -360 -300 mV

Output Eye Cross VOEC Single-ended measurement 40 50 60 %

!

Notes: 1 Analog and clock input amplitudes <300 mVpp may cause part to fail the following AC electrical specifications: Clock Phase Margin, Deterministic Jitter, Random Jitter, Clock to Data Output Delay. 2 Typical refers to variance or “1-sigma” value. Expectation value is 0 mV. 3 Outputs are CML and must be externally DC terminated with 50 Ω to GND.

AC Electrical Specifications

WARNING – To prevent damage to the part: • DC power must be turned off prior to connecting or disconnecting any cables.


Electrical specifications guaranteed when the part is operated within the specified operating conditions


Input Specification

0 to 13 GHz 14 15 --- Input Return Loss RLIN

13 to 25 GHz 11 12 --- dB

Soak time = 0.1 µs --- 2 ---

Soak time = 1 µs --- 12 --- Thermal Hysteresis1 VTHYS

Soak time = 100 µs --- 16 ---

mV

Clock Specification

Maximum Clock Frequency fMAX 25 --- --- GHz

Minimum Clock Slew Rate SMIN At CLKIN zero crossing --- --- 1 V/ns

Clock Input Return Loss RLIN 0 to 25 GHz 11 12 --- dB

Clock Phase Margin CPM 25 GHz 305 --- --- deg

Output Specification

Output Rise/Fall Time tr/tf 20–80% --- 15 18 ps

Output Return Loss6 RLOUT --- --- --- dB

Deterministic Jitter4 JD Peak-to-peak --- 2.0 3.5 ps

Random Jitter5 JR RMS --- 0.2 0.3 ps

Die 30 40 50 Clock to Data Output Delay2 tQ

Packaged 80 100 120 ps

Clock to Data Output Delay Variation2, 3 ∆tQ Between 20 and 10 mV overdrive --- TBD --- ps

!

Notes: 1 See Hysteresis Specification section. 2 Valid when clock to data phase is near center of CPM window. tQ and ∆tQ specifications are not fully characterized. 3 Increase of tQ for transition from –0.5-V input voltage to small positive input voltages, V1 and V2, relative to input threshold voltage, where V1 = 20 mV, V2 = 10 mV. See note 1 for determining the threshold voltage. 3 Increase of tQ for transition from –0.5-V input voltage to small positive input voltages, V1 and V2, relative to input threshold voltage, where V1 = 20 mV, V2 = 10 mV. See note 1 for determining the threshold voltage. 4 Deterministic jitter measured with a 12.5 Gbps, 27-1 PRBS pattern. 4 Deterministic jitter measured with a 12.5 Gbps, 27-1 PRBS pattern. 5 Random jitter measured with a 12.5 Gbps, 1010… pattern. 5 Random jitter measured with a 12.5 Gbps, 1010… pattern. 6 See Figure 1 for minimum output return loss specification.6 See Figure 1 for minimum output return loss specification.

Output Return Loss Specification

Minimum Output Return Loss Specification

0

4

8

12

16

0 5 10 15 20 25

Frequency (GHz)

Out

put R

etur

n Lo

ss (d

B)

Figure 1. Minimum output return loss specification.

Timing Diagram

IN -

IN+

DOUTn

DOUTp

50%50%CLKIN =CLKINp - CLKINn

tQ

trtf

20%

80%

20%

80%

1/fCLK

1 2 3 4

1 2

5

3


Input and Output Equivalent Circuits

DOUTp

65 Ω 65 Ω

GND

DOUTn

GND

62.5 Ω

IN+

IN-

62.5 Ω

GND

50 Ω

CLKINp

CLKINn

50 Ω



Typical Operating Characteristics

Typical Output Waveforms

Figure 2. Output DOUTp data eye from on-wafer measurement (DC coupled). Source is 10 Gbps 27–1 PRBS pattern (scope view is 100 mV/div, 20 ps/div)

Figure 3. Output DOUTp data eye from on-wafer measurement (AC coupled). Source is 10 Gbps 27–1 PRBS pattern (scope view is 100 mV/div, 20 ps/div)

DC Characteristics

Output Amplitude (OutP, single-ended) vs. Supply with Temperature as parameter

0.55

0.57

0.59

0.61

0.63

0.65

0.67

0.69

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)

Out

P A

mpl

itude

(V)

T = -5 CT = 25 CT = 85 C

Figure 4. Output DOUTp amplitude swing (volts pk-pk) vs. VEE and temperature. Source is 25 Gbps 27–1 PRBS pattern.

VOUTp VOH vs. Supply with Temperature as parameter

-64

-62

-60

-58

-56

-54

-52

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)

VOU

Tp V

OH

(mV)

T = -5 CT = 25 CT = 85 C

Figure 5. Output DOUTp HIGH voltage (volts DC) vs. VEE and temperature. Source is 25 Gbps 27–1 PRBS pattern.



VOUTp Common Mode Voltage vs. Supply with Temperature as parameter

-376

-374

-372

-370

-368

-366

-364

-362

-360

-358

-356

3.0 3.1 3.2 3.3 3.4 3.5 3.6Power supply (V)

VOUT

p C

omm

on M

ode

Vol

tage

(mV)

T = -5 CT = 25 CT = 85 C

Figure 6. Output DOUTp common mode voltage (volts DC) vs. VEE and temperature. Source is 25 Gbps 27–1 PRBS pattern.

Eye Crossing (OutP) vs. Supply with Temperature as parameter

40.0

45.0

50.0

55.0

60.0

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)

Eye

Cro

ssin

g (O

utP)

(%)

T = -5 CT = 25 CT = 85 C

Figure 7. Output DOUTp data eye crossing vs. VEE and temperature. Source is 25 Gbps 27–1 PRBS pattern.

Power Dissipation vs. Supply with Temperature as parameter

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)

Pow

er D

issi

patio

n (W

) T = -5 CT = 25 CT = 85 C

Figure 8. Power dissipation of the 25706CP (W) vs. VEE and temperature.



AC Characteristics

Peak-to-Peak Jitter (OutP, 2^7-1 patt.) vs. Supply with Temperature as parameter

1.0

1.5

2.0

2.5

3.0

3.5

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)

Peak

-to-P

eak

Jitte

r (ps

)

T = -5 CT = 25 CT = 85 C

Figure 9. Output DOUTp deterministic jitter as measured on the oscilloscope (ps pk-pk) vs. VEE and temperature. Source is 25 Gbps 27–1 PRBS pattern. Measurement includes deterministic jitter of source and test equipment.

Random Jitter (outp) vs. Supply with Temp. as parameter

185

190

195

200

205

210

215

220

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)R

ando

m J

itter

(RM

S in

fs)

T = -5 CT = 25 CT = 85 C

Figure 10. Output DOUTp random jitter (ps RMS) vs. VEE and temperature. Source is 25 Gbps 27–1 PRBS pattern. Measurement includes random jitter of source and test equipment.

Rise Time (OutP) vs. Supply with Temperature as parameter

14.0

14.5

15.0

15.5

16.0

16.5

17.0

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)

Ris

e Ti

me

(Out

P) (p

s)

T = -5 CT = 25 CT = 85 C

Figure 11. Output DOUTp rise time (ps) vs. VEE and temperature. Source is 25 Gbps 1010… pattern.

Phase Margin vs. Supply with Temperature as parameter

310312

314316

318320

322324

326328

330

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Power supply (V)

Phas

e M

argi

n (d

egre

es) T = -5 C

T = 25 CT = 85 C

Figure 12. Analog input to clock input phase margin (degrees) vs. VEE and temperature. Source is 25 Gbps 27–1 PRBS pattern.



Hysteresis Characteristics

Delta VOUT versus Delta VIN

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

-10 -5 0 5 10

Delta Vin (mV)

Del

ta V

out (

V)

-5 C25 C55 C85 C

Figure 13. Typical analog input (IN+) DC hysteresis on the 25706CP. For this measurement, the offset voltage was calculated from the swept data by taking the average of the threshold for the positive and negative sweep. The difference between the thresholds is the hysteresis.

Hysteresis versus Soak Time

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

16.00

18.00

20.00

0.001 0.01 0.1 1 10 100

Data SoakD

ata

Hys

tere

sis

(mV)

1000 100 10 1 0.1 0.01(µs)

(Mbps)

Figure 14. Analog input (IN+) thermal hysteresis on the 25706CP is shown as a function of input soak time in µs (and equivalent data rate in Mb/s). Input used was a 1010… square wave pattern at varying data rates. Clock frequency set to 1 GHz.

S-Parameter Characteristics

Analog Input S11 Amplitude

-40

-35

-30

-25

-20

-15

-10

-5

0

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Frequency (GHz)

S11

am

plitu

de (d

B)

Figure 15. Input Return Loss under typical VEE and temperature conditions.

Data Output S22 Amplitude

-40

-35

-30

-25

-20

-15

-10

-5

0

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Frequency (GHz)

S22

am

plitu

de (d

B)

Figure 16. Output Return Loss under typical VEE and temperature conditions.


Die Pad Layout

GND

10

1.280 mm

0.98

0 m

m

65 ± 5 µm(4 sides)

IN-

3

DOUTp

16

CLKINn

9

CLKINp

8

IN+

4

DOUTn

15

VEE

24

VEE

23

GND

22

GND

21

VEE

20

VEE

19

GND

18

GND

17

GND

14

GND

13

VEE

11

VEE

12

GND

1

GND

2

GND

5

GND

6

GND

7

Notes:

1. Numbers correspond to 100 µm squares on 150 µm pitch. 2. Pad outer dimensions fit either to squares or to rectangles enclosing two adjacent squares. 3. Die thickness = 150 ± 10 µm.

Name Pad Square

Number Description Function

IN- 3 Inverting analog input. Internally terminated 65 Ω to GND. Input

IN+ 4 Non-inverting analog input. Internally terminated 65 Ω to GND. Input

CLKINp 8 Non-inverting clock input. Analog input is latched onto the rising edge of this input signal. Internally terminated 50 Ω to GND. Input

CLKINn 9 Inverting clock input. Analog input is latched onto the falling edge of this input signal. Internally terminated 50 Ω to GND. Input

DOUTp 16 Non-inverting data output. Back terminated 60 Ω to GND. Always terminate to 50 Ω to GND.

Output

DOUTn 15 Inverting data output. Back terminated 60 Ω to GND. Always terminate to 50 Ω to GND.

Output

GND 1, 2, 5, 6, 7, 10, 13, 14, 17, 18,

21, 22 Ground. Supply

VEE 11, 12, 19, 20,

23, 24 Power Supply: Connect to –3.3 V. Supply


Die Pad Locations For dimensioning purposes, reference origin (0, 0) is the lower left corner of the lower left pad.

Pad Lower Left Corner

Pad # Signal X Y

1 GND 0 750

2 GND 0 600

3 IN- 0 450

4 IN+ 0 300

5 GND 0 150

6 GND 0 0

7 GND 150 0

8 CLKINp 300 0

9 CLKINn 450 0

10 GND 600 0

11 VEE 750 0

12 VEE 900 0

13 GND 1050 0

14 GND 1050 150

15 DOUTn 1050 300

16 DOUTp 1050 450

17 GND 1050 600

18 GND 1050 750

19 VEE 900 750

20 VEE 750 750

21 GND 600 750

22 GND 450 750

23 VEE 300 750

24 VEE 150 750


LGA Pinout

Name Pin Description Function

IN- 5 Inverting analog input. Internally terminated 65 Ω to GND. Input

IN+ 3 Non-inverting analog input. Internally terminated 65 Ω to GND. Input

CLKINp 26 Non-inverting clock input. Analog input is latched onto the rising edge of this input signal. Internally terminated 50 Ω to GND.

Input

CLKINn 24 Inverting clock input. Analog input is latched onto the falling edge of this input signal. Internally terminated 50 Ω to GND.

Input

DOUTp 17 Non-inverting data output. Back terminated 60 Ω to GND. Always terminate to 50 Ω to GND.

Output

DOUTn 19 Inverting data output. Back terminated 60 Ω to GND. Always terminate to 50 Ω to GND.

Output

GND 1, 2, 4, 6, 7, 9, 12, 13, 16, 18, 20, 21, 23, 25,

27, Paddle Ground Supply

VEE 10, 11, 22 Power Supply: Connect to –3.3 V Supply

NC 8, 14, 15, 28 Not Connected NC


LGA Package Mechanical Drawing

Top View

Side View

Side View Bottom View


Order Information

Part No. Description

25706CP-S01D 25 GHz Latched Comparator (–3.3 V Supply) – Die

25706CP-S01L 25 GHz Latched Comparator (–3.3 V Supply) in LGA Package

25706CP-S01LEVB 25 GHz Latched Comparator (–3.3 V Supply) in LGA Package on an Evaluation Board with SMA Connectors

Contact Information

Inphi Corporation 2393 Townsgate Road, Suite 101 Westlake Village, CA 91361

• Phone: (805) 446-5100 • Fax: (805) 446-5189 • E-mail: [email protected]

Visit us on the Internet at: http://www.inphi-corp.com

For each customer application, customer’s technical experts must validate all parameters. Inphi Corporation reserves the right to change product specifications contained herein without prior notice. No liability is assumed as a result of the use or application of this product. No circuit patent licenses are implied. Contact Inphi Corporation’s marketing department for the latest information regarding this product. Limited Qualification Notification NOTE: The 25706CP has been tested to meet the DC and AC electrical specifications outlined in this data sheet and a characterization report is available. While the 25706CP has not undergone full qualification testing (i.e. it has not been subjected to high temperature operation life test), a number of other products fabricated in the same semiconductor process and packaged in the same ceramic LGA package have completed full qualification testing and have been demonstrated to be reliable. Contact Inphi Corporation for more details. Updates To Version 1.0

1. Corrected block diagram on page 1. 2. Changed DC electrical specification tables on page 3 based upon recommendations in the

characterization report. Specs changed are: Input VIH, Input VIL, Input VOS, Input ∆VOS/∆T, Clock Input VIL, Output DOUT, Output VOH, Output VOCM.

3. Changed AC electrical specification tables on page 4 based upon recommendations in the characterization report. Specs changed are: Clock CPM, Output RLOUT.

4. Added figure 1 – minimum output return loss specification – on page 5. 5. Added data on DC hysteresis (spec on page 3 and new diagram on figure 12). 6. Clarified previous “hysteresis” spec entries as “thermal hysteresis” (page 4 and figure 13). 7. Removed “Hysteresis Specification” section – moved to the application note instead.

mailto:[email protected]

http://www.inphi-corp.com/

25706cp 25 ghz latched comparator data...

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